From: William Qiu <william.qiu@starfivetech.com> To: <devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Emil Renner Berthing <kernel@esmil.dk>, Ziv Xu <ziv.xu@starfivetech.com>, William Qiu <william.qiu@starfivetech.com> Subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI Date: Fri, 2 Jun 2023 16:49:24 +0800 [thread overview] Message-ID: <20230602084925.215411-3-william.qiu@starfivetech.com> (raw) In-Reply-To: <20230602084925.215411-1-william.qiu@starfivetech.com> Add QSPI clock operation in device probe. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> --- drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 6ddb2dfc0f00..21788472c7fb 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -63,6 +63,8 @@ struct cqspi_st { struct platform_device *pdev; struct spi_master *master; struct clk *clk; + struct clk_bulk_data *clks; + unsigned int num_clks; unsigned int sclk; void __iomem *iobase; @@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev) } if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks); + if (cqspi->num_clks < 0) { + dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks); + return -EINVAL; + } + + ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); + if (ret) + dev_err(dev, "Cannot enable clock clks\n"); + rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret = PTR_ERR(rstc_ref); @@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev) clk_disable_unprepare(cqspi->clk); + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) + clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } @@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev) clk_disable_unprepare(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) + clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); + return ret; } @@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev) struct spi_master *master = dev_get_drvdata(dev); clk_prepare_enable(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) + clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); cqspi_wait_idle(cqspi); cqspi_controller_init(cqspi); -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: William Qiu <william.qiu@starfivetech.com> To: <devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Emil Renner Berthing <kernel@esmil.dk>, Ziv Xu <ziv.xu@starfivetech.com>, William Qiu <william.qiu@starfivetech.com> Subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI Date: Fri, 2 Jun 2023 16:49:24 +0800 [thread overview] Message-ID: <20230602084925.215411-3-william.qiu@starfivetech.com> (raw) In-Reply-To: <20230602084925.215411-1-william.qiu@starfivetech.com> Add QSPI clock operation in device probe. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> --- drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 6ddb2dfc0f00..21788472c7fb 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -63,6 +63,8 @@ struct cqspi_st { struct platform_device *pdev; struct spi_master *master; struct clk *clk; + struct clk_bulk_data *clks; + unsigned int num_clks; unsigned int sclk; void __iomem *iobase; @@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev) } if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks); + if (cqspi->num_clks < 0) { + dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks); + return -EINVAL; + } + + ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); + if (ret) + dev_err(dev, "Cannot enable clock clks\n"); + rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret = PTR_ERR(rstc_ref); @@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev) clk_disable_unprepare(cqspi->clk); + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) + clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } @@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev) clk_disable_unprepare(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) + clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); + return ret; } @@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev) struct spi_master *master = dev_get_drvdata(dev); clk_prepare_enable(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) + clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); cqspi_wait_idle(cqspi); cqspi_controller_init(cqspi); -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-06-02 8:50 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-02 8:49 [PATCH v2 0/3] Add initialization of clock for StarFive JH7110 SoC William Qiu 2023-06-02 8:49 ` William Qiu 2023-06-02 8:49 ` [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks " William Qiu 2023-06-02 8:49 ` William Qiu 2023-06-02 18:02 ` Conor Dooley 2023-06-02 18:02 ` Conor Dooley 2023-06-06 3:34 ` William Qiu 2023-06-06 3:34 ` William Qiu 2023-06-06 12:43 ` Krzysztof Kozlowski 2023-06-06 12:43 ` Krzysztof Kozlowski 2023-06-19 7:27 ` William Qiu 2023-06-19 7:27 ` William Qiu 2023-06-02 8:49 ` William Qiu [this message] 2023-06-02 8:49 ` [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI William Qiu 2023-06-02 12:33 ` kernel test robot 2023-06-02 12:33 ` kernel test robot 2023-06-06 3:32 ` William Qiu 2023-06-06 3:32 ` William Qiu 2023-06-15 7:57 ` kernel test robot 2023-06-02 8:49 ` [PATCH v2 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC William Qiu 2023-06-02 8:49 ` William Qiu 2023-08-04 19:04 ` (subset) [PATCH v2 0/3] Add initialization of clock " Mark Brown 2023-08-04 19:04 ` Mark Brown 2023-06-03 22:58 [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI kernel test robot
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