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From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: andi.shyti@intel.com, chris.p.wilson@linux.intel.com,
	tomasz.mistat@intel.com, jonathan.cavitt@intel.com,
	rodrigo.vivi@intel.com, gregory.f.germano@intel.com,
	matthew.d.roper@intel.com, nirmoy.das@intel.com
Subject: [Intel-gfx] [PATCH v9 3/3] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
Date: Tue, 12 Sep 2023 07:19:31 -0700	[thread overview]
Message-ID: <20230912141931.1803917-4-jonathan.cavitt@intel.com> (raw)
In-Reply-To: <20230912141931.1803917-1-jonathan.cavitt@intel.com>

Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 2e06bea73297a..823c6c40213f5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -124,6 +124,9 @@
 #define RING_INDIRECT_CTX(base)			_MMIO((base) + 0x1c4) /* gen8+ */
 #define RING_INDIRECT_CTX_OFFSET(base)		_MMIO((base) + 0x1c8) /* gen8+ */
 #define ECOSKPD(base)				_MMIO((base) + 0x1d0)
+#define   XEHP_BLITTER_SCHEDULING_MODE_MASK	REG_GENMASK(12, 11)
+#define   XEHP_BLITTER_ROUND_ROBIN_MODE		\
+		REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1)
 #define   ECO_CONSTANT_BUFFER_SR_DISABLE	REG_BIT(4)
 #define   ECO_GATING_CX_ONLY			REG_BIT(3)
 #define   GEN6_BLITTER_FBC_NOTIFY		REG_BIT(3)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 70071ead0659c..3f8177bf5de70 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2777,6 +2777,11 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			 RING_SEMA_WAIT_POLL(engine->mmio_base),
 			 1);
 	}
+	/* Wa_16018031267, Wa_16018063123 */
+	if (NEEDS_FASTCOLOR_BLT_WABB(engine))
+		wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),
+				    XEHP_BLITTER_SCHEDULING_MODE_MASK,
+				    XEHP_BLITTER_ROUND_ROBIN_MODE);
 }
 
 static void
-- 
2.25.1


  parent reply	other threads:[~2023-09-12 14:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-12 14:19 [Intel-gfx] [PATCH v9 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt
2023-09-12 14:19 ` [Intel-gfx] [PATCH v9 1/3] drm/i915: Reserve some kernel space per vm Jonathan Cavitt
2023-09-12 14:19 ` [Intel-gfx] [PATCH v9 2/3] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 Jonathan Cavitt
2023-09-12 14:19 ` Jonathan Cavitt [this message]
2023-09-12 20:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply " Patchwork
2023-09-12 20:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-12 20:40 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-09-13 21:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
2023-09-13 21:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-13 21:37 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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