From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 09/12] clk: renesas: r9a07g044: Add DSI clock and reset entries
Date: Thu, 7 Dec 2023 10:55:05 +0000 [thread overview]
Message-ID: <20231207105508.171162-10-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20231207105508.171162-1-biju.das.jz@bp.renesas.com>
commit 67f80edf8390fd8201bb285fe2b55df9e2e5edbe upstream.
Add DSI clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index e27a8e50fac1..ab546d57cb60 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
};
static const struct {
- struct rzg2l_mod_clk common[64];
+ struct rzg2l_mod_clk common[70];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
@@ -240,6 +240,18 @@ static const struct {
0x558, 1),
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
0x558, 2),
+ DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
+ 0x568, 0),
+ DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
+ 0x568, 1),
+ DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
+ 0x568, 2),
+ DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
+ 0x568, 3),
+ DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
+ 0x568, 4),
+ DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
+ 0x568, 5),
DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
0x56c, 0),
DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
@@ -341,6 +353,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
+ DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
+ DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
+ DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
--
2.25.1
next prev parent reply other threads:[~2023-12-07 10:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-07 10:54 [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 01/12] clk: renesas: rzg2l: Add FOUTPOSTDIV " Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 02/12] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 03/12] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 04/12] clk: renesas: r9a07g044: Add M1 clock support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 05/12] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 06/12] clk: renesas: r9a07g044: Add M3 Clock support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 07/12] clk: renesas: r9a07g044: Add M4 " Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 08/12] clk: renesas: r9a07g044: Add LCDC clock and reset entries Biju Das
2023-12-07 10:55 ` Biju Das [this message]
2023-12-07 10:55 ` [PATCH 5.10.y-cip 10/12] clk: renesas: r9a07g044: Add GPT clock and reset entry Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 11/12] clk: renesas: r9a07g044: Add POEG clock and reset entries Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 12/12] clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write Biju Das
2023-12-07 11:17 ` [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support Pavel Machek
2023-12-07 13:49 ` nobuhiro1.iwamatsu
2023-12-07 18:03 ` Pavel Machek
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