From: Leonardo Bras <leobras@redhat.com> To: Will Deacon <will@kernel.org>, Peter Zijlstra <peterz@infradead.org>, Boqun Feng <boqun.feng@gmail.com>, Mark Rutland <mark.rutland@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>, Andrea Parri <parri.andrea@gmail.com>, Geert Uytterhoeven <geert@linux-m68k.org>, Ingo Molnar <mingo@kernel.org>, Andrzej Hajda <andrzej.hajda@intel.com> Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v1 4/5] riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2 Date: Wed, 3 Jan 2024 13:32:02 -0300 [thread overview] Message-ID: <20240103163203.72768-6-leobras@redhat.com> (raw) In-Reply-To: <20240103163203.72768-2-leobras@redhat.com> cmpxchg for variables of size 1-byte and 2-bytes is not yet available for riscv, even though its present in other architectures such as arm64 and x86. This could lead to not being able to implement some locking mechanisms or requiring some rework to make it work properly. Implement 1-byte and 2-bytes cmpxchg in order to achieve parity with other architectures. Signed-off-by: Leonardo Bras <leobras@redhat.com> Tested-by: Guo Ren <guoren@kernel.org> --- arch/riscv/include/asm/cmpxchg.h | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index e3e0ac7ba061b..ac9d0eeb74e67 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -72,6 +72,35 @@ * indicated by comparing RETURN with OLD. */ +#define __arch_cmpxchg_masked(sc_sfx, prepend, append, r, p, o, n) \ +({ \ + u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \ + ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \ + ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \ + << __s; \ + ulong __newx = (ulong)(n) << __s; \ + ulong __oldx = (ulong)(o) << __s; \ + ulong __retx; \ + ulong __rc; \ + \ + __asm__ __volatile__ ( \ + prepend \ + "0: lr.w %0, %2\n" \ + " and %1, %0, %z5\n" \ + " bne %1, %z3, 1f\n" \ + " and %1, %0, %z6\n" \ + " or %1, %1, %z4\n" \ + " sc.w" sc_sfx " %1, %1, %2\n" \ + " bnez %1, 0b\n" \ + append \ + "1:\n" \ + : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \ + : "rJ" ((long)__oldx), "rJ" (__newx), \ + "rJ" (__mask), "rJ" (~__mask) \ + : "memory"); \ + \ + r = (__typeof__(*(p)))((__retx & __mask) >> __s); \ +}) #define __arch_cmpxchg(lr_sfx, sc_sfx, prepend, append, r, p, co, o, n) \ ({ \ @@ -98,6 +127,11 @@ __typeof__(*(__ptr)) __ret; \ \ switch (sizeof(*__ptr)) { \ + case 1: \ + case 2: \ + __arch_cmpxchg_masked(sc_sfx, prepend, append, \ + __ret, __ptr, __old, __new); \ + break; \ case 4: \ __arch_cmpxchg(".w", ".w" sc_sfx, prepend, append, \ __ret, __ptr, (long), __old, __new); \ -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Leonardo Bras <leobras@redhat.com> To: Will Deacon <will@kernel.org>, Peter Zijlstra <peterz@infradead.org>, Boqun Feng <boqun.feng@gmail.com>, Mark Rutland <mark.rutland@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>, Andrea Parri <parri.andrea@gmail.com>, Geert Uytterhoeven <geert@linux-m68k.org>, Ingo Molnar <mingo@kernel.org>, Andrzej Hajda <andrzej.hajda@intel.com> Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v1 4/5] riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2 Date: Wed, 3 Jan 2024 13:32:02 -0300 [thread overview] Message-ID: <20240103163203.72768-6-leobras@redhat.com> (raw) In-Reply-To: <20240103163203.72768-2-leobras@redhat.com> cmpxchg for variables of size 1-byte and 2-bytes is not yet available for riscv, even though its present in other architectures such as arm64 and x86. This could lead to not being able to implement some locking mechanisms or requiring some rework to make it work properly. Implement 1-byte and 2-bytes cmpxchg in order to achieve parity with other architectures. Signed-off-by: Leonardo Bras <leobras@redhat.com> Tested-by: Guo Ren <guoren@kernel.org> --- arch/riscv/include/asm/cmpxchg.h | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index e3e0ac7ba061b..ac9d0eeb74e67 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -72,6 +72,35 @@ * indicated by comparing RETURN with OLD. */ +#define __arch_cmpxchg_masked(sc_sfx, prepend, append, r, p, o, n) \ +({ \ + u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \ + ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \ + ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \ + << __s; \ + ulong __newx = (ulong)(n) << __s; \ + ulong __oldx = (ulong)(o) << __s; \ + ulong __retx; \ + ulong __rc; \ + \ + __asm__ __volatile__ ( \ + prepend \ + "0: lr.w %0, %2\n" \ + " and %1, %0, %z5\n" \ + " bne %1, %z3, 1f\n" \ + " and %1, %0, %z6\n" \ + " or %1, %1, %z4\n" \ + " sc.w" sc_sfx " %1, %1, %2\n" \ + " bnez %1, 0b\n" \ + append \ + "1:\n" \ + : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \ + : "rJ" ((long)__oldx), "rJ" (__newx), \ + "rJ" (__mask), "rJ" (~__mask) \ + : "memory"); \ + \ + r = (__typeof__(*(p)))((__retx & __mask) >> __s); \ +}) #define __arch_cmpxchg(lr_sfx, sc_sfx, prepend, append, r, p, co, o, n) \ ({ \ @@ -98,6 +127,11 @@ __typeof__(*(__ptr)) __ret; \ \ switch (sizeof(*__ptr)) { \ + case 1: \ + case 2: \ + __arch_cmpxchg_masked(sc_sfx, prepend, append, \ + __ret, __ptr, __old, __new); \ + break; \ case 4: \ __arch_cmpxchg(".w", ".w" sc_sfx, prepend, append, \ __ret, __ptr, (long), __old, __new); \ -- 2.43.0
next prev parent reply other threads:[~2024-01-03 16:33 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-03 16:31 [PATCH v1 0/5] Rework & improve riscv cmpxchg.h and atomic.h Leonardo Bras 2024-01-03 16:31 ` Leonardo Bras 2024-01-03 16:31 ` [PATCH v1 1/5] riscv/cmpxchg: Deduplicate xchg() asm functions Leonardo Bras 2024-01-03 16:31 ` Leonardo Bras 2024-01-04 19:53 ` Boqun Feng 2024-01-04 19:53 ` Boqun Feng 2024-01-04 20:41 ` Leonardo Bras 2024-01-04 20:41 ` Leonardo Bras 2024-01-04 21:51 ` Boqun Feng 2024-01-04 21:51 ` Boqun Feng 2024-01-05 4:45 ` Leonardo Bras 2024-01-05 4:45 ` Leonardo Bras 2024-01-05 5:18 ` Boqun Feng 2024-01-05 5:18 ` Boqun Feng 2024-01-05 6:59 ` Leonardo Bras 2024-01-05 6:59 ` Leonardo Bras 2024-01-13 6:54 ` kernel test robot 2024-01-13 6:54 ` kernel test robot 2024-01-16 19:27 ` Leonardo Bras 2024-01-16 19:27 ` Leonardo Bras 2024-01-03 16:32 ` [PATCH v1 2/5] riscv/cmpxchg: Deduplicate cmpxchg() asm and macros Leonardo Bras 2024-01-03 16:32 ` Leonardo Bras 2024-01-03 16:32 ` [PATCH v1 3/5] riscv/atomic.h : Deduplicate arch_atomic.* Leonardo Bras 2024-01-03 16:32 ` Leonardo Bras 2024-01-03 16:32 ` Leonardo Bras [this message] 2024-01-03 16:32 ` [PATCH v1 4/5] riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2 Leonardo Bras 2024-01-03 16:32 ` [PATCH v1 5/5] riscv/cmpxchg: Implement xchg " Leonardo Bras 2024-01-03 16:32 ` Leonardo Bras 2024-01-03 16:34 ` [PATCH v1 0/5] Rework & improve riscv cmpxchg.h and atomic.h Leonardo Bras 2024-01-03 16:34 ` Leonardo Bras 2024-04-10 14:20 ` patchwork-bot+linux-riscv 2024-04-10 14:20 ` patchwork-bot+linux-riscv
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