From: Leonardo Bras <leobras@redhat.com> To: Leonardo Bras <leobras@redhat.com> Cc: Will Deacon <will@kernel.org>, Peter Zijlstra <peterz@infradead.org>, Boqun Feng <boqun.feng@gmail.com>, Mark Rutland <mark.rutland@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Andrea Parri <parri.andrea@gmail.com>, Geert Uytterhoeven <geert@linux-m68k.org>, Ingo Molnar <mingo@kernel.org>, Andrzej Hajda <andrzej.hajda@intel.com>, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v1 0/5] Rework & improve riscv cmpxchg.h and atomic.h Date: Wed, 3 Jan 2024 13:34:43 -0300 [thread overview] Message-ID: <ZZWMox3D2GHX0Tzr@LeoBras> (raw) In-Reply-To: <20240103163203.72768-2-leobras@redhat.com> On Wed, Jan 03, 2024 at 01:31:58PM -0300, Leonardo Bras wrote: > While studying riscv's cmpxchg.h file, I got really interested in > understanding how RISCV asm implemented the different versions of > {cmp,}xchg. > > When I understood the pattern, it made sense for me to remove the > duplications and create macros to make it easier to understand what exactly > changes between the versions: Instruction sufixes & barriers. > > Also, did the same kind of work on atomic.c. > > After that, I noted both cmpxchg and xchg only accept variables of > size 4 and 8, compared to x86 and arm64 which do 1,2,4,8. > > Now that deduplication is done, it is quite direct to implement them > for variable sizes 1 and 2, so I did it. Then Guo Ren already presented > me some possible users :) > > I did compare the generated asm on a test.c that contained usage for every > changed function, and could not detect any change on patches 1 + 2 + 3 > compared with upstream. > > Pathes 4 & 5 were compiled-tested, merged with guoren/qspinlock_v11 and > booted just fine with qemu -machine virt -append "qspinlock". > > (tree: https://gitlab.com/LeoBras/linux/-/commits/guo_qspinlock_v11) > > Latest tests happened based on this tree: > https://github.com/guoren83/linux/tree/qspinlock_v12 > > Thanks! > Leo > > Changes since squashed cmpxchg RFCv5: > - Resend as v1 Oh, forgot to mention: I added some of Reviewed-by that were missing. Thanks Guo Ren! > https://lore.kernel.org/all/20230810040349.92279-2-leobras@redhat.com/ > > Changes since squashed cmpxchg RFCv4: > - Added (__typeof__(*(p))) before returning from {cmp,}xchg, as done > in current upstream, (possibly) fixing the bug from kernel test robot > https://lore.kernel.org/all/20230809021311.1390578-2-leobras@redhat.com/ > > Changes since squashed cmpxchg RFCv3: > - Fixed bug on cmpxchg macro for var size 1 & 2: now working > - Macros for var size 1 & 2's lr.w and sc.w now are guaranteed to receive > input of a 32-bit aligned address > - Renamed internal macros from _mask to _masked for patches 4 & 5 > - __rc variable on macros for var size 1 & 2 changed from register to ulong > https://lore.kernel.org/all/20230804084900.1135660-2-leobras@redhat.com/ > > Changes since squashed cmpxchg RFCv2: > - Removed rc parameter from the new macro: it can be internal to the macro > - 2 new patches: cmpxchg size 1 and 2, xchg size 1 and 2 > https://lore.kernel.org/all/20230803051401.710236-2-leobras@redhat.com/ > > Changes since squashed cmpxchg RFCv1: > - Unified with atomic.c patchset > - Rebased on top of torvalds/master (thanks Andrea Parri!) > - Removed helper macros that were not being used elsewhere in the kernel. > https://lore.kernel.org/all/20230419062505.257231-1-leobras@redhat.com/ > https://lore.kernel.org/all/20230406082018.70367-1-leobras@redhat.com/ > > Changes since (cmpxchg) RFCv3: > - Squashed the 6 original patches in 2: one for cmpxchg and one for xchg > https://lore.kernel.org/all/20230404163741.2762165-1-leobras@redhat.com/ > > Changes since (cmpxchg) RFCv2: > - Fixed macros that depend on having a local variable with a magic name > - Previous cast to (long) is now only applied on 4-bytes cmpxchg > https://lore.kernel.org/all/20230321074249.2221674-1-leobras@redhat.com/ > > Changes since (cmpxchg) RFCv1: > - Fixed patch 4/6 suffix from 'w.aqrl' to '.w.aqrl', to avoid build error > https://lore.kernel.org/all/20230318080059.1109286-1-leobras@redhat.com/ > > Leonardo Bras (5): > riscv/cmpxchg: Deduplicate xchg() asm functions > riscv/cmpxchg: Deduplicate cmpxchg() asm and macros > riscv/atomic.h : Deduplicate arch_atomic.* > riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2 > riscv/cmpxchg: Implement xchg for variables of size 1 and 2 > > arch/riscv/include/asm/atomic.h | 164 ++++++------- > arch/riscv/include/asm/cmpxchg.h | 404 ++++++++++--------------------- > 2 files changed, 200 insertions(+), 368 deletions(-) > > > base-commit: 610a9b8f49fbcf1100716370d3b5f6f884a2835a > -- > 2.43.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Leonardo Bras <leobras@redhat.com> To: Leonardo Bras <leobras@redhat.com> Cc: Will Deacon <will@kernel.org>, Peter Zijlstra <peterz@infradead.org>, Boqun Feng <boqun.feng@gmail.com>, Mark Rutland <mark.rutland@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Andrea Parri <parri.andrea@gmail.com>, Geert Uytterhoeven <geert@linux-m68k.org>, Ingo Molnar <mingo@kernel.org>, Andrzej Hajda <andrzej.hajda@intel.com>, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v1 0/5] Rework & improve riscv cmpxchg.h and atomic.h Date: Wed, 3 Jan 2024 13:34:43 -0300 [thread overview] Message-ID: <ZZWMox3D2GHX0Tzr@LeoBras> (raw) In-Reply-To: <20240103163203.72768-2-leobras@redhat.com> On Wed, Jan 03, 2024 at 01:31:58PM -0300, Leonardo Bras wrote: > While studying riscv's cmpxchg.h file, I got really interested in > understanding how RISCV asm implemented the different versions of > {cmp,}xchg. > > When I understood the pattern, it made sense for me to remove the > duplications and create macros to make it easier to understand what exactly > changes between the versions: Instruction sufixes & barriers. > > Also, did the same kind of work on atomic.c. > > After that, I noted both cmpxchg and xchg only accept variables of > size 4 and 8, compared to x86 and arm64 which do 1,2,4,8. > > Now that deduplication is done, it is quite direct to implement them > for variable sizes 1 and 2, so I did it. Then Guo Ren already presented > me some possible users :) > > I did compare the generated asm on a test.c that contained usage for every > changed function, and could not detect any change on patches 1 + 2 + 3 > compared with upstream. > > Pathes 4 & 5 were compiled-tested, merged with guoren/qspinlock_v11 and > booted just fine with qemu -machine virt -append "qspinlock". > > (tree: https://gitlab.com/LeoBras/linux/-/commits/guo_qspinlock_v11) > > Latest tests happened based on this tree: > https://github.com/guoren83/linux/tree/qspinlock_v12 > > Thanks! > Leo > > Changes since squashed cmpxchg RFCv5: > - Resend as v1 Oh, forgot to mention: I added some of Reviewed-by that were missing. Thanks Guo Ren! > https://lore.kernel.org/all/20230810040349.92279-2-leobras@redhat.com/ > > Changes since squashed cmpxchg RFCv4: > - Added (__typeof__(*(p))) before returning from {cmp,}xchg, as done > in current upstream, (possibly) fixing the bug from kernel test robot > https://lore.kernel.org/all/20230809021311.1390578-2-leobras@redhat.com/ > > Changes since squashed cmpxchg RFCv3: > - Fixed bug on cmpxchg macro for var size 1 & 2: now working > - Macros for var size 1 & 2's lr.w and sc.w now are guaranteed to receive > input of a 32-bit aligned address > - Renamed internal macros from _mask to _masked for patches 4 & 5 > - __rc variable on macros for var size 1 & 2 changed from register to ulong > https://lore.kernel.org/all/20230804084900.1135660-2-leobras@redhat.com/ > > Changes since squashed cmpxchg RFCv2: > - Removed rc parameter from the new macro: it can be internal to the macro > - 2 new patches: cmpxchg size 1 and 2, xchg size 1 and 2 > https://lore.kernel.org/all/20230803051401.710236-2-leobras@redhat.com/ > > Changes since squashed cmpxchg RFCv1: > - Unified with atomic.c patchset > - Rebased on top of torvalds/master (thanks Andrea Parri!) > - Removed helper macros that were not being used elsewhere in the kernel. > https://lore.kernel.org/all/20230419062505.257231-1-leobras@redhat.com/ > https://lore.kernel.org/all/20230406082018.70367-1-leobras@redhat.com/ > > Changes since (cmpxchg) RFCv3: > - Squashed the 6 original patches in 2: one for cmpxchg and one for xchg > https://lore.kernel.org/all/20230404163741.2762165-1-leobras@redhat.com/ > > Changes since (cmpxchg) RFCv2: > - Fixed macros that depend on having a local variable with a magic name > - Previous cast to (long) is now only applied on 4-bytes cmpxchg > https://lore.kernel.org/all/20230321074249.2221674-1-leobras@redhat.com/ > > Changes since (cmpxchg) RFCv1: > - Fixed patch 4/6 suffix from 'w.aqrl' to '.w.aqrl', to avoid build error > https://lore.kernel.org/all/20230318080059.1109286-1-leobras@redhat.com/ > > Leonardo Bras (5): > riscv/cmpxchg: Deduplicate xchg() asm functions > riscv/cmpxchg: Deduplicate cmpxchg() asm and macros > riscv/atomic.h : Deduplicate arch_atomic.* > riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2 > riscv/cmpxchg: Implement xchg for variables of size 1 and 2 > > arch/riscv/include/asm/atomic.h | 164 ++++++------- > arch/riscv/include/asm/cmpxchg.h | 404 ++++++++++--------------------- > 2 files changed, 200 insertions(+), 368 deletions(-) > > > base-commit: 610a9b8f49fbcf1100716370d3b5f6f884a2835a > -- > 2.43.0 >
next prev parent reply other threads:[~2024-01-03 16:35 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-03 16:31 [PATCH v1 0/5] Rework & improve riscv cmpxchg.h and atomic.h Leonardo Bras 2024-01-03 16:31 ` Leonardo Bras 2024-01-03 16:31 ` [PATCH v1 1/5] riscv/cmpxchg: Deduplicate xchg() asm functions Leonardo Bras 2024-01-03 16:31 ` Leonardo Bras 2024-01-04 19:53 ` Boqun Feng 2024-01-04 19:53 ` Boqun Feng 2024-01-04 20:41 ` Leonardo Bras 2024-01-04 20:41 ` Leonardo Bras 2024-01-04 21:51 ` Boqun Feng 2024-01-04 21:51 ` Boqun Feng 2024-01-05 4:45 ` Leonardo Bras 2024-01-05 4:45 ` Leonardo Bras 2024-01-05 5:18 ` Boqun Feng 2024-01-05 5:18 ` Boqun Feng 2024-01-05 6:59 ` Leonardo Bras 2024-01-05 6:59 ` Leonardo Bras 2024-01-13 6:54 ` kernel test robot 2024-01-13 6:54 ` kernel test robot 2024-01-16 19:27 ` Leonardo Bras 2024-01-16 19:27 ` Leonardo Bras 2024-01-03 16:32 ` [PATCH v1 2/5] riscv/cmpxchg: Deduplicate cmpxchg() asm and macros Leonardo Bras 2024-01-03 16:32 ` Leonardo Bras 2024-01-03 16:32 ` [PATCH v1 3/5] riscv/atomic.h : Deduplicate arch_atomic.* Leonardo Bras 2024-01-03 16:32 ` Leonardo Bras 2024-01-03 16:32 ` [PATCH v1 4/5] riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2 Leonardo Bras 2024-01-03 16:32 ` Leonardo Bras 2024-01-03 16:32 ` [PATCH v1 5/5] riscv/cmpxchg: Implement xchg " Leonardo Bras 2024-01-03 16:32 ` Leonardo Bras 2024-01-03 16:34 ` Leonardo Bras [this message] 2024-01-03 16:34 ` [PATCH v1 0/5] Rework & improve riscv cmpxchg.h and atomic.h Leonardo Bras 2024-04-10 14:20 ` patchwork-bot+linux-riscv 2024-04-10 14:20 ` patchwork-bot+linux-riscv
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