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From: Roger Pau Monne <roger.pau@citrix.com>
To: xen-devel@lists.xenproject.org
Cc: Roger Pau Monne <roger.pau@citrix.com>,
	Jan Beulich <jbeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: [PATCH 3/3] x86/intel: expose BHI_CTRL to guests
Date: Tue, 30 Jan 2024 10:14:00 +0100	[thread overview]
Message-ID: <20240130091400.50622-4-roger.pau@citrix.com> (raw)
In-Reply-To: <20240130091400.50622-1-roger.pau@citrix.com>

The CPUID feature bit signals the presence of the BHI_DIS_S control in
SPEC_CTRL MSR.

Note that those controls are not used by the hypervisor.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/msr.c                          | 1 +
 xen/include/public/arch-x86/cpufeatureset.h | 2 +-
 xen/tools/gen-cpuid.py                      | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index b3b4f75c021a..e0d57bce40ec 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -330,6 +330,7 @@ uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp)
             (cp->feat.rrsba_ctrl ? (SPEC_CTRL_RRSBA_DIS_U |
                                     SPEC_CTRL_RRSBA_DIS_S)
                                  : 0) |
+            (cp->feat.bhi_ctrl   ? SPEC_CTRL_BHI_DIS_S : 0) |
             0);
 }
 
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index bade4edab30c..be5c1b748e27 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -305,7 +305,7 @@ XEN_CPUFEATURE(INTEL_PSFD,         13*32+ 0) /*A  MSR_SPEC_CTRL.PSFD */
 XEN_CPUFEATURE(IPRED_CTRL,         13*32+ 1) /*A  MSR_SPEC_CTRL.IPRED_DIS_* */
 XEN_CPUFEATURE(RRSBA_CTRL,         13*32+ 2) /*A  MSR_SPEC_CTRL.RRSBA_DIS_* */
 XEN_CPUFEATURE(DDP_CTRL,           13*32+ 3) /*   MSR_SPEC_CTRL.DDP_DIS_U */
-XEN_CPUFEATURE(BHI_CTRL,           13*32+ 4) /*   MSR_SPEC_CTRL.BHI_DIS_S */
+XEN_CPUFEATURE(BHI_CTRL,           13*32+ 4) /*A  MSR_SPEC_CTRL.BHI_DIS_S */
 XEN_CPUFEATURE(MCDT_NO,            13*32+ 5) /*A  MCDT_NO */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 1c6d76244177..25d329ce486f 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -320,7 +320,7 @@ def crunch_numbers(state):
         # as dependent features simplifies Xen's logic, and prevents the guest
         # from seeing implausible configurations.
         IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS,
-                IPRED_CTRL, RRSBA_CTRL],
+                IPRED_CTRL, RRSBA_CTRL, BHI_CTRL],
         IBRS: [AMD_STIBP, AMD_SSBD, PSFD, AUTO_IBRS,
                IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE],
         IBPB: [IBPB_RET, SBPB, IBPB_BRTYPE],
-- 
2.43.0



  parent reply	other threads:[~2024-01-30  9:14 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-30  9:13 [PATCH 0/3] x86/intel: expose additional SPEC_CTRL MSR controls Roger Pau Monne
2024-01-30  9:13 ` [PATCH 1/3] x86/intel: expose IPRED_CTRL to guests Roger Pau Monne
2024-01-30 10:57   ` Jan Beulich
2024-01-30 12:06     ` Roger Pau Monné
2024-01-30 12:59       ` Jan Beulich
2024-01-30 14:35         ` Roger Pau Monné
2024-01-30 14:47           ` Jan Beulich
2024-01-30 15:01             ` Roger Pau Monné
2024-01-30 15:46         ` Andrew Cooper
2024-01-30  9:13 ` [PATCH 2/3] x86/intel: expose RRSBA_CTRL " Roger Pau Monne
2024-01-30  9:14 ` Roger Pau Monne [this message]
2024-01-30 10:27 ` [PATCH] XTF: tests SPEC_CTRL added bits Roger Pau Monne
2024-01-30 10:42   ` Jan Beulich
2024-01-30 11:46     ` Roger Pau Monné
2024-01-30 12:55       ` Jan Beulich
2024-01-30 15:02         ` Roger Pau Monné
2024-01-30 15:04           ` Andrew Cooper
2024-01-30 16:25 ` [PATCH 0/3] x86/intel: expose additional SPEC_CTRL MSR controls Andrew Cooper
2024-01-30 17:18   ` Roger Pau Monné

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