From: Jerome Brunet <jbrunet@baylibre.com> To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Neil Armstrong" <neil.armstrong@linaro.org>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org> Cc: Jerome Brunet <jbrunet@baylibre.com>, Kevin Hilman <khilman@baylibre.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao <junyi.zhao@amlogic.com> Subject: [PATCH v5 3/5] pwm: meson: generalize 4 inputs clock on meson8 pwm type Date: Wed, 21 Feb 2024 16:11:49 +0100 [thread overview] Message-ID: <20240221151154.26452-4-jbrunet@baylibre.com> (raw) In-Reply-To: <20240221151154.26452-1-jbrunet@baylibre.com> Meson8 pwm type always has 4 input clocks. Some inputs may be grounded, like in the AO domain of some SoCs. Drop the parent number parameter and make this is constant. This is also done to make the addition of generic meson8 compatible easier. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/pwm/pwm-meson.c | 53 +++++++++-------------------------------- 1 file changed, 11 insertions(+), 42 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 40a5b64c26f5..a02fdbc61256 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -60,7 +60,7 @@ #define MISC_A_EN BIT(0) #define MESON_NUM_PWMS 2 -#define MESON_MAX_MUX_PARENTS 4 +#define MESON_NUM_MUX_PARENTS 4 static struct meson_pwm_channel_data { u8 reg_offset; @@ -97,8 +97,7 @@ struct meson_pwm_channel { }; struct meson_pwm_data { - const char * const *parent_names; - unsigned int num_parents; + const char *const parent_names[MESON_NUM_MUX_PARENTS]; }; struct meson_pwm { @@ -339,62 +338,32 @@ static const struct pwm_ops meson_pwm_ops = { .get_state = meson_pwm_get_state, }; -static const char * const pwm_meson8b_parent_names[] = { - "xtal", NULL, "fclk_div4", "fclk_div3" -}; - static const struct meson_pwm_data pwm_meson8b_data = { - .parent_names = pwm_meson8b_parent_names, - .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names), + .parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" }, }; /* * Only the 2 first inputs of the GXBB AO PWMs are valid * The last 2 are grounded */ -static const char * const pwm_gxbb_ao_parent_names[] = { - "xtal", "clk81" -}; - static const struct meson_pwm_data pwm_gxbb_ao_data = { - .parent_names = pwm_gxbb_ao_parent_names, - .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), -}; - -static const char * const pwm_axg_ee_parent_names[] = { - "xtal", "fclk_div5", "fclk_div4", "fclk_div3" + .parent_names = { "xtal", "clk81", NULL, NULL }, }; static const struct meson_pwm_data pwm_axg_ee_data = { - .parent_names = pwm_axg_ee_parent_names, - .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), -}; - -static const char * const pwm_axg_ao_parent_names[] = { - "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" + .parent_names = { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" }, }; static const struct meson_pwm_data pwm_axg_ao_data = { - .parent_names = pwm_axg_ao_parent_names, - .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), -}; - -static const char * const pwm_g12a_ao_ab_parent_names[] = { - "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" + .parent_names = { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }, }; static const struct meson_pwm_data pwm_g12a_ao_ab_data = { - .parent_names = pwm_g12a_ao_ab_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names), -}; - -static const char * const pwm_g12a_ao_cd_parent_names[] = { - "xtal", "g12a_ao_clk81", + .parent_names = { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" }, }; static const struct meson_pwm_data pwm_g12a_ao_cd_data = { - .parent_names = pwm_g12a_ao_cd_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), + .parent_names = { "xtal", "g12a_ao_clk81", NULL, NULL }, }; static const struct of_device_id meson_pwm_matches[] = { @@ -437,13 +406,13 @@ MODULE_DEVICE_TABLE(of, meson_pwm_matches); static int meson_pwm_init_channels(struct pwm_chip *chip) { struct meson_pwm *meson = to_meson_pwm(chip); - struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {}; + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; struct device *dev = pwmchip_parent(chip); unsigned int i; char name[255]; int err; - for (i = 0; i < meson->data->num_parents; i++) { + for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) { mux_parent_data[i].index = -1; mux_parent_data[i].name = meson->data->parent_names[i]; } @@ -459,7 +428,7 @@ static int meson_pwm_init_channels(struct pwm_chip *chip) init.ops = &clk_mux_ops; init.flags = 0; init.parent_data = mux_parent_data; - init.num_parents = meson->data->num_parents; + init.num_parents = MESON_NUM_MUX_PARENTS; channel->mux.reg = meson->base + REG_MISC_AB; channel->mux.shift = -- 2.43.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com> To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Neil Armstrong" <neil.armstrong@linaro.org>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org> Cc: Jerome Brunet <jbrunet@baylibre.com>, Kevin Hilman <khilman@baylibre.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao <junyi.zhao@amlogic.com> Subject: [PATCH v5 3/5] pwm: meson: generalize 4 inputs clock on meson8 pwm type Date: Wed, 21 Feb 2024 16:11:49 +0100 [thread overview] Message-ID: <20240221151154.26452-4-jbrunet@baylibre.com> (raw) In-Reply-To: <20240221151154.26452-1-jbrunet@baylibre.com> Meson8 pwm type always has 4 input clocks. Some inputs may be grounded, like in the AO domain of some SoCs. Drop the parent number parameter and make this is constant. This is also done to make the addition of generic meson8 compatible easier. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/pwm/pwm-meson.c | 53 +++++++++-------------------------------- 1 file changed, 11 insertions(+), 42 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 40a5b64c26f5..a02fdbc61256 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -60,7 +60,7 @@ #define MISC_A_EN BIT(0) #define MESON_NUM_PWMS 2 -#define MESON_MAX_MUX_PARENTS 4 +#define MESON_NUM_MUX_PARENTS 4 static struct meson_pwm_channel_data { u8 reg_offset; @@ -97,8 +97,7 @@ struct meson_pwm_channel { }; struct meson_pwm_data { - const char * const *parent_names; - unsigned int num_parents; + const char *const parent_names[MESON_NUM_MUX_PARENTS]; }; struct meson_pwm { @@ -339,62 +338,32 @@ static const struct pwm_ops meson_pwm_ops = { .get_state = meson_pwm_get_state, }; -static const char * const pwm_meson8b_parent_names[] = { - "xtal", NULL, "fclk_div4", "fclk_div3" -}; - static const struct meson_pwm_data pwm_meson8b_data = { - .parent_names = pwm_meson8b_parent_names, - .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names), + .parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" }, }; /* * Only the 2 first inputs of the GXBB AO PWMs are valid * The last 2 are grounded */ -static const char * const pwm_gxbb_ao_parent_names[] = { - "xtal", "clk81" -}; - static const struct meson_pwm_data pwm_gxbb_ao_data = { - .parent_names = pwm_gxbb_ao_parent_names, - .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), -}; - -static const char * const pwm_axg_ee_parent_names[] = { - "xtal", "fclk_div5", "fclk_div4", "fclk_div3" + .parent_names = { "xtal", "clk81", NULL, NULL }, }; static const struct meson_pwm_data pwm_axg_ee_data = { - .parent_names = pwm_axg_ee_parent_names, - .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), -}; - -static const char * const pwm_axg_ao_parent_names[] = { - "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" + .parent_names = { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" }, }; static const struct meson_pwm_data pwm_axg_ao_data = { - .parent_names = pwm_axg_ao_parent_names, - .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), -}; - -static const char * const pwm_g12a_ao_ab_parent_names[] = { - "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" + .parent_names = { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }, }; static const struct meson_pwm_data pwm_g12a_ao_ab_data = { - .parent_names = pwm_g12a_ao_ab_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names), -}; - -static const char * const pwm_g12a_ao_cd_parent_names[] = { - "xtal", "g12a_ao_clk81", + .parent_names = { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" }, }; static const struct meson_pwm_data pwm_g12a_ao_cd_data = { - .parent_names = pwm_g12a_ao_cd_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), + .parent_names = { "xtal", "g12a_ao_clk81", NULL, NULL }, }; static const struct of_device_id meson_pwm_matches[] = { @@ -437,13 +406,13 @@ MODULE_DEVICE_TABLE(of, meson_pwm_matches); static int meson_pwm_init_channels(struct pwm_chip *chip) { struct meson_pwm *meson = to_meson_pwm(chip); - struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {}; + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; struct device *dev = pwmchip_parent(chip); unsigned int i; char name[255]; int err; - for (i = 0; i < meson->data->num_parents; i++) { + for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) { mux_parent_data[i].index = -1; mux_parent_data[i].name = meson->data->parent_names[i]; } @@ -459,7 +428,7 @@ static int meson_pwm_init_channels(struct pwm_chip *chip) init.ops = &clk_mux_ops; init.flags = 0; init.parent_data = mux_parent_data; - init.num_parents = meson->data->num_parents; + init.num_parents = MESON_NUM_MUX_PARENTS; channel->mux.reg = meson->base + REG_MISC_AB; channel->mux.shift = -- 2.43.0
next prev parent reply other threads:[~2024-02-21 15:12 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-21 15:11 [PATCH v5 0/5] pwm: meson: dt-bindings fixup Jerome Brunet 2024-02-21 15:11 ` Jerome Brunet 2024-02-21 15:11 ` [PATCH v5 1/5] dt-bindings: pwm: amlogic: fix s4 bindings Jerome Brunet 2024-02-21 15:11 ` Jerome Brunet 2024-02-21 15:11 ` [PATCH v5 2/5] dt-bindings: pwm: amlogic: Add a new binding for meson8 pwm types Jerome Brunet 2024-02-21 15:11 ` Jerome Brunet 2024-02-23 14:19 ` Rob Herring 2024-02-23 14:19 ` Rob Herring 2024-02-21 15:11 ` Jerome Brunet [this message] 2024-02-21 15:11 ` [PATCH v5 3/5] pwm: meson: generalize 4 inputs clock on meson8 pwm type Jerome Brunet 2024-02-21 15:11 ` [PATCH v5 4/5] pwm: meson: don't carry internal clock elements around Jerome Brunet 2024-02-21 15:11 ` Jerome Brunet 2024-04-12 11:27 ` Uwe Kleine-König 2024-04-12 11:27 ` Uwe Kleine-König 2024-02-21 15:11 ` [PATCH v5 5/5] pwm: meson: add generic compatible for meson8 to sm1 Jerome Brunet 2024-02-21 15:11 ` Jerome Brunet 2024-04-12 12:08 ` Uwe Kleine-König 2024-04-12 12:08 ` Uwe Kleine-König 2024-04-18 11:57 ` Jerome Brunet 2024-04-18 11:57 ` Jerome Brunet 2024-04-18 16:08 ` Uwe Kleine-König 2024-04-18 16:08 ` Uwe Kleine-König 2024-04-23 8:08 ` Neil Armstrong 2024-04-23 8:08 ` Neil Armstrong 2024-03-02 10:04 ` [PATCH v5 0/5] pwm: meson: dt-bindings fixup Uwe Kleine-König 2024-03-02 10:04 ` Uwe Kleine-König 2024-03-02 15:50 ` Jerome Brunet 2024-03-02 15:50 ` Jerome Brunet 2024-04-12 8:04 ` Jerome Brunet 2024-04-12 8:04 ` Jerome Brunet 2024-04-12 8:29 ` George Stark 2024-04-12 8:29 ` George Stark
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