From: Siddharth Vadapalli <s-vadapalli@ti.com> To: Niklas Cassel <cassel@kernel.org> Cc: Siddharth Vadapalli <s-vadapalli@ti.com>, <lpieralisi@kernel.org>, <kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>, <manivannan.sadhasivam@linaro.org>, <fancer.lancer@gmail.com>, <u.kleine-koenig@pengutronix.de>, <dlemoal@kernel.org>, <yoshihiro.shimoda.uh@renesas.com>, <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <srk@ti.com> Subject: Re: [PATCH v5] PCI: keystone: Fix pci_ops for AM654x SoC Date: Tue, 26 Mar 2024 20:00:04 +0530 [thread overview] Message-ID: <2e40b30d-b063-48ac-a566-f66eb2788003@ti.com> (raw) In-Reply-To: <ZgLUCqh12RMApzyr@x1-carbon> On Tue, Mar 26, 2024 at 02:56:26PM +0100, Niklas Cassel wrote: > On Tue, Mar 26, 2024 at 04:49:05PM +0530, Siddharth Vadapalli wrote: > > In the process of converting .scan_bus() callbacks to .add_bus(), the > > ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus(). > > The .scan_bus() method belonged to ks_pcie_host_ops which was specific > > to controller version 3.65a, while the .add_bus() method had been added > > to ks_pcie_ops which is shared between the controller versions 3.65a and > > 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer > > ks_pcie_v3_65_add_bus() method are applicable to the controller version > > 4.90a which is present in AM654x SoCs. > > ... > > + } while (val & DBI_CS2); > > +} > > + > > static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) > > { > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); > > + > > + /* Configure and set up BAR0 */ > > + ks_pcie_set_dbi_mode(ks_pcie); > > + > > + /* Enable BAR0 */ > > + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); > > + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); > > + > > + ks_pcie_clear_dbi_mode(ks_pcie); > > + > > + /* > > + * For BAR0, just setting bus address for inbound writes (MSI) should > > + * be sufficient. Use physical address to avoid any conflicts. > > + */ > > This comment seems to have wrong indentation. > With that fixed: > > Reviewed-by: Niklas Cassel <cassel@kernel.org> I will fix it and post the v6 patch. Regards, Siddharth.
WARNING: multiple messages have this Message-ID (diff)
From: Siddharth Vadapalli <s-vadapalli@ti.com> To: Niklas Cassel <cassel@kernel.org> Cc: Siddharth Vadapalli <s-vadapalli@ti.com>, <lpieralisi@kernel.org>, <kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>, <manivannan.sadhasivam@linaro.org>, <fancer.lancer@gmail.com>, <u.kleine-koenig@pengutronix.de>, <dlemoal@kernel.org>, <yoshihiro.shimoda.uh@renesas.com>, <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <srk@ti.com> Subject: Re: [PATCH v5] PCI: keystone: Fix pci_ops for AM654x SoC Date: Tue, 26 Mar 2024 20:00:04 +0530 [thread overview] Message-ID: <2e40b30d-b063-48ac-a566-f66eb2788003@ti.com> (raw) In-Reply-To: <ZgLUCqh12RMApzyr@x1-carbon> On Tue, Mar 26, 2024 at 02:56:26PM +0100, Niklas Cassel wrote: > On Tue, Mar 26, 2024 at 04:49:05PM +0530, Siddharth Vadapalli wrote: > > In the process of converting .scan_bus() callbacks to .add_bus(), the > > ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus(). > > The .scan_bus() method belonged to ks_pcie_host_ops which was specific > > to controller version 3.65a, while the .add_bus() method had been added > > to ks_pcie_ops which is shared between the controller versions 3.65a and > > 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer > > ks_pcie_v3_65_add_bus() method are applicable to the controller version > > 4.90a which is present in AM654x SoCs. > > ... > > + } while (val & DBI_CS2); > > +} > > + > > static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) > > { > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); > > + > > + /* Configure and set up BAR0 */ > > + ks_pcie_set_dbi_mode(ks_pcie); > > + > > + /* Enable BAR0 */ > > + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); > > + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); > > + > > + ks_pcie_clear_dbi_mode(ks_pcie); > > + > > + /* > > + * For BAR0, just setting bus address for inbound writes (MSI) should > > + * be sufficient. Use physical address to avoid any conflicts. > > + */ > > This comment seems to have wrong indentation. > With that fixed: > > Reviewed-by: Niklas Cassel <cassel@kernel.org> I will fix it and post the v6 patch. Regards, Siddharth. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-03-26 14:30 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-26 11:19 [PATCH v5] PCI: keystone: Fix pci_ops for AM654x SoC Siddharth Vadapalli 2024-03-26 11:19 ` Siddharth Vadapalli 2024-03-26 13:56 ` Niklas Cassel 2024-03-26 13:56 ` Niklas Cassel 2024-03-26 14:30 ` Siddharth Vadapalli [this message] 2024-03-26 14:30 ` Siddharth Vadapalli 2024-03-26 14:47 ` Siddharth Vadapalli 2024-03-26 14:47 ` Siddharth Vadapalli
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