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From: Baruch Siach <baruch@tkos.co.il>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <bgolaszewski@baylibre.com>
Cc: Baruch Siach <baruch@tkos.co.il>,
	Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Ralph Sennhauser <ralph.sennhauser@gmail.com>,
	linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/5] arm64: dts: armada: add pwm offsets for ap/cp gpios
Date: Wed, 18 Nov 2020 12:30:45 +0200	[thread overview]
Message-ID: <5189d34603ac90eb265b906cb37115d105aa4087.1605694661.git.baruch@tkos.co.il> (raw)
In-Reply-To: <cover.1605694661.git.baruch@tkos.co.il>

The 'pwm-offset' property of both GPIO blocks (per CP component) point
to the same counter registers offset. The driver will decide how to use
counters A/B.

This is different from the convention of pwm on earlier Armada series
(370/38x). On those systems the assignment of A/B counters to GPIO
blocks is coded in both DT and the driver. The actual behaviour of the
current driver on Armada 8K/7K is the same as earlier systems.

Add also clock properties for base pwm frequency reference.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 arch/arm64/boot/dts/marvell/armada-ap80x.dtsi |  3 +++
 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++++++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 12e477f1aeb9..7f8d589ed938 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -281,6 +281,9 @@ ap_gpio: gpio@1040 {
 					gpio-controller;
 					#gpio-cells = <2>;
 					gpio-ranges = <&ap_pinctrl 0 0 20>;
+					pwm-offset = <0x10c0>;
+					#pwm-cells = <2>;
+					clocks = <&ap_clk 3>;
 				};
 			};
 
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 9dcf16beabf5..366daec416df 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -234,12 +234,17 @@ CP11X_LABEL(gpio1): gpio@100 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
+				pwm-offset = <0x1f0>;
+				#pwm-cells = <2>;
 				interrupt-controller;
 				interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
 					<85 IRQ_TYPE_LEVEL_HIGH>,
 					<84 IRQ_TYPE_LEVEL_HIGH>,
 					<83 IRQ_TYPE_LEVEL_HIGH>;
 				#interrupt-cells = <2>;
+				clock-names = "core", "axi";
+				clocks = <&CP11X_LABEL(clk) 1 21>,
+					 <&CP11X_LABEL(clk) 1 17>;
 				status = "disabled";
 			};
 
@@ -250,12 +255,17 @@ CP11X_LABEL(gpio2): gpio@140 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
+				pwm-offset = <0x1f0>;
+				#pwm-cells = <2>;
 				interrupt-controller;
 				interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
 					<81 IRQ_TYPE_LEVEL_HIGH>,
 					<80 IRQ_TYPE_LEVEL_HIGH>,
 					<79 IRQ_TYPE_LEVEL_HIGH>;
 				#interrupt-cells = <2>;
+				clock-names = "core", "axi";
+				clocks = <&CP11X_LABEL(clk) 1 21>,
+					 <&CP11X_LABEL(clk) 1 17>;
 				status = "disabled";
 			};
 		};
-- 
2.29.2


WARNING: multiple messages have this Message-ID (diff)
From: Baruch Siach <baruch@tkos.co.il>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <bgolaszewski@baylibre.com>
Cc: Andrew Lunn <andrew@lunn.ch>, Baruch Siach <baruch@tkos.co.il>,
	Jason Cooper <jason@lakedaemon.net>,
	linux-pwm@vger.kernel.org,
	Gregory Clement <gregory.clement@bootlin.com>,
	linux-gpio@vger.kernel.org,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Ralph Sennhauser <ralph.sennhauser@gmail.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	linux-arm-kernel@lists.infradead.org,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: [PATCH 4/5] arm64: dts: armada: add pwm offsets for ap/cp gpios
Date: Wed, 18 Nov 2020 12:30:45 +0200	[thread overview]
Message-ID: <5189d34603ac90eb265b906cb37115d105aa4087.1605694661.git.baruch@tkos.co.il> (raw)
In-Reply-To: <cover.1605694661.git.baruch@tkos.co.il>

The 'pwm-offset' property of both GPIO blocks (per CP component) point
to the same counter registers offset. The driver will decide how to use
counters A/B.

This is different from the convention of pwm on earlier Armada series
(370/38x). On those systems the assignment of A/B counters to GPIO
blocks is coded in both DT and the driver. The actual behaviour of the
current driver on Armada 8K/7K is the same as earlier systems.

Add also clock properties for base pwm frequency reference.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 arch/arm64/boot/dts/marvell/armada-ap80x.dtsi |  3 +++
 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++++++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 12e477f1aeb9..7f8d589ed938 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -281,6 +281,9 @@ ap_gpio: gpio@1040 {
 					gpio-controller;
 					#gpio-cells = <2>;
 					gpio-ranges = <&ap_pinctrl 0 0 20>;
+					pwm-offset = <0x10c0>;
+					#pwm-cells = <2>;
+					clocks = <&ap_clk 3>;
 				};
 			};
 
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 9dcf16beabf5..366daec416df 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -234,12 +234,17 @@ CP11X_LABEL(gpio1): gpio@100 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
+				pwm-offset = <0x1f0>;
+				#pwm-cells = <2>;
 				interrupt-controller;
 				interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
 					<85 IRQ_TYPE_LEVEL_HIGH>,
 					<84 IRQ_TYPE_LEVEL_HIGH>,
 					<83 IRQ_TYPE_LEVEL_HIGH>;
 				#interrupt-cells = <2>;
+				clock-names = "core", "axi";
+				clocks = <&CP11X_LABEL(clk) 1 21>,
+					 <&CP11X_LABEL(clk) 1 17>;
 				status = "disabled";
 			};
 
@@ -250,12 +255,17 @@ CP11X_LABEL(gpio2): gpio@140 {
 				gpio-controller;
 				#gpio-cells = <2>;
 				gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
+				pwm-offset = <0x1f0>;
+				#pwm-cells = <2>;
 				interrupt-controller;
 				interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
 					<81 IRQ_TYPE_LEVEL_HIGH>,
 					<80 IRQ_TYPE_LEVEL_HIGH>,
 					<79 IRQ_TYPE_LEVEL_HIGH>;
 				#interrupt-cells = <2>;
+				clock-names = "core", "axi";
+				clocks = <&CP11X_LABEL(clk) 1 21>,
+					 <&CP11X_LABEL(clk) 1 17>;
 				status = "disabled";
 			};
 		};
-- 
2.29.2


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  parent reply	other threads:[~2020-11-18 10:47 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-18 10:30 [PATCH 0/5] gpio: mvebu: Armada 8K/7K PWM support Baruch Siach
2020-11-18 10:30 ` Baruch Siach
2020-11-18 10:30 ` [PATCH 1/5] gpio: mvebu: update Armada XP per-CPU comment Baruch Siach
2020-11-18 10:30   ` Baruch Siach
2020-11-18 22:47   ` Andrew Lunn
2020-11-18 22:47     ` Andrew Lunn
2020-11-18 10:30 ` [PATCH 2/5] gpio: mvebu: switch pwm duration registers to regmap Baruch Siach
2020-11-18 10:30   ` Baruch Siach
2020-11-18 22:59   ` Andrew Lunn
2020-11-18 22:59     ` Andrew Lunn
2020-11-18 10:30 ` [PATCH 3/5] gpio: mvebu: add pwm support for Armada 8K/7K Baruch Siach
2020-11-18 10:30   ` Baruch Siach
2020-11-18 23:18   ` Andrew Lunn
2020-11-18 23:18     ` Andrew Lunn
2020-11-19  6:21     ` Baruch Siach
2020-11-19  6:21       ` Baruch Siach
2020-11-19 13:34       ` Andrew Lunn
2020-11-19 13:34         ` Andrew Lunn
2020-11-19 13:47         ` Baruch Siach
2020-11-19 13:47           ` Baruch Siach
2020-12-01 18:16           ` Bartosz Golaszewski
2020-12-01 18:16             ` Bartosz Golaszewski
2020-12-01 18:21             ` Baruch Siach
2020-12-01 18:21               ` Baruch Siach
2020-11-18 10:30 ` Baruch Siach [this message]
2020-11-18 10:30   ` [PATCH 4/5] arm64: dts: armada: add pwm offsets for ap/cp gpios Baruch Siach
2020-11-18 10:30 ` [PATCH 5/5] dt-bindings: ap806: document gpio pwm-offset property Baruch Siach
2020-11-18 10:30   ` Baruch Siach
2020-11-18 22:46 ` [PATCH 0/5] gpio: mvebu: Armada 8K/7K PWM support Andrew Lunn
2020-11-18 22:46   ` Andrew Lunn
2020-11-19  5:49   ` Baruch Siach
2020-11-19  5:49     ` Baruch Siach

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