All of lore.kernel.org
 help / color / mirror / Atom feed
From: Michal Simek <michal.simek@xilinx.com>
To: linux-kernel@vger.kernel.org, monstr@monstr.eu,
	michal.simek@xilinx.com, git@xilinx.com
Cc: Kalyani Akula <kalyani.akula@xilinx.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 09/12] arm64: dts: zynqmp: Wire zynqmp qspi controller
Date: Thu, 21 Jan 2021 11:26:57 +0100	[thread overview]
Message-ID: <5cebbc59a452f282c4ce0f0e1dffecadac8f126a.1611224800.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1611224800.git.michal.simek@xilinx.com>

Add missing ZynqMP qspi IP. It works in single mode only.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi |  4 ++++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi         | 14 ++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 7af57619436d..6a577e1383c1 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -164,6 +164,10 @@ &pcie {
 	clocks = <&zynqmp_clk PCIE_REF>;
 };
 
+&qspi {
+	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
 &sata {
 	clocks = <&zynqmp_clk SATA_REF>;
 };
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 19b349f00ce7..533c19b80283 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -595,6 +595,20 @@ pcie_intc: legacy-interrupt-controller {
 			};
 		};
 
+		qspi: spi@ff0f0000 {
+			compatible = "xlnx,zynqmp-qspi-1.0";
+			status = "disabled";
+			clock-names = "ref_clk", "pclk";
+			interrupts = <0 15 4>;
+			interrupt-parent = <&gic>;
+			num-cs = <1>;
+			reg = <0x0 0xff0f0000 0x0 0x1000>,
+			      <0x0 0xc0000000 0x0 0x8000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			power-domains = <&zynqmp_firmware PD_QSPI>;
+		};
+
 		psgtr: phy@fd400000 {
 			compatible = "xlnx,zynqmp-psgtr-v1.1";
 			status = "disabled";
-- 
2.30.0


WARNING: multiple messages have this Message-ID (diff)
From: Michal Simek <michal.simek@xilinx.com>
To: linux-kernel@vger.kernel.org, monstr@monstr.eu,
	michal.simek@xilinx.com, git@xilinx.com
Cc: devicetree@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	Kalyani Akula <kalyani.akula@xilinx.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 09/12] arm64: dts: zynqmp: Wire zynqmp qspi controller
Date: Thu, 21 Jan 2021 11:26:57 +0100	[thread overview]
Message-ID: <5cebbc59a452f282c4ce0f0e1dffecadac8f126a.1611224800.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1611224800.git.michal.simek@xilinx.com>

Add missing ZynqMP qspi IP. It works in single mode only.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi |  4 ++++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi         | 14 ++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 7af57619436d..6a577e1383c1 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -164,6 +164,10 @@ &pcie {
 	clocks = <&zynqmp_clk PCIE_REF>;
 };
 
+&qspi {
+	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
 &sata {
 	clocks = <&zynqmp_clk SATA_REF>;
 };
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 19b349f00ce7..533c19b80283 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -595,6 +595,20 @@ pcie_intc: legacy-interrupt-controller {
 			};
 		};
 
+		qspi: spi@ff0f0000 {
+			compatible = "xlnx,zynqmp-qspi-1.0";
+			status = "disabled";
+			clock-names = "ref_clk", "pclk";
+			interrupts = <0 15 4>;
+			interrupt-parent = <&gic>;
+			num-cs = <1>;
+			reg = <0x0 0xff0f0000 0x0 0x1000>,
+			      <0x0 0xc0000000 0x0 0x8000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			power-domains = <&zynqmp_firmware PD_QSPI>;
+		};
+
 		psgtr: phy@fd400000 {
 			compatible = "xlnx,zynqmp-psgtr-v1.1";
 			status = "disabled";
-- 
2.30.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-01-21 10:34 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-21 10:26 [PATCH v2 00/12] arm64: dts: zynqmp: DT updates to match latest drivers Michal Simek
2021-01-21 10:26 ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 01/12] arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 02/12] arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 03/12] arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 04/12] arm64: dts: zynqmp: Enable reset controller driver Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 22:38   ` Laurent Pinchart
2021-01-21 22:38     ` Laurent Pinchart
2021-01-21 10:26 ` [PATCH v2 05/12] arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 06/12] arm64: dts: zynqmp: Add label for zynqmp_ipi Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 07/12] arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 08/12] arm64: dts: zynqmp: Wire arasan nand controller Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:26 ` Michal Simek [this message]
2021-01-21 10:26   ` [PATCH v2 09/12] arm64: dts: zynqmp: Wire zynqmp qspi controller Michal Simek
2021-01-21 10:26 ` [PATCH v2 10/12] arm64: dts: zynqmp: Add missing lpd watchdog node Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:26 ` [PATCH v2 11/12] arm64: dts: zynqmp: Add missing iommu IDs Michal Simek
2021-01-21 10:26   ` Michal Simek
2021-01-21 10:27 ` [PATCH v2 12/12] arm64: dts: zynqmp: Add description for zcu104 revC Michal Simek
2021-01-21 10:27   ` Michal Simek
2021-02-01  9:38   ` Michal Simek
2021-02-01  9:38     ` Michal Simek
2021-02-01  9:36 ` [PATCH v2 00/12] arm64: dts: zynqmp: DT updates to match latest drivers Michal Simek
2021-02-01  9:36   ` Michal Simek

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5cebbc59a452f282c4ce0f0e1dffecadac8f126a.1611224800.git.michal.simek@xilinx.com \
    --to=michal.simek@xilinx.com \
    --cc=devicetree@vger.kernel.org \
    --cc=git@xilinx.com \
    --cc=kalyani.akula@xilinx.com \
    --cc=krzk@kernel.org \
    --cc=laurent.pinchart@ideasonboard.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=monstr@monstr.eu \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.