From: Ziyang Huang <hzyitc@outlook.com> To: mcoquelin.stm32@gmail.com Cc: alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, Ziyang Huang <hzyitc@outlook.com> Subject: [PATCH 1/8] net: phy: Introduce Qualcomm IPQ5018 internal PHY driver Date: Sun, 21 Jan 2024 20:42:30 +0800 [thread overview] Message-ID: <TYZPR01MB5556D5568546D6DA4313209EC9762@TYZPR01MB5556.apcprd01.prod.exchangelabs.com> (raw) In-Reply-To: <TYZPR01MB55563BD6A2B78402E4BB44D4C9762@TYZPR01MB5556.apcprd01.prod.exchangelabs.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> --- drivers/net/phy/Kconfig | 5 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/ipq5018-internal.c | 125 +++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 drivers/net/phy/ipq5018-internal.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 107880d13d21..2d068fea7008 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -202,6 +202,11 @@ config INTEL_XWAY_PHY PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel SoCs xRX200, xRX300, xRX330, xRX350 and xRX550. +config IPQ5018_INTERNAL_PHY + tristate "Qualcomm IPQ5018 internal PHY" + help + Supports for the Qualcomm IPQ5018 internal PHY. + config LSI_ET1011C_PHY tristate "LSI ET1011C PHY" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index c945ed9bd14b..16d65378ae34 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_DP83TD510_PHY) += dp83td510.o obj-$(CONFIG_FIXED_PHY) += fixed_phy.o obj-$(CONFIG_ICPLUS_PHY) += icplus.o obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o +obj-$(CONFIG_IPQ5018_INTERNAL_PHY) += ipq5018-internal.o obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o obj-$(CONFIG_LXT_PHY) += lxt.o obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o diff --git a/drivers/net/phy/ipq5018-internal.c b/drivers/net/phy/ipq5018-internal.c new file mode 100644 index 000000000000..d1331951b4d8 --- /dev/null +++ b/drivers/net/phy/ipq5018-internal.c @@ -0,0 +1,125 @@ +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/phy.h> +#include <linux/reset.h> + +#define IPQ5018_PHY_ID 0x004dd0c0 + +#define TX_RX_CLK_RATE 125000000 /* 125M */ + +#define IPQ5018_PHY_FIFO_CONTROL 0x19 +#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) + +struct ipq5018_phy { + int num_clks; + struct clk_bulk_data *clks; + struct reset_control *rst; + + struct clk_hw *clk_rx, *clk_tx; + struct clk_hw_onecell_data *clk_data; +}; + +static int ipq5018_probe(struct phy_device *phydev) +{ + struct ipq5018_phy *priv; + struct device *dev = &phydev->mdio.dev; + char name[64]; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate priv\n"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 0) + return dev_err_probe(dev, priv->num_clks, + "failed to acquire clocks\n"); + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable clocks\n"); + + priv->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR_OR_NULL(priv->rst)) + return dev_err_probe(dev, PTR_ERR(priv->rst), + "failed to acquire reset\n"); + + ret = reset_control_reset(priv->rst); + if (ret) + return dev_err_probe(dev, ret, + "failed to reset\n"); + + snprintf(name, sizeof(name), "%s#rx", dev_name(dev)); + priv->clk_rx = clk_hw_register_fixed_rate(dev, name, NULL, 0, + TX_RX_CLK_RATE); + if (IS_ERR_OR_NULL(priv->clk_rx)) + return dev_err_probe(dev, PTR_ERR(priv->clk_rx), + "failed to register rx clock\n"); + + snprintf(name, sizeof(name), "%s#tx", dev_name(dev)); + priv->clk_tx = clk_hw_register_fixed_rate(dev, name, NULL, 0, + TX_RX_CLK_RATE); + if (IS_ERR_OR_NULL(priv->clk_tx)) + return dev_err_probe(dev, PTR_ERR(priv->clk_tx), + "failed to register tx clock\n"); + + priv->clk_data = devm_kzalloc(dev, + struct_size(priv->clk_data, hws, 2), + GFP_KERNEL); + if (!priv->clk_data) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate clk_data\n"); + + priv->clk_data->num = 2; + priv->clk_data->hws[0] = priv->clk_rx; + priv->clk_data->hws[1] = priv->clk_tx; + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + priv->clk_data); + if (ret) + return dev_err_probe(dev, ret, + "fail to register clock provider\n"); + + return 0; +} + +static int ipq5018_soft_reset(struct phy_device *phydev) +{ + int ret; + + ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL, + IPQ5018_PHY_FIFO_RESET, 0); + if (ret < 0) + return ret; + + msleep(50); + + ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL, + IPQ5018_PHY_FIFO_RESET, IPQ5018_PHY_FIFO_RESET); + if (ret < 0) + return ret; + + return 0; +} + +static struct phy_driver ipq5018_internal_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), + .name = "Qualcomm IPQ5018 internal PHY", + .flags = PHY_IS_INTERNAL, + .probe = ipq5018_probe, + .soft_reset = ipq5018_soft_reset, + }, +}; +module_phy_driver(ipq5018_internal_phy_driver); + +static struct mdio_device_id __maybe_unused ipq5018_internal_phy_ids[] = { + { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, + { } +}; +MODULE_DEVICE_TABLE(mdio, ipq5018_internal_phy_ids); + +MODULE_DESCRIPTION("Qualcomm IPQ5018 internal PHY driver"); +MODULE_AUTHOR("Ziyang Huang <hzyitc@outlook.com>"); -- 2.40.1
WARNING: multiple messages have this Message-ID (diff)
From: Ziyang Huang <hzyitc@outlook.com> To: mcoquelin.stm32@gmail.com Cc: alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, Ziyang Huang <hzyitc@outlook.com> Subject: [PATCH 1/8] net: phy: Introduce Qualcomm IPQ5018 internal PHY driver Date: Sun, 21 Jan 2024 20:42:30 +0800 [thread overview] Message-ID: <TYZPR01MB5556D5568546D6DA4313209EC9762@TYZPR01MB5556.apcprd01.prod.exchangelabs.com> (raw) In-Reply-To: <TYZPR01MB55563BD6A2B78402E4BB44D4C9762@TYZPR01MB5556.apcprd01.prod.exchangelabs.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> --- drivers/net/phy/Kconfig | 5 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/ipq5018-internal.c | 125 +++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 drivers/net/phy/ipq5018-internal.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 107880d13d21..2d068fea7008 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -202,6 +202,11 @@ config INTEL_XWAY_PHY PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel SoCs xRX200, xRX300, xRX330, xRX350 and xRX550. +config IPQ5018_INTERNAL_PHY + tristate "Qualcomm IPQ5018 internal PHY" + help + Supports for the Qualcomm IPQ5018 internal PHY. + config LSI_ET1011C_PHY tristate "LSI ET1011C PHY" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index c945ed9bd14b..16d65378ae34 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_DP83TD510_PHY) += dp83td510.o obj-$(CONFIG_FIXED_PHY) += fixed_phy.o obj-$(CONFIG_ICPLUS_PHY) += icplus.o obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o +obj-$(CONFIG_IPQ5018_INTERNAL_PHY) += ipq5018-internal.o obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o obj-$(CONFIG_LXT_PHY) += lxt.o obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o diff --git a/drivers/net/phy/ipq5018-internal.c b/drivers/net/phy/ipq5018-internal.c new file mode 100644 index 000000000000..d1331951b4d8 --- /dev/null +++ b/drivers/net/phy/ipq5018-internal.c @@ -0,0 +1,125 @@ +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/phy.h> +#include <linux/reset.h> + +#define IPQ5018_PHY_ID 0x004dd0c0 + +#define TX_RX_CLK_RATE 125000000 /* 125M */ + +#define IPQ5018_PHY_FIFO_CONTROL 0x19 +#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) + +struct ipq5018_phy { + int num_clks; + struct clk_bulk_data *clks; + struct reset_control *rst; + + struct clk_hw *clk_rx, *clk_tx; + struct clk_hw_onecell_data *clk_data; +}; + +static int ipq5018_probe(struct phy_device *phydev) +{ + struct ipq5018_phy *priv; + struct device *dev = &phydev->mdio.dev; + char name[64]; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate priv\n"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 0) + return dev_err_probe(dev, priv->num_clks, + "failed to acquire clocks\n"); + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable clocks\n"); + + priv->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR_OR_NULL(priv->rst)) + return dev_err_probe(dev, PTR_ERR(priv->rst), + "failed to acquire reset\n"); + + ret = reset_control_reset(priv->rst); + if (ret) + return dev_err_probe(dev, ret, + "failed to reset\n"); + + snprintf(name, sizeof(name), "%s#rx", dev_name(dev)); + priv->clk_rx = clk_hw_register_fixed_rate(dev, name, NULL, 0, + TX_RX_CLK_RATE); + if (IS_ERR_OR_NULL(priv->clk_rx)) + return dev_err_probe(dev, PTR_ERR(priv->clk_rx), + "failed to register rx clock\n"); + + snprintf(name, sizeof(name), "%s#tx", dev_name(dev)); + priv->clk_tx = clk_hw_register_fixed_rate(dev, name, NULL, 0, + TX_RX_CLK_RATE); + if (IS_ERR_OR_NULL(priv->clk_tx)) + return dev_err_probe(dev, PTR_ERR(priv->clk_tx), + "failed to register tx clock\n"); + + priv->clk_data = devm_kzalloc(dev, + struct_size(priv->clk_data, hws, 2), + GFP_KERNEL); + if (!priv->clk_data) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate clk_data\n"); + + priv->clk_data->num = 2; + priv->clk_data->hws[0] = priv->clk_rx; + priv->clk_data->hws[1] = priv->clk_tx; + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + priv->clk_data); + if (ret) + return dev_err_probe(dev, ret, + "fail to register clock provider\n"); + + return 0; +} + +static int ipq5018_soft_reset(struct phy_device *phydev) +{ + int ret; + + ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL, + IPQ5018_PHY_FIFO_RESET, 0); + if (ret < 0) + return ret; + + msleep(50); + + ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL, + IPQ5018_PHY_FIFO_RESET, IPQ5018_PHY_FIFO_RESET); + if (ret < 0) + return ret; + + return 0; +} + +static struct phy_driver ipq5018_internal_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), + .name = "Qualcomm IPQ5018 internal PHY", + .flags = PHY_IS_INTERNAL, + .probe = ipq5018_probe, + .soft_reset = ipq5018_soft_reset, + }, +}; +module_phy_driver(ipq5018_internal_phy_driver); + +static struct mdio_device_id __maybe_unused ipq5018_internal_phy_ids[] = { + { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, + { } +}; +MODULE_DEVICE_TABLE(mdio, ipq5018_internal_phy_ids); + +MODULE_DESCRIPTION("Qualcomm IPQ5018 internal PHY driver"); +MODULE_AUTHOR("Ziyang Huang <hzyitc@outlook.com>"); -- 2.40.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-01-21 12:42 UTC|newest] Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-21 12:40 [PATCH 0/8] ipq5018: enable ethernet support Ziyang Huang 2024-01-21 12:40 ` Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang [this message] 2024-01-21 12:42 ` [PATCH 1/8] net: phy: Introduce Qualcomm IPQ5018 internal PHY driver Ziyang Huang 2024-01-21 16:19 ` Andrew Lunn 2024-01-21 16:19 ` Andrew Lunn 2024-01-22 15:37 ` Ziyang Huang 2024-01-22 15:37 ` Ziyang Huang 2024-01-22 17:18 ` Andrew Lunn 2024-01-22 17:18 ` Andrew Lunn 2024-01-23 15:38 ` Ziyang Huang 2024-01-23 15:38 ` Ziyang Huang 2024-01-23 23:15 ` Andrew Lunn 2024-01-23 23:15 ` Andrew Lunn 2024-01-21 12:42 ` [PATCH 2/8] phy: Introduce Qualcomm ethernet uniphy driver Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-23 15:58 ` Ziyang Huang 2024-01-23 15:58 ` Ziyang Huang 2024-01-23 23:25 ` Andrew Lunn 2024-01-23 23:25 ` Andrew Lunn 2024-01-21 12:42 ` [PATCH 3/8] net: stmmac: Introduce Qualcomm IPQ50xx DWMAC driver Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-24 5:54 ` kernel test robot 2024-01-24 5:54 ` kernel test robot 2024-01-24 9:40 ` kernel test robot 2024-01-24 9:40 ` kernel test robot 2024-01-21 12:42 ` [PATCH 4/8] clk: qcom: gcc-ipq5018: correct gcc_gmac0_sys_clk reg Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:28 ` Andrew Lunn 2024-01-21 16:28 ` Andrew Lunn 2024-01-22 15:39 ` Ziyang Huang 2024-01-22 15:39 ` Ziyang Huang 2024-01-21 12:42 ` [PATCH 5/8] clk: qcom: support for duplicate freq in RCG2 freq table Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:57 ` Andrew Lunn 2024-01-21 16:57 ` Andrew Lunn 2024-01-22 16:35 ` Ziyang Huang 2024-01-22 16:35 ` Ziyang Huang 2024-01-22 17:34 ` Andrew Lunn 2024-01-22 17:34 ` Andrew Lunn 2024-01-23 15:43 ` Ziyang Huang 2024-01-23 15:43 ` Ziyang Huang 2024-01-22 7:55 ` Krzysztof Kozlowski 2024-01-22 7:55 ` Krzysztof Kozlowski 2024-01-22 14:48 ` Ziyang Huang 2024-01-22 14:48 ` Ziyang Huang 2024-01-21 12:42 ` [PATCH 6/8] net: mdio: ipq4019: support reset control Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:35 ` Andrew Lunn 2024-01-21 16:35 ` Andrew Lunn 2024-01-22 15:52 ` Ziyang Huang 2024-01-22 15:52 ` Ziyang Huang 2024-01-21 12:42 ` [PATCH 7/8] arm64: dts: qcom: ipq5018: enable ethernet support Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-21 16:45 ` Andrew Lunn 2024-01-21 16:45 ` Andrew Lunn 2024-01-22 15:52 ` Ziyang Huang 2024-01-22 15:52 ` Ziyang Huang 2024-01-22 17:27 ` Andrew Lunn 2024-01-22 17:27 ` Andrew Lunn 2024-01-21 12:42 ` [PATCH 8/8] arm64: dts: qcom: ipq5018-rdp432-c2: " Ziyang Huang 2024-01-21 12:42 ` Ziyang Huang 2024-01-22 7:54 ` Krzysztof Kozlowski 2024-01-22 7:54 ` Krzysztof Kozlowski 2024-01-24 0:53 ` kernel test robot 2024-01-24 0:53 ` kernel test robot 2024-01-21 15:51 ` [PATCH 0/8] ipq5018: " Andrew Lunn 2024-01-21 15:51 ` Andrew Lunn 2024-01-22 14:45 ` Ziyang Huang 2024-01-22 14:45 ` Ziyang Huang
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