From: Geert Uytterhoeven <geert+renesas@glider.be> To: Magnus Damm <magnus.damm@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven <geert+renesas@glider.be> Subject: [PATCH] arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock Date: Fri, 7 Oct 2022 17:20:03 +0200 [thread overview] Message-ID: <a5bd4148f92806f7c8e577d383370f810315f586.1665155947.git.geert+renesas@glider.be> (raw) As serial communication requires a clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the clock input for the HSCIF0 Baud Rate Generator internal clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- For full proper operation, this depends on "[PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks"[1]. However, as the "brg_int" clock is optional, the serial driver will keep on functioning without it, and just resort to a less optimal clock input/divider combination, which is still good enough for the serial console. [1] https://lore.kernel.org/r/d0f35c35e1f96c5a649ab477e7ba5d8025957cd0.1665147497.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index edabd1519ccc979d..c941054f4980667b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -360,7 +360,7 @@ hscif0: serial@e6540000 { reg = <0 0xe6540000 0 96>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x31>, <&dmac0 0x30>, -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert+renesas@glider.be> To: Magnus Damm <magnus.damm@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven <geert+renesas@glider.be> Subject: [PATCH] arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock Date: Fri, 7 Oct 2022 17:20:03 +0200 [thread overview] Message-ID: <a5bd4148f92806f7c8e577d383370f810315f586.1665155947.git.geert+renesas@glider.be> (raw) As serial communication requires a clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the clock input for the HSCIF0 Baud Rate Generator internal clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- For full proper operation, this depends on "[PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks"[1]. However, as the "brg_int" clock is optional, the serial driver will keep on functioning without it, and just resort to a less optimal clock input/divider combination, which is still good enough for the serial console. [1] https://lore.kernel.org/r/d0f35c35e1f96c5a649ab477e7ba5d8025957cd0.1665147497.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index edabd1519ccc979d..c941054f4980667b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -360,7 +360,7 @@ hscif0: serial@e6540000 { reg = <0 0xe6540000 0 96>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x31>, <&dmac0 0x30>, -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2022-10-07 15:20 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-07 15:20 Geert Uytterhoeven [this message] 2022-10-07 15:20 ` [PATCH] arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock Geert Uytterhoeven 2022-10-10 7:55 ` Wolfram Sang 2022-10-10 7:55 ` Wolfram Sang 2022-10-10 11:12 ` Geert Uytterhoeven 2022-10-10 11:12 ` Geert Uytterhoeven
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=a5bd4148f92806f7c8e577d383370f810315f586.1665155947.git.geert+renesas@glider.be \ --to=geert+renesas@glider.be \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-renesas-soc@vger.kernel.org \ --cc=magnus.damm@gmail.com \ --cc=yoshihiro.shimoda.uh@renesas.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.