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From: viresh.kumar@linaro.org (Viresh Kumar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/9] pinctrl: SPEAr3xx: correct register space to configure pwm
Date: Sat, 27 Oct 2012 14:47:47 +0530	[thread overview]
Message-ID: <c93a7cffdf92e0bb0e4f4b78daec66218752fa7a.1351329224.git.viresh.kumar@linaro.org> (raw)
In-Reply-To: <cover.1351329224.git.viresh.kumar@linaro.org>

From: Shiraz Hashim <shiraz.hashim@st.com>

To have pwm on pad no. 34 we also need to select between pwm and SD_LED
functions. Add this to pwm pin mux register configuration.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/pinctrl/spear/pinctrl-spear320.c | 4 ++++
 drivers/pinctrl/spear/pinctrl-spear3xx.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
index 020b1e0..4fccf95 100644
--- a/drivers/pinctrl/spear/pinctrl-spear320.c
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -2240,6 +2240,10 @@ static struct spear_muxreg pwm2_pin_34_muxreg[] = {
 		.mask = PMX_SSP_CS_MASK,
 		.val = 0,
 	}, {
+		.reg = MODE_CONFIG_REG,
+		.mask = PMX_PWM_MASK,
+		.val = PMX_PWM_MASK,
+	}, {
 		.reg = IP_SEL_PAD_30_39_REG,
 		.mask = PMX_PL_34_MASK,
 		.val = PMX_PWM2_PL_34_VAL,
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
index 31f4434..7860b36 100644
--- a/drivers/pinctrl/spear/pinctrl-spear3xx.h
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -15,6 +15,7 @@
 #include "pinctrl-spear.h"
 
 /* pad mux declarations */
+#define PMX_PWM_MASK		(1 << 16)
 #define PMX_FIRDA_MASK		(1 << 14)
 #define PMX_I2C_MASK		(1 << 13)
 #define PMX_SSP_CS_MASK		(1 << 12)
-- 
1.7.12.rc2.18.g61b472e

  parent reply	other threads:[~2012-10-27  9:17 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-27  9:17 [PATCH 0/9] Pinctrl: SPEAr: Fixes for 3.7-rc3 Viresh Kumar
2012-10-27  9:17 ` [PATCH 1/9] pinctrl: SPEAr: Don't update all non muxreg bits on pinctrl_disable Viresh Kumar
2012-10-27  9:17 ` Viresh Kumar [this message]
2012-10-27  9:17 ` [PATCH 3/9] pinctrl: SPEAr320: Correct pad mux entries for rmii/smii Viresh Kumar
2012-10-27  9:17 ` [PATCH 4/9] pinctrl: SPEAr1310: fix clcd high resolution pin group name Viresh Kumar
2012-10-27  9:17 ` [PATCH 5/9] pinctrl: SPEAr1310: Fix value of PERIP_CFG reigster and MCIF_SEL_SHIFT Viresh Kumar
2012-10-27  9:17 ` [PATCH 6/9] pinctrl: SPEAr1310: Separate out pci pins from pcie_sata pin group Viresh Kumar
2012-10-27  9:17 ` [PATCH 7/9] pinctrl: SPEAr1310: add register entries for enabling pad direction Viresh Kumar
2012-10-27  9:17 ` [PATCH 8/9] pinctrl: SPEAr1340: Make DDR reset & clock pads as gpio Viresh Kumar
2012-10-27  9:17 ` [PATCH 9/9] pinctrl: SPEAr1340: Add clcd sleep mode pin configuration Viresh Kumar
2012-11-05 10:38 ` [PATCH 0/9] Pinctrl: SPEAr: Fixes for 3.7-rc3 Linus Walleij
2012-11-05 10:46   ` viresh kumar
2012-11-05 11:36     ` Linus Walleij

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