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From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, oleg@redhat.com,
	guoren@linux.alibaba.com, vincent.chen@sifive.com,
	paul.walmsley@sifive.com, palmerdabbelt@google.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 06/13] riscv: Add vector feature to compile
Date: Fri, 12 Jun 2020 15:09:55 +0800	[thread overview]
Message-ID: <cd64796afb84d9f3d97168fbfead633c15f68ce3.1591344965.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1591344965.git.greentime.hu@sifive.com>

From: Guo Ren <guoren@linux.alibaba.com>

This patch adds a new config option which could enable assembler's
vector feature.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
 arch/riscv/Kconfig  | 9 +++++++++
 arch/riscv/Makefile | 1 +
 2 files changed, 10 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 74f82cf4f781..3b742d949a09 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -305,6 +305,15 @@ config FPU
 
 	  If you don't know what to do here, say Y.
 
+config VECTOR
+	bool "VECTOR support"
+	default n
+	help
+	  Say N here if you want to disable all vector related procedure
+	  in the kernel.
+
+	  If you don't know what to do here, say Y.
+
 endmenu
 
 menu "Kernel features"
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 957d064bead0..7c80c95582e3 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -46,6 +46,7 @@ riscv-march-aflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
 riscv-march-aflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
 riscv-march-aflags-$(CONFIG_FPU)		:= $(riscv-march-aflags-y)fd
 riscv-march-aflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-aflags-y)c
+riscv-march-aflags-$(CONFIG_VECTOR)		:= $(riscv-march-aflags-y)v
 
 KBUILD_CFLAGS += -march=$(riscv-march-cflags-y)
 KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
-- 
2.27.0


  parent reply	other threads:[~2020-06-12  7:10 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-12  7:09 [PATCH v6 00/13] riscv: Add vector ISA support Greentime Hu
2020-06-12  7:09 ` [PATCH 01/13] ptrace: Use regset_size() for dynamic regset Greentime Hu
2020-06-12  7:09 ` [PATCH 02/13] riscv: Separate patch for cflags and aflags Greentime Hu
2020-06-12  7:09 ` [PATCH 03/13] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-06-12  7:09 ` [PATCH 04/13] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-06-12  7:09 ` [PATCH 05/13] riscv: Add new csr defines related to vector extension Greentime Hu
2020-06-12  7:09 ` Greentime Hu [this message]
2020-06-12  7:09 ` [PATCH 07/13] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-06-12  7:09 ` [PATCH 08/13] riscv: Reset vector register Greentime Hu
2020-06-12  7:09 ` [PATCH 09/13] riscv: Add vector struct and assembler definitions Greentime Hu
2020-06-12  7:09 ` [PATCH 10/13] riscv: Add task switch support for vector Greentime Hu
2020-06-12  7:10 ` [PATCH 11/13] riscv: Add ptrace vector support Greentime Hu
2020-06-12  7:10 ` [PATCH 12/13] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-06-12  7:10 ` [PATCH 13/13] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu

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