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From: Stafford Horne <shorne@gmail.com>
To: peter.maydell@linaro.org
Cc: QEMU Development <qemu-devel@nongnu.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PULL 04/11] target/openrisc: Fixes for memory debugging
Date: Mon,  1 May 2017 08:14:18 +0900	[thread overview]
Message-ID: <d7f2141c62e684e5156892055e43d36194b4ff25.1493593744.git.shorne@gmail.com> (raw)
In-Reply-To: <cover.1493593744.git.shorne@gmail.com>
In-Reply-To: <cover.1493593744.git.shorne@gmail.com>

When debugging in gdb you might want to inspect instructions in mapped
pages or in exception vectors like 0x800 etc.  This was previously not
possible in qemu since the *get_phys_page_debug() routine only looked
into the data tlb.

Change to fall back to look into instruction tlb and plain physical
pages.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 target/openrisc/mmu.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 56b11d3..a6d7bcd 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -124,7 +124,7 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
 {
     int ret = TLBRET_MATCH;
 
-    if (rw == 2) {    /* ITLB */
+    if (rw == MMU_INST_FETCH) {    /* ITLB */
        *physical = 0;
         ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,
                                                           prot, address, rw);
@@ -221,12 +221,27 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
     hwaddr phys_addr;
     int prot;
+    int miss;
 
-    if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) {
-        return -1;
+    /* Check memory for any kind of address, since during debug the
+       gdb can ask for anything, check data tlb for address */
+    miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
+
+    /* Check instruction tlb */
+    if (miss) {
+        miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH);
+    }
+
+    /* Last, fall back to a plain address */
+    if (miss) {
+        miss = cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0);
     }
 
-    return phys_addr;
+    if (miss) {
+        return -1;
+    } else {
+        return phys_addr;
+    }
 }
 
 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
-- 
2.9.3

  parent reply	other threads:[~2017-04-30 23:15 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-30 23:14 [Qemu-devel] [PULL 00/11] Fixes and features for OpenRISC Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 01/11] MAINTAINERS: Add myself as openrisc maintainer Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 02/11] target/openrisc: Implement EVBAR register Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 03/11] target/openrisc: Implement EPH bit Stafford Horne
2017-04-30 23:14 ` Stafford Horne [this message]
2017-04-30 23:14 ` [Qemu-devel] [PULL 05/11] target/openrisc: add numcores and coreid support Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 06/11] migration: Add VMSTATE_UINTTL_2DARRAY() Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 07/11] target/openrisc: implement shadow registers Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 08/11] migration: Add VMSTATE_STRUCT_2DARRAY() Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 09/11] target/openrisc: Implement full vmstate serialization Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 10/11] target/openrisc: Remove duplicate features property Stafford Horne
2017-04-30 23:14 ` [Qemu-devel] [PULL 11/11] target/openrisc: Support non-busy idle state using PMR SPR Stafford Horne
2017-05-01  0:06 ` [Qemu-devel] [PULL 00/11] Fixes and features for OpenRISC no-reply
2017-05-02 14:20 ` Stefan Hajnoczi
2017-05-02 15:05   ` Stafford Horne

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