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From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Conor Dooley <conor@kernel.org>
Cc: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
	<robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <vigneshr@ti.com>,
	<afd@ti.com>, <srk@ti.com>, <s-vadapalli@ti.com>
Subject: Re: [PATCH v2] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC
Date: Mon, 22 Jan 2024 15:31:11 +0530	[thread overview]
Message-ID: <f0d41955-6eaa-4931-a65e-84e1906ff0b1@ti.com> (raw)
In-Reply-To: <20240122-getting-drippy-bb22a0634092@spud>

Hello Conor,

On 22/01/24 15:17, Conor Dooley wrote:
> On Mon, Jan 22, 2024 at 12:14:57PM +0530, Siddharth Vadapalli wrote:
>> TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
>> The controller on J722S SoC is similar to the one present on TI's AM64
>> SoC, with the difference being that the controller on AM64 SoC supports
>> up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.
>>
>> Update the bindings with a new compatible for J722S SoC.
> 
> Since the difference is just that this device supports a higher link
> speed, should it not have a fallback compatible to the am64 variant?
> Or is the programming model different for this device for the lower link
> speeds different?

Thank you for reviewing the patch. I shall add the same fallback compatible that
am64 has which is "ti,j721e-pcie-host". I will post the v3 patch with this
change if that's acceptable.

-- 
Regards,
Siddharth.

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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Conor Dooley <conor@kernel.org>
Cc: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
	<robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <vigneshr@ti.com>,
	<afd@ti.com>, <srk@ti.com>, <s-vadapalli@ti.com>
Subject: Re: [PATCH v2] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC
Date: Mon, 22 Jan 2024 15:31:11 +0530	[thread overview]
Message-ID: <f0d41955-6eaa-4931-a65e-84e1906ff0b1@ti.com> (raw)
In-Reply-To: <20240122-getting-drippy-bb22a0634092@spud>

Hello Conor,

On 22/01/24 15:17, Conor Dooley wrote:
> On Mon, Jan 22, 2024 at 12:14:57PM +0530, Siddharth Vadapalli wrote:
>> TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
>> The controller on J722S SoC is similar to the one present on TI's AM64
>> SoC, with the difference being that the controller on AM64 SoC supports
>> up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.
>>
>> Update the bindings with a new compatible for J722S SoC.
> 
> Since the difference is just that this device supports a higher link
> speed, should it not have a fallback compatible to the am64 variant?
> Or is the programming model different for this device for the lower link
> speeds different?

Thank you for reviewing the patch. I shall add the same fallback compatible that
am64 has which is "ti,j721e-pcie-host". I will post the v3 patch with this
change if that's acceptable.

-- 
Regards,
Siddharth.

  reply	other threads:[~2024-01-22 10:02 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-22  6:44 [PATCH v2] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC Siddharth Vadapalli
2024-01-22  6:44 ` Siddharth Vadapalli
2024-01-22  9:47 ` Conor Dooley
2024-01-22  9:47   ` Conor Dooley
2024-01-22 10:01   ` Siddharth Vadapalli [this message]
2024-01-22 10:01     ` Siddharth Vadapalli

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