soc.lore.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v5 0/1] Add support for the Mercury+ AA1 module
@ 2021-10-21 15:17 Paweł Anikiel
  2021-10-21 15:17 ` Paweł Anikiel
                   ` (2 more replies)
  0 siblings, 3 replies; 10+ messages in thread
From: Paweł Anikiel @ 2021-10-21 15:17 UTC (permalink / raw)
  To: arnd, olof, soc, robh+dt, dinguyen
  Cc: linux-arm-kernel, devicetree, linux-kernel, upstream, mw, ka,
	jam, tn, amstan, Paweł Anikiel

The following patches add support for the Mercury+ AA1 with an
Arria 10 SoCFPGA.

This version is almost the same as v3, only difference is having
devicetree Makefile entries for arria10_* sorted.

v5:
* revert `move devicetree aliases to socfpga_arria10.dtsi`

v4:
* move devicetree aliases to socfpga_arria10.dtsi
* sort arria10 entries in arch/arm/boot/dts/Makefile

v3:
* replace i2c busno property with devicetree aliases
* reset controller patch added to Philipp Zabel's tree

v2:
* remove spi flash node
* rename memory and mdio nodes
* add gpio nodes
* add busno property to designware i2c driver

Paweł Anikiel (1):
  dts: socfpga: Add Mercury+ AA1 devicetree

 arch/arm/boot/dts/Makefile                    |   1 +
 .../boot/dts/socfpga_arria10_mercury_aa1.dts  | 112 ++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts

-- 
2.25.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH v5 0/1] Add support for the Mercury+ AA1 module
  2021-10-21 15:17 [PATCH v5 0/1] Add support for the Mercury+ AA1 module Paweł Anikiel
@ 2021-10-21 15:17 ` Paweł Anikiel
  2021-10-21 15:17 ` [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree Paweł Anikiel
  2021-10-22 20:10 ` [PATCH v5 0/1] Add support for the Mercury+ AA1 module patchwork-bot+linux-soc
  2 siblings, 0 replies; 10+ messages in thread
From: Paweł Anikiel @ 2021-10-21 15:17 UTC (permalink / raw)
  To: arnd, olof, soc, robh+dt, dinguyen
  Cc: linux-arm-kernel, devicetree, linux-kernel, upstream, mw, ka,
	jam, tn, amstan, Paweł Anikiel

The following patches add support for the Mercury+ AA1 with an
Arria 10 SoCFPGA.

This version is almost the same as v3, only difference is having
devicetree Makefile entries for arria10_* sorted.

v5:
* revert `move devicetree aliases to socfpga_arria10.dtsi`

v4:
* move devicetree aliases to socfpga_arria10.dtsi
* sort arria10 entries in arch/arm/boot/dts/Makefile

v3:
* replace i2c busno property with devicetree aliases
* reset controller patch added to Philipp Zabel's tree

v2:
* remove spi flash node
* rename memory and mdio nodes
* add gpio nodes
* add busno property to designware i2c driver

Paweł Anikiel (1):
  dts: socfpga: Add Mercury+ AA1 devicetree

 arch/arm/boot/dts/Makefile                    |   1 +
 .../boot/dts/socfpga_arria10_mercury_aa1.dts  | 112 ++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts

-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree
  2021-10-21 15:17 [PATCH v5 0/1] Add support for the Mercury+ AA1 module Paweł Anikiel
  2021-10-21 15:17 ` Paweł Anikiel
@ 2021-10-21 15:17 ` Paweł Anikiel
  2021-10-21 15:17   ` Paweł Anikiel
  2021-10-21 15:34   ` Arnd Bergmann
  2021-10-22 20:10 ` [PATCH v5 0/1] Add support for the Mercury+ AA1 module patchwork-bot+linux-soc
  2 siblings, 2 replies; 10+ messages in thread
From: Paweł Anikiel @ 2021-10-21 15:17 UTC (permalink / raw)
  To: arnd, olof, soc, robh+dt, dinguyen
  Cc: linux-arm-kernel, devicetree, linux-kernel, upstream, mw, ka,
	jam, tn, amstan, Paweł Anikiel, Joanna Brozek,
	Mariusz Glebocki, Tomasz Gorochowik, Maciej Mikunda

Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com>
---
 arch/arm/boot/dts/Makefile                    |   1 +
 .../boot/dts/socfpga_arria10_mercury_aa1.dts  | 112 ++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e0934180724..803702883122 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1075,6 +1075,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
 	s5pv210-torbreck.dtb
 dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
 	socfpga_arria5_socdk.dtb \
+	socfpga_arria10_mercury_aa1.dtb \
 	socfpga_arria10_socdk_nand.dtb \
 	socfpga_arria10_socdk_qspi.dtb \
 	socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
new file mode 100644
index 000000000000..2a3364b26361
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "socfpga_arria10.dtsi"
+
+/ {
+
+	model = "Enclustra Mercury AA1";
+	compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+	aliases {
+		ethernet0 = &gmac0;
+		serial1 = &uart1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x80000000>; /* 2GB */
+	};
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+};
+
+&eccmgr {
+	sdmmca-ecc@ff8c2c00 {
+		compatible = "altr,socfpga-sdmmc-ecc";
+		reg = <0xff8c2c00 0x400>;
+		altr,ecc-parent = <&mmc>;
+		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+			     <47 IRQ_TYPE_LEVEL_HIGH>,
+			     <16 IRQ_TYPE_LEVEL_HIGH>,
+			     <48 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	phy-addr = <0xffffffff>; /* probe for phy addr */
+
+	max-frame-size = <3800>;
+	status = "okay";
+
+	phy-handle = <&phy3>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy3: ethernet-phy@3 {
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <1860>; /* 960ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+			reg = <3>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	isl12022: isl12022@6f {
+		status = "okay";
+		compatible = "isil,isl12022";
+		reg = <0x6f>;
+	};
+};
+
+/* Following mappings are taken from arria10 socdk dts */
+&mmc {
+	status = "okay";
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+};
+
+&osc1 {
+	clock-frequency = <33330000>;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree
  2021-10-21 15:17 ` [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree Paweł Anikiel
@ 2021-10-21 15:17   ` Paweł Anikiel
  2021-10-21 15:34   ` Arnd Bergmann
  1 sibling, 0 replies; 10+ messages in thread
From: Paweł Anikiel @ 2021-10-21 15:17 UTC (permalink / raw)
  To: arnd, olof, soc, robh+dt, dinguyen
  Cc: linux-arm-kernel, devicetree, linux-kernel, upstream, mw, ka,
	jam, tn, amstan, Paweł Anikiel, Joanna Brozek,
	Mariusz Glebocki, Tomasz Gorochowik, Maciej Mikunda

Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com>
---
 arch/arm/boot/dts/Makefile                    |   1 +
 .../boot/dts/socfpga_arria10_mercury_aa1.dts  | 112 ++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e0934180724..803702883122 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1075,6 +1075,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
 	s5pv210-torbreck.dtb
 dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
 	socfpga_arria5_socdk.dtb \
+	socfpga_arria10_mercury_aa1.dtb \
 	socfpga_arria10_socdk_nand.dtb \
 	socfpga_arria10_socdk_qspi.dtb \
 	socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
new file mode 100644
index 000000000000..2a3364b26361
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "socfpga_arria10.dtsi"
+
+/ {
+
+	model = "Enclustra Mercury AA1";
+	compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+	aliases {
+		ethernet0 = &gmac0;
+		serial1 = &uart1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x80000000>; /* 2GB */
+	};
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+};
+
+&eccmgr {
+	sdmmca-ecc@ff8c2c00 {
+		compatible = "altr,socfpga-sdmmc-ecc";
+		reg = <0xff8c2c00 0x400>;
+		altr,ecc-parent = <&mmc>;
+		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+			     <47 IRQ_TYPE_LEVEL_HIGH>,
+			     <16 IRQ_TYPE_LEVEL_HIGH>,
+			     <48 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	phy-addr = <0xffffffff>; /* probe for phy addr */
+
+	max-frame-size = <3800>;
+	status = "okay";
+
+	phy-handle = <&phy3>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy3: ethernet-phy@3 {
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <1860>; /* 960ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+			reg = <3>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	isl12022: isl12022@6f {
+		status = "okay";
+		compatible = "isil,isl12022";
+		reg = <0x6f>;
+	};
+};
+
+/* Following mappings are taken from arria10 socdk dts */
+&mmc {
+	status = "okay";
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+};
+
+&osc1 {
+	clock-frequency = <33330000>;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree
  2021-10-21 15:17 ` [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree Paweł Anikiel
  2021-10-21 15:17   ` Paweł Anikiel
@ 2021-10-21 15:34   ` Arnd Bergmann
  2021-10-21 15:34     ` Arnd Bergmann
                       ` (2 more replies)
  1 sibling, 3 replies; 10+ messages in thread
From: Arnd Bergmann @ 2021-10-21 15:34 UTC (permalink / raw)
  To: Paweł Anikiel
  Cc: Arnd Bergmann, Olof Johansson, SoC Team, Rob Herring,
	Dinh Nguyen, Linux ARM, DTML, Linux Kernel Mailing List,
	upstream, Marcin Wojtas, Konrad Adamczyk, Jacek Majkowski,
	Tomasz Nowicki, Alexandru Stan, Joanna Brozek, Mariusz Glebocki,
	Tomasz Gorochowik, Maciej Mikunda

On Thu, Oct 21, 2021 at 5:17 PM Paweł Anikiel <pan@semihalf.com> wrote:
>
> Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.
>
> Signed-off-by: Paweł Anikiel <pan@semihalf.com>
> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com>

Thank you for the respin, looks good to me now.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

Dinh, are you planning to pick this up into your socfpga tree, or
should I apply it directly to the soc tree this time?

        Arnd

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree
  2021-10-21 15:34   ` Arnd Bergmann
  2021-10-21 15:34     ` Arnd Bergmann
@ 2021-10-21 15:34     ` Arnd Bergmann
  2021-10-21 22:10     ` Dinh Nguyen
  2 siblings, 0 replies; 10+ messages in thread
From: Arnd Bergmann @ 2021-10-21 15:34 UTC (permalink / raw)
  To: Paweł Anikiel
  Cc: Arnd Bergmann, Olof Johansson, SoC Team, Rob Herring,
	Dinh Nguyen, Linux ARM, DTML, Linux Kernel Mailing List,
	upstream, Marcin Wojtas, Konrad Adamczyk, Jacek Majkowski,
	Tomasz Nowicki, Alexandru Stan, Joanna Brozek, Mariusz Glebocki,
	Tomasz Gorochowik, Maciej Mikunda

On Thu, Oct 21, 2021 at 5:17 PM Paweł Anikiel <pan@semihalf.com> wrote:
>
> Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.
>
> Signed-off-by: Paweł Anikiel <pan@semihalf.com>
> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com>

Thank you for the respin, looks good to me now.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

Dinh, are you planning to pick this up into your socfpga tree, or
should I apply it directly to the soc tree this time?

        Arnd

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree
  2021-10-21 15:34   ` Arnd Bergmann
@ 2021-10-21 15:34     ` Arnd Bergmann
  2021-10-21 15:34     ` Arnd Bergmann
  2021-10-21 22:10     ` Dinh Nguyen
  2 siblings, 0 replies; 10+ messages in thread
From: Arnd Bergmann @ 2021-10-21 15:34 UTC (permalink / raw)
  To: Paweł Anikiel
  Cc: Arnd Bergmann, Olof Johansson, SoC Team, Rob Herring,
	Dinh Nguyen, Linux ARM, DTML, Linux Kernel Mailing List,
	upstream, Marcin Wojtas, Konrad Adamczyk, Jacek Majkowski,
	Tomasz Nowicki, Alexandru Stan, Joanna Brozek, Mariusz Glebocki,
	Tomasz Gorochowik, Maciej Mikunda

On Thu, Oct 21, 2021 at 5:17 PM Paweł Anikiel <pan@semihalf.com> wrote:
>
> Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.
>
> Signed-off-by: Paweł Anikiel <pan@semihalf.com>
> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com>

Thank you for the respin, looks good to me now.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

Dinh, are you planning to pick this up into your socfpga tree, or
should I apply it directly to the soc tree this time?

        Arnd

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree
  2021-10-21 15:34   ` Arnd Bergmann
  2021-10-21 15:34     ` Arnd Bergmann
  2021-10-21 15:34     ` Arnd Bergmann
@ 2021-10-21 22:10     ` Dinh Nguyen
  2021-10-21 22:10       ` Dinh Nguyen
  2 siblings, 1 reply; 10+ messages in thread
From: Dinh Nguyen @ 2021-10-21 22:10 UTC (permalink / raw)
  To: Arnd Bergmann, Paweł Anikiel
  Cc: Olof Johansson, SoC Team, Rob Herring, Linux ARM, DTML,
	Linux Kernel Mailing List, upstream, Marcin Wojtas,
	Konrad Adamczyk, Jacek Majkowski, Tomasz Nowicki, Alexandru Stan,
	Joanna Brozek, Mariusz Glebocki, Tomasz Gorochowik,
	Maciej Mikunda



On 10/21/21 10:34 AM, Arnd Bergmann wrote:
> On Thu, Oct 21, 2021 at 5:17 PM Paweł Anikiel <pan@semihalf.com> wrote:
>>
>> Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.
>>
>> Signed-off-by: Paweł Anikiel <pan@semihalf.com>
>> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
>> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
>> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
>> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com>
> 
> Thank you for the respin, looks good to me now.
> 
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> 
> Dinh, are you planning to pick this up into your socfpga tree, or
> should I apply it directly to the soc tree this time?
> 

If you don't mind, please apply it directly to the soc tree.

Thanks,
Dinh

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree
  2021-10-21 22:10     ` Dinh Nguyen
@ 2021-10-21 22:10       ` Dinh Nguyen
  0 siblings, 0 replies; 10+ messages in thread
From: Dinh Nguyen @ 2021-10-21 22:10 UTC (permalink / raw)
  To: Arnd Bergmann, Paweł Anikiel
  Cc: Olof Johansson, SoC Team, Rob Herring, Linux ARM, DTML,
	Linux Kernel Mailing List, upstream, Marcin Wojtas,
	Konrad Adamczyk, Jacek Majkowski, Tomasz Nowicki, Alexandru Stan,
	Joanna Brozek, Mariusz Glebocki, Tomasz Gorochowik,
	Maciej Mikunda



On 10/21/21 10:34 AM, Arnd Bergmann wrote:
> On Thu, Oct 21, 2021 at 5:17 PM Paweł Anikiel <pan@semihalf.com> wrote:
>>
>> Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.
>>
>> Signed-off-by: Paweł Anikiel <pan@semihalf.com>
>> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
>> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
>> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
>> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com>
> 
> Thank you for the respin, looks good to me now.
> 
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> 
> Dinh, are you planning to pick this up into your socfpga tree, or
> should I apply it directly to the soc tree this time?
> 

If you don't mind, please apply it directly to the soc tree.

Thanks,
Dinh

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 0/1] Add support for the Mercury+ AA1 module
  2021-10-21 15:17 [PATCH v5 0/1] Add support for the Mercury+ AA1 module Paweł Anikiel
  2021-10-21 15:17 ` Paweł Anikiel
  2021-10-21 15:17 ` [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree Paweł Anikiel
@ 2021-10-22 20:10 ` patchwork-bot+linux-soc
  2 siblings, 0 replies; 10+ messages in thread
From: patchwork-bot+linux-soc @ 2021-10-22 20:10 UTC (permalink / raw)
  To: =?utf-8?b?UGF3ZcWCIEFuaWtpZWwgPHBhbkBzZW1paGFsZi5jb20+?=; +Cc: soc

Hello:

This patch was applied to soc/soc.git (for-next)
by Arnd Bergmann <arnd@arndb.de>:

On Thu, 21 Oct 2021 17:17:35 +0200 you wrote:
> The following patches add support for the Mercury+ AA1 with an
> Arria 10 SoCFPGA.
> 
> This version is almost the same as v3, only difference is having
> devicetree Makefile entries for arria10_* sorted.
> 
> v5:
> * revert `move devicetree aliases to socfpga_arria10.dtsi`
> 
> [...]

Here is the summary with links:
  - [v5,1/1] dts: socfpga: Add Mercury+ AA1 devicetree
    https://git.kernel.org/soc/soc/c/8f0450c51148

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-10-22 20:10 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-21 15:17 [PATCH v5 0/1] Add support for the Mercury+ AA1 module Paweł Anikiel
2021-10-21 15:17 ` Paweł Anikiel
2021-10-21 15:17 ` [PATCH v5 1/1] dts: socfpga: Add Mercury+ AA1 devicetree Paweł Anikiel
2021-10-21 15:17   ` Paweł Anikiel
2021-10-21 15:34   ` Arnd Bergmann
2021-10-21 15:34     ` Arnd Bergmann
2021-10-21 15:34     ` Arnd Bergmann
2021-10-21 22:10     ` Dinh Nguyen
2021-10-21 22:10       ` Dinh Nguyen
2021-10-22 20:10 ` [PATCH v5 0/1] Add support for the Mercury+ AA1 module patchwork-bot+linux-soc

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).