* fix a few RISC-V / renesas Kconfig dependencies v2
@ 2023-10-18 5:26 Christoph Hellwig
2023-10-18 5:26 ` [PATCH 1/3] riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT Christoph Hellwig
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Christoph Hellwig @ 2023-10-18 5:26 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Conor Dooley, Geert Uytterhoeven,
Magnus Damm
Cc: linux-riscv, linux-renesas-soc, Arnd Bergmann, Olof Johansson,
Samuel Holland, soc
Hi all,
this small series sorts out a few Kconfig dependency issue for the
rich set of RISC-V non-coherent DMA support.
Geert suggested for it to go into the soc tree, which is fine with me
if I get a stable branch for it as it is required for further dma-mapping
work.
Changes since v1:
- select DMA_DIRECT_REMAP from ERRATA_THEAD_CMO
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
2023-10-18 5:26 fix a few RISC-V / renesas Kconfig dependencies v2 Christoph Hellwig
@ 2023-10-18 5:26 ` Christoph Hellwig
2023-10-18 5:26 ` [PATCH 2/3] riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT Christoph Hellwig
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Christoph Hellwig @ 2023-10-18 5:26 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Conor Dooley, Geert Uytterhoeven,
Magnus Damm
Cc: linux-riscv, linux-renesas-soc, Arnd Bergmann, Olof Johansson,
Samuel Holland, soc, Conor Dooley
RISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenance
helpers, which are built into the kernel unconditionally.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/Kconfig | 1 -
drivers/cache/Kconfig | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d607ab0f7c6daf..0ac0b538379718 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -277,7 +277,6 @@ config RISCV_DMA_NONCOHERENT
config RISCV_NONSTANDARD_CACHE_OPS
bool
- depends on RISCV_DMA_NONCOHERENT
help
This enables function pointer support for non-standard noncoherent
systems to handle cache management.
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index a57677f908f3ba..d6e5e3abaad8af 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -3,7 +3,7 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller"
- depends on RISCV_DMA_NONCOHERENT
+ depends on RISCV
select RISCV_NONSTANDARD_CACHE_OPS
help
Support for the L2 cache controller on Andes Technology AX45MP platforms.
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
2023-10-18 5:26 fix a few RISC-V / renesas Kconfig dependencies v2 Christoph Hellwig
2023-10-18 5:26 ` [PATCH 1/3] riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT Christoph Hellwig
@ 2023-10-18 5:26 ` Christoph Hellwig
2023-10-18 18:42 ` Samuel Holland
2023-10-18 5:26 ` [PATCH 3/3] soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM Christoph Hellwig
2023-10-26 9:22 ` fix a few RISC-V / renesas Kconfig dependencies v2 Geert Uytterhoeven
3 siblings, 1 reply; 7+ messages in thread
From: Christoph Hellwig @ 2023-10-18 5:26 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Conor Dooley, Geert Uytterhoeven,
Magnus Damm
Cc: linux-riscv, linux-renesas-soc, Arnd Bergmann, Olof Johansson,
Samuel Holland, soc, Conor Dooley, Robin Murphy, Lad Prabhakar
RISCV_DMA_NONCOHERENT is also used for whacky non-standard
non-coherent ops that use different hooks in dma-direct.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/Kconfig | 2 +-
arch/riscv/Kconfig.errata | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0ac0b538379718..9c48fecc671918 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -273,7 +273,6 @@ config RISCV_DMA_NONCOHERENT
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB
- select DMA_DIRECT_REMAP if MMU
config RISCV_NONSTANDARD_CACHE_OPS
bool
@@ -549,6 +548,7 @@ config RISCV_ISA_ZICBOM
depends on RISCV_ALTERNATIVE
default y
select RISCV_DMA_NONCOHERENT
+ select DMA_DIRECT_REMAP
help
Adds support to dynamically detect the presence of the ZICBOM
extension (Cache Block Management Operations) and enable its
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 566bcefeab502c..e2c731cfed8cc6 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -77,6 +77,7 @@ config ERRATA_THEAD_PBMT
config ERRATA_THEAD_CMO
bool "Apply T-Head cache management errata"
depends on ERRATA_THEAD && MMU
+ select DMA_DIRECT_REMAP
select RISCV_DMA_NONCOHERENT
default y
help
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
2023-10-18 5:26 fix a few RISC-V / renesas Kconfig dependencies v2 Christoph Hellwig
2023-10-18 5:26 ` [PATCH 1/3] riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT Christoph Hellwig
2023-10-18 5:26 ` [PATCH 2/3] riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT Christoph Hellwig
@ 2023-10-18 5:26 ` Christoph Hellwig
2023-10-26 9:22 ` fix a few RISC-V / renesas Kconfig dependencies v2 Geert Uytterhoeven
3 siblings, 0 replies; 7+ messages in thread
From: Christoph Hellwig @ 2023-10-18 5:26 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Conor Dooley, Geert Uytterhoeven,
Magnus Damm
Cc: linux-riscv, linux-renesas-soc, Arnd Bergmann, Olof Johansson,
Samuel Holland, soc, Lad Prabhakar, Conor Dooley
ARCH_R9A07G043 has its own non-standard global pool based DMA coherent
allocator, which conflicts with the remap based RISCV_ISA_ZICBOM version.
Add a proper dependency.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/soc/renesas/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 335251ff6e8214..624185e09c967b 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -341,6 +341,7 @@ config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five"
depends on NONPORTABLE
depends on RISCV_ALTERNATIVE
+ depends on !RISCV_ISA_ZICBOM
depends on RISCV_SBI
select ARCH_RZG2L
select AX45MP_L2_CACHE
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
2023-10-18 5:26 ` [PATCH 2/3] riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT Christoph Hellwig
@ 2023-10-18 18:42 ` Samuel Holland
0 siblings, 0 replies; 7+ messages in thread
From: Samuel Holland @ 2023-10-18 18:42 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-riscv, linux-renesas-soc, Arnd Bergmann, Olof Johansson,
soc, Conor Dooley, Robin Murphy, Lad Prabhakar, Paul Walmsley,
Palmer Dabbelt, Conor Dooley, Geert Uytterhoeven, Magnus Damm
On 2023-10-18 12:26 AM, Christoph Hellwig wrote:
> RISCV_DMA_NONCOHERENT is also used for whacky non-standard
> non-coherent ops that use different hooks in dma-direct.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/riscv/Kconfig | 2 +-
> arch/riscv/Kconfig.errata | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
Tested-by: Samuel Holland <samuel.holland@sifive.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: fix a few RISC-V / renesas Kconfig dependencies v2
2023-10-18 5:26 fix a few RISC-V / renesas Kconfig dependencies v2 Christoph Hellwig
` (2 preceding siblings ...)
2023-10-18 5:26 ` [PATCH 3/3] soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM Christoph Hellwig
@ 2023-10-26 9:22 ` Geert Uytterhoeven
3 siblings, 0 replies; 7+ messages in thread
From: Geert Uytterhoeven @ 2023-10-26 9:22 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Paul Walmsley, Palmer Dabbelt, Conor Dooley, Magnus Damm,
linux-riscv, linux-renesas-soc, Arnd Bergmann, Olof Johansson,
Samuel Holland, soc
Hi Christoph,
On Wed, Oct 18, 2023 at 7:27 AM Christoph Hellwig <hch@lst.de> wrote:
> this small series sorts out a few Kconfig dependency issue for the
> rich set of RISC-V non-coherent DMA support.
Thanks for your series!
> Geert suggested for it to go into the soc tree, which is fine with me
> if I get a stable branch for it as it is required for further dma-mapping
> work.
As Arnd asked me to send a PR to him, I'm queuing these in
renesas-fixes, and will send a PR momentarily.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/3] soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
2023-10-17 13:59 fix a few RISC-V / renesas Kconfig dependencies Christoph Hellwig
@ 2023-10-17 13:59 ` Christoph Hellwig
0 siblings, 0 replies; 7+ messages in thread
From: Christoph Hellwig @ 2023-10-17 13:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Conor Dooley, Geert Uytterhoeven,
Magnus Damm
Cc: linux-riscv, linux-renesas-soc, Arnd Bergmann, Olof Johansson,
soc, Lad Prabhakar, Conor Dooley
ARCH_R9A07G043 has its own non-standard global pool based DMA coherent
allocator, which conflicts with the remap based RISCV_ISA_ZICBOM version.
Add a proper dependency.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/soc/renesas/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 335251ff6e8214..624185e09c967b 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -341,6 +341,7 @@ config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five"
depends on NONPORTABLE
depends on RISCV_ALTERNATIVE
+ depends on !RISCV_ISA_ZICBOM
depends on RISCV_SBI
select ARCH_RZG2L
select AX45MP_L2_CACHE
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-10-26 9:22 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2023-10-18 5:26 fix a few RISC-V / renesas Kconfig dependencies v2 Christoph Hellwig
2023-10-18 5:26 ` [PATCH 1/3] riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT Christoph Hellwig
2023-10-18 5:26 ` [PATCH 2/3] riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT Christoph Hellwig
2023-10-18 18:42 ` Samuel Holland
2023-10-18 5:26 ` [PATCH 3/3] soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM Christoph Hellwig
2023-10-26 9:22 ` fix a few RISC-V / renesas Kconfig dependencies v2 Geert Uytterhoeven
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