From: Benjamin Fair <benjaminfair@google.com> To: Tomer Maimon <tmaimon77@gmail.com> Cc: Joel Stanley <joel@jms.id.au>, Arnd Bergmann <arnd@arndb.de>, olof@lixom.net, arm@kernel.org, soc@kernel.org, avifishman70@gmail.com, Rob Herring <robh+dt@kernel.org>, mark.rutland@arm.com, Nancy Yuen <yuenn@google.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, OpenBMC Maillist <openbmc@lists.ozlabs.org> Subject: Re: [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree Date: Thu, 19 Nov 2020 10:39:48 -0800 [thread overview] Message-ID: <CADKL2t45q907QGpq9rqjnGgMx=43Gz4RRGbyRLZUozYD0kt-DQ@mail.gmail.com> (raw) In-Reply-To: <20201119080002.100342-1-tmaimon77@gmail.com> On Thu, 19 Nov 2020 at 00:00, Tomer Maimon <tmaimon77@gmail.com> wrote: > > Add Nuvoton NPCM730 SoC device tree. > > The Nuvoton NPCN730 SoC is a part of the > Nuvoton NPCM7xx SoCs family. > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> > > --- > arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi > > diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > new file mode 100644 > index 000000000000..86ec12ec2b50 > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > @@ -0,0 +1,44 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2020 Nuvoton Technology > + > +#include "nuvoton-common-npcm7xx.dtsi" > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "nuvoton,npcm750-smp"; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&l2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&l2>; > + }; > + }; > + > + soc { > + timer@3fe600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x3fe600 0x20>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_HIGH)>; > + clocks = <&clk NPCM7XX_CLK_AHB>; > + }; > + }; > +}; > -- > 2.22.0 >
WARNING: multiple messages have this Message-ID (diff)
From: Benjamin Fair <benjaminfair@google.com> To: Tomer Maimon <tmaimon77@gmail.com> Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>, avifishman70@gmail.com, OpenBMC Maillist <openbmc@lists.ozlabs.org>, linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, soc@kernel.org, arm@kernel.org, olof@lixom.net Subject: Re: [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree Date: Thu, 19 Nov 2020 10:39:48 -0800 [thread overview] Message-ID: <CADKL2t45q907QGpq9rqjnGgMx=43Gz4RRGbyRLZUozYD0kt-DQ@mail.gmail.com> (raw) Message-ID: <20201119183948.ZGXdazSKNfqm3kOQt7Ia-YzVADnmmIjhU9u0mtdux0E@z> (raw) In-Reply-To: <20201119080002.100342-1-tmaimon77@gmail.com> On Thu, 19 Nov 2020 at 00:00, Tomer Maimon <tmaimon77@gmail.com> wrote: > > Add Nuvoton NPCM730 SoC device tree. > > The Nuvoton NPCN730 SoC is a part of the > Nuvoton NPCM7xx SoCs family. > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> > > --- > arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi > > diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > new file mode 100644 > index 000000000000..86ec12ec2b50 > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > @@ -0,0 +1,44 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2020 Nuvoton Technology > + > +#include "nuvoton-common-npcm7xx.dtsi" > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "nuvoton,npcm750-smp"; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&l2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&l2>; > + }; > + }; > + > + soc { > + timer@3fe600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x3fe600 0x20>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_HIGH)>; > + clocks = <&clk NPCM7XX_CLK_AHB>; > + }; > + }; > +}; > -- > 2.22.0 >
next prev parent reply other threads:[~2020-11-19 18:40 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-19 8:00 [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree Tomer Maimon 2020-11-19 8:00 ` Tomer Maimon 2020-11-19 18:39 ` Benjamin Fair [this message] 2020-11-19 18:39 ` Benjamin Fair 2020-11-19 18:39 ` Benjamin Fair 2020-11-23 16:52 ` Arnd Bergmann 2020-11-23 16:52 ` Arnd Bergmann
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