[PATCH v3 00/20] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board

[PATCH v3 00/20] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board

[Peter Griffin]

Hi folks,

Firstly, thanks to everyone who reviewed the v2/V1 series! V3 incorporates
all the review feedback received so far.

As this series spans multiple subsytems the expectation is that Krzysztof
will apply the whole series through the Samsung SoC tree. If the relevant
subsystem maintainers can give a acked-by or reviewed-by on the relevant
patches that would be most appreciated!

This series adds initial SoC support for the GS101 SoC and also initial board
support for Pixel 6 phone (Oriole).

The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro
(raven) phones. Currently DT is added for the gs101 SoC and Oriole.
As you can see from the patches the SoC is based on a Samsung Exynos SoC,
and therefore lots of the low level Exynos drivers and bindings can be
re-used.

The support added in this series consists of:
* cpus
* pinctrl
* some CCF implementation
* watchdog
* uart
* gpio

This is enough to boot through to a busybox initramfs and shell using an
upstream kernel though :) More platform support will be added over the
following weeks and months.

For further information on how to build and flash the upstream kernel on your
Pixel 6, with a prebuilt busybox initramfs please refer to the script and
README.md here:

https://git.codelinaro.org/linaro/googlelt/pixelscripts

Note 1: I've removed the dtbo overlay from v2 and later submissions and
will re-submit once I have appropriate documentation for it.

Note 2: I've left the bootargs in dts with earlycon for now, for two reasons.
1) The bootloader hangs if bootargs isn't present in the dtb as it tries to
re-write this with additional bootargs.
2) there is a issue whereby the full serial console doesn't come up properly
if earlycon isn't also specified. This issue needs further investigation.

kind regards,

Peter.

Changes since v2:
 - Fixup pinctrl@174d0000: interrupts: [..] is too long DTC warning (Tudor)
 - Add missing windowed watchdog code (Guenter)
 - Fixup UART YAML bindings error (Krzysztof)
 - gs101.dtsi add missing serial_0 alias (me)
 - samsung_tty.c: fixup gs101_serial_drv_data so fifosize os obtained from DT
 
Changes since v1:
 - Remove irq/gs101.h and replace macros with irq numbers globally
 - exynos-pmu - keep alphabetical order
 - add cmu_apm to clock bindings documentation
 - sysreg bindings - remove superfluous `google,gs101-sysreg`
 - watchdog bindings - Alphanumerical order, update gs201 comment
 - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC
 - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order
 - samsung,pinctrl- add google,gs101-wakeup-eint compatible
 - clk-pll: fixup typos
 - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate)
 - clk-gs101: fix alphabetical order
 - clk-gs101: cmu_apm: fixup typo and missing empty entry
 - clk-gs101: cmu_misc: remove clocks that were being registerred twice
 - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield
 - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well
 - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter
 - watchdog: s3c2410_wdt: remove dev_info prints
 - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines
   add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix
 - gs101-oriole.dtso: Remove overlay until board_id is documented properly
 - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones
 - gpio-keys: update linux,code to use input-event-code macros
 - add dedicated gs101-uart compatible

Peter Griffin (20):
  dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
  dt-bindings: clock: Add Google gs101 clock management unit bindings
  dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG
    compatibles to GS101
  dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
  dt-bindings: arm: google: Add bindings for Google ARM platforms
  dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
  dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
  dt-bindings: serial: samsung: Add google-gs101-uart compatible
  clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
  clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
  clk: samsung: clk-gs101: add CMU_APM support
  clk: samsung: clk-gs101: Add support for CMU_MISC clock unit
  pinctrl: samsung: Add filter selection support for alive banks
  pinctrl: samsung: Add gs101 SoC pinctrl configuration
  watchdog: s3c2410_wdt: Add support for Google tensor SoCs
  tty: serial: samsung: Add gs101 compatible and SoC data
  arm64: dts: google: Add initial Google gs101 SoC support
  arm64: dts: google: Add initial Oriole/pixel 6 board support
  arm64: defconfig: Enable Google Tensor SoC
  MAINTAINERS: add entry for Google Tensor SoC

 .../devicetree/bindings/arm/google.yaml       |   46 +
 .../bindings/clock/google,gs101-clock.yaml    |  125 +
 .../samsung,pinctrl-wakeup-interrupt.yaml     |    2 +
 .../bindings/pinctrl/samsung,pinctrl.yaml     |   22 +-
 .../bindings/serial/samsung_uart.yaml         |    1 +
 .../bindings/soc/samsung/exynos-pmu.yaml      |    2 +
 .../soc/samsung/samsung,exynos-sysreg.yaml    |    6 +
 .../bindings/watchdog/samsung-wdt.yaml        |   10 +-
 MAINTAINERS                                   |   10 +
 arch/arm64/Kconfig.platforms                  |    6 +
 arch/arm64/boot/dts/Makefile                  |    1 +
 arch/arm64/boot/dts/google/Makefile           |    4 +
 arch/arm64/boot/dts/google/gs101-oriole.dts   |   79 +
 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 ++++++++++
 arch/arm64/boot/dts/google/gs101-pinctrl.h    |   32 +
 arch/arm64/boot/dts/google/gs101.dtsi         |  504 ++++
 arch/arm64/configs/defconfig                  |    1 +
 drivers/clk/samsung/Kconfig                   |    9 +
 drivers/clk/samsung/Makefile                  |    2 +
 drivers/clk/samsung/clk-gs101.c               | 2164 +++++++++++++++++
 drivers/clk/samsung/clk-pll.c                 |    9 +-
 drivers/clk/samsung/clk-pll.h                 |    3 +
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    |  163 ++
 drivers/pinctrl/samsung/pinctrl-exynos.c      |   84 +-
 drivers/pinctrl/samsung/pinctrl-exynos.h      |   41 +
 drivers/pinctrl/samsung/pinctrl-samsung.c     |    4 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |   24 +
 drivers/tty/serial/samsung_tty.c              |   13 +
 drivers/watchdog/s3c2410_wdt.c                |  127 +-
 include/dt-bindings/clock/google,gs101.h      |  232 ++
 30 files changed, 4985 insertions(+), 16 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
 create mode 100644 arch/arm64/boot/dts/google/Makefile
 create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
 create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
 create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
 create mode 100644 drivers/clk/samsung/clk-gs101.c
 create mode 100644 include/dt-bindings/clock/google,gs101.h

-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 01/20] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible

[Peter Griffin]

Add gs101-pmu compatible to the bindings documentation.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
index e1d716df5dfa..9e497c310532 100644
--- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
@@ -15,6 +15,7 @@ select:
     compatible:
       contains:
         enum:
+          - google,gs101-pmu
           - samsung,exynos3250-pmu
           - samsung,exynos4210-pmu
           - samsung,exynos4212-pmu
@@ -35,6 +36,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - google,gs101-pmu
               - samsung,exynos3250-pmu
               - samsung,exynos4210-pmu
               - samsung,exynos4212-pmu
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Peter Griffin]

Provide dt-schema documentation for Google gs101 SoC clock controller.
Currently this adds support for cmu_top, cmu_misc and cmu_apm.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
 include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
 2 files changed, 357 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
 create mode 100644 include/dt-bindings/clock/google,gs101.h

diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
new file mode 100644
index 000000000000..f74494594b3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google GS101 SoC clock controller
+
+maintainers:
+  - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+  Google GS101 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. The root clock in that clock tree
+  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
+  clock in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'dt-bindings/clock/gs101.h' header.
+
+properties:
+  compatible:
+    enum:
+      - google,gs101-cmu-top
+      - google,gs101-cmu-apm
+      - google,gs101-cmu-misc
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-misc
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+            - description: Misc bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_misc_bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-apm
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+  - reg
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_TOP
+  - |
+    #include <dt-bindings/clock/google,gs101.h>
+    soc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+
+        cmu_top: clock-controller@1e080000 {
+            compatible = "google,gs101-cmu-top";
+            reg = <0x0 0x1e080000 0x8000>;
+            #clock-cells = <1>;
+            clocks = <&ext_24_5m>;
+            clock-names = "oscclk";
+        };
+    };
+
+...
diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
new file mode 100644
index 000000000000..7765ba68f734
--- /dev/null
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -0,0 +1,232 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Device Tree binding constants for Google gs101 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+
+/* CMU_TOP PLL*/
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_SHARED2_PLL		3
+#define CLK_FOUT_SHARED3_PLL		4
+#define CLK_FOUT_SPARE_PLL		5
+
+/* CMU_TOP MUX*/
+#define CLK_MOUT_SHARED0_PLL		6
+#define CLK_MOUT_SHARED1_PLL		7
+#define CLK_MOUT_SHARED2_PLL		8
+#define CLK_MOUT_SHARED3_PLL		9
+#define CLK_MOUT_SPARE_PLL		10
+#define CLK_MOUT_BUS0_BUS		11
+#define CLK_MOUT_CMU_BOOST		12
+#define CLK_MOUT_BUS1_BUS		13
+#define CLK_MOUT_BUS2_BUS		14
+#define CLK_MOUT_CORE_BUS		15
+#define CLK_MOUT_EH_BUS			16
+#define CLK_MOUT_CPUCL2_SWITCH		17
+#define CLK_MOUT_CPUCL1_SWITCH		18
+#define CLK_MOUT_CPUCL0_SWITCH		19
+#define CLK_MOUT_CPUCL0_DBG		20
+#define CLK_MOUT_CMU_HPM		21
+#define CLK_MOUT_G3D_SWITCH		22
+#define CLK_MOUT_G3D_GLB		23
+#define CLK_MOUT_DPU_BUS		24
+#define CLK_MOUT_DISP_BUS		25
+#define CLK_MOUT_G2D_G2D		26
+#define CLK_MOUT_G2D_MSCL		27
+#define CLK_MOUT_HSI0_USB31DRD		28
+#define CLK_MOUT_HSI0_BUS		29
+#define CLK_MOUT_HSI0_DPGTC		30
+#define CLK_MOUT_HSI0_USBDPDGB		31
+#define CLK_MOUT_HSI1_BUS		32
+#define CLK_MOUT_HSI1_PCIE		33
+#define CLK_MOUT_HSI2_BUS		34
+#define CLK_MOUT_HSI2_PCIE		35
+#define CLK_MOUT_HSI2_UFS_EMBD		36
+#define CLK_MOUT_HSI2_MMC_CARD		37
+#define CLK_MOUT_CSIS			38
+#define CLK_MOUT_PDP_BUS		39
+#define CLK_MOUT_PDP_VRA		40
+#define CLK_MOUT_IPP_BUS		41
+#define CLK_MOUT_G3AA			42
+#define CLK_MOUT_ITP			43
+#define CLK_MOUT_DNS_BUS		44
+#define CLK_MOUT_TNR_BUS		45
+#define CLK_MOUT_MCSC_ITSC		46
+#define CLK_MOUT_MCSC_MCSC		47
+#define CLK_MOUT_GDC_SCSC		48
+#define CLK_MOUT_GDC_GDC0		49
+#define CLK_MOUT_GDC_GDC1		50
+#define CLK_MOUT_MFC_MFC		51
+#define CLK_MOUT_MIF_SWITCH		52
+#define CLK_MOUT_MIF_BUS		53
+#define CLK_MOUT_MISC_BUS		54
+#define CLK_MOUT_MISC_SSS		55
+#define CLK_MOUT_PERIC0_IP		56
+#define CLK_MOUT_PERIC0_BUS		57
+#define CLK_MOUT_PERIC1_IP		58
+#define CLK_MOUT_PERIC1_BUS		59
+#define CLK_MOUT_TPU_TPU		60
+#define CLK_MOUT_TPU_TPUCTL		61
+#define CLK_MOUT_TPU_BUS		62
+#define CLK_MOUT_TPU_UART		63
+#define CLK_MOUT_TPU_HPM		64
+#define CLK_MOUT_BO_BUS			65
+#define CLK_MOUT_G3D_BUSD		66
+
+/* CMU_TOP Dividers*/
+#define CLK_DOUT_SHARED0_DIV3		67
+#define CLK_DOUT_SHARED0_DIV2		68
+#define CLK_DOUT_SHARED0_DIV4		69
+#define CLK_DOUT_SHARED0_DIV5		70
+#define CLK_DOUT_SHARED1_DIV3		71
+#define CLK_DOUT_SHARED1_DIV2		72
+#define CLK_DOUT_SHARED1_DIV4		73
+#define CLK_DOUT_SHARED2_DIV2		74
+#define CLK_DOUT_SHARED3_DIV2		75
+#define CLK_DOUT_BUS0_BUS		76
+#define CLK_DOUT_CMU_BOOST		77
+#define CLK_DOUT_BUS1_BUS		78
+#define CLK_DOUT_BUS2_BUS		79
+#define CLK_DOUT_CORE_BUS		80
+#define CLK_DOUT_EH_BUS			81
+#define CLK_DOUT_CPUCL2_SWITCH		82
+#define CLK_DOUT_CPUCL1_SWITCH		83
+#define CLK_DOUT_CPUCL0_SWITCH		84
+#define CLK_DOUT_CPUCL0_DBG		85
+#define CLK_DOUT_CMU_HPM		86
+#define CLK_DOUT_G3D_SWITCH		87
+#define CLK_DOUT_G3D_GLB		88
+#define CLK_DOUT_DPU_BUS		89
+#define CLK_DOUT_DISP_BUS		90
+#define CLK_DOUT_G2D_G2D		91
+#define CLK_DOUT_G2D_MSCL		92
+#define CLK_DOUT_HSI0_USB31DRD		93
+#define CLK_DOUT_HSI0_BUS		94
+#define CLK_DOUT_HSI0_DPGTC		95
+#define CLK_DOUT_HSI0_USBDPDGB		96
+#define CLK_DOUT_HSI1_BUS		97
+#define CLK_DOUT_HSI1_PCIE		98
+#define CLK_DOUT_HSI2_BUS		100
+#define CLK_DOUT_HSI2_PCIE		101
+#define CLK_DOUT_HSI2_UFS_EMBD		102
+#define CLK_DOUT_HSI2_MMC_CARD		103
+#define CLK_DOUT_CSIS			104
+#define CLK_DOUT_PDP_BUS		105
+#define CLK_DOUT_PDP_VRA		106
+#define CLK_DOUT_IPP_BUS		107
+#define CLK_DOUT_G3AA			108
+#define CLK_DOUT_ITP			109
+#define CLK_DOUT_DNS_BUS		110
+#define CLK_DOUT_TNR_BUS		111
+#define CLK_DOUT_MCSC_ITSC		112
+#define CLK_DOUT_MCSC_MCSC		113
+#define CLK_DOUT_GDC_SCSC		114
+#define CLK_DOUT_GDC_GDC0		115
+#define CLK_DOUT_GDC_GDC1		116
+#define CLK_DOUT_MFC_MFC		117
+#define CLK_DOUT_MIF_BUS		118
+#define CLK_DOUT_MISC_BUS		119
+#define CLK_DOUT_MISC_SSS		120
+#define CLK_DOUT_PERIC0_BUS		121
+#define CLK_DOUT_PERIC0_IP		122
+#define CLK_DOUT_PERIC1_BUS		123
+#define CLK_DOUT_PERIC1_IP		124
+#define CLK_DOUT_TPU_TPU		125
+#define CLK_DOUT_TPU_TPUCTL		126
+#define CLK_DOUT_TPU_BUS		127
+#define CLK_DOUT_TPU_UART		128
+#define CLK_DOUT_TPU_HPM		129
+#define CLK_DOUT_BO_BUS			130
+
+/* CMU_TOP Gates*/
+#define CLK_GOUT_BUS0_BUS		131
+#define CLK_GOUT_BUS1_BUS		132
+#define CLK_GOUT_BUS2_BUS		133
+#define CLK_GOUT_CORE_BUS		134
+#define CLK_GOUT_EH_BUS			135
+#define CLK_GOUT_CPUCL2_SWITCH		136
+#define CLK_GOUT_CPUCL1_SWITCH		137
+#define CLK_GOUT_CPUCL0_SWITCH		138
+#define CLK_GOUT_CPUCL0_DBG		139
+#define CLK_GOUT_CMU_HPM		140
+#define CLK_GOUT_G3D_SWITCH		141
+#define CLK_GOUT_G3D_GLB		142
+#define CLK_GOUT_DPU_BUS		143
+#define CLK_GOUT_DISP_BUS		144
+#define CLK_GOUT_G2D_G2D		145
+#define CLK_GOUT_G2D_MSCL		146
+#define CLK_GOUT_HSI0_USB31DRD		147
+#define CLK_GOUT_HSI0_BUS		148
+#define CLK_GOUT_HSI0_DPGTC		149
+#define CLK_GOUT_HSI0_USBDPDGB		150
+#define CLK_GOUT_HSI1_BUS		151
+#define CLK_GOUT_HSI1_PCIE		152
+#define CLK_GOUT_HSI2_BUS		153
+#define CLK_GOUT_HSI2_PCIE		154
+#define CLK_GOUT_HSI2_UFS_EMBD		155
+#define CLK_GOUT_HSI2_MMC_CARD		156
+#define CLK_GOUT_CSIS			157
+#define CLK_GOUT_PDP_BUS		158
+#define CLK_GOUT_PDP_VRA		159
+#define CLK_GOUT_IPP_BUS		160
+#define CLK_GOUT_G3AA			161
+#define CLK_GOUT_ITP			162
+#define CLK_GOUT_DNS_BUS		163
+#define CLK_GOUT_TNR_BUS		164
+#define CLK_GOUT_MCSC_ITSC		165
+#define CLK_GOUT_MCSC_MCSC		166
+#define CLK_GOUT_GDC_SCSC		167
+#define CLK_GOUT_GDC_GDC0		168
+#define CLK_GOUT_GDC_GDC1		169
+#define CLK_GOUT_MFC_MFC		170
+#define CLK_GOUT_MIF_SWITCH		171
+#define CLK_GOUT_MIF_BUS		172
+#define CLK_GOUT_MISC_BUS		173
+#define CLK_GOUT_MISC_SSS		174
+#define CLK_GOUT_PERIC0_BUS		175
+#define CLK_GOUT_PERIC0_IP		176
+#define CLK_GOUT_PERIC1_BUS		177
+#define CLK_GOUT_PERIC1_IP		178
+#define CLK_GOUT_TPU_TPU		179
+#define CLK_GOUT_TPU_TPUCTL		180
+#define CLK_GOUT_TPU_BUS		181
+#define CLK_GOUT_TPU_UART		182
+#define CLK_GOUT_TPU_HPM		183
+#define CLK_GOUT_BO_BUS			184
+#define CLK_GOUT_CMU_BOOST		185
+
+/* CMU_APM */
+
+#define CLK_MOUT_APM_FUNC					1
+#define CLK_MOUT_APM_FUNCSRC					2
+#define CLK_DOUT_APM_BOOST					3
+#define CLK_DOUT_APM_USI0_UART					4
+#define CLK_DOUT_APM_USI0_USI					5
+#define CLK_DOUT_APM_USI1_UART					6
+#define CLK_GOUT_APM_FUNC					7
+#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK	8
+#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK	9
+#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK		10
+#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK		11
+#define CLK_APM_PLL_DIV2_APM					12
+#define CLK_APM_PLL_DIV4_APM					13
+#define CLK_APM_PLL_DIV16_APM					14
+
+/* CMU_MISC */
+
+#define CLK_MOUT_MISC_BUS_USER					1
+#define CLK_MOUT_MISC_SSS_USER					2
+#define CLK_DOUT_MISC_BUSP					3
+#define CLK_DOUT_MISC_GIC					4
+#define CLK_GOUT_MISC_PCLK					5
+#define CLK_GOUT_MISC_SYSREG_PCLK				6
+#define CLK_GOUT_MISC_WDT_CLUSTER0				7
+#define CLK_GOUT_MISC_WDT_CLUSTER1				8
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 03/20] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101

[Peter Griffin]

GS101 has three different SYSREG controllers, add dedicated
compatibles for them to the documentation.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 .../bindings/soc/samsung/samsung,exynos-sysreg.yaml         | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index 163e912e9cad..dbd12a97faad 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -30,6 +30,12 @@ properties:
               - samsung,exynos5433-fsys-sysreg
           - const: samsung,exynos5433-sysreg
           - const: syscon
+      - items:
+          - enum:
+              - google,gs101-peric0-sysreg
+              - google,gs101-peric1-sysreg
+              - google,gs101-apm-sysreg
+          - const: syscon
       - items:
           - enum:
               - samsung,exynos5433-sysreg
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 04/20] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings

[Peter Griffin]

Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
dt-schema documentation.

gs101 SoC has two CPU clusters and each cluster has its own dedicated
watchdog timer (similar to exynos850 and exynosautov9 SoCs).

These WDT instances are controlled using different bits in PMU
registers.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 .../devicetree/bindings/watchdog/samsung-wdt.yaml      | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
index 8fb6656ba0c2..67c8767f0499 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
@@ -17,6 +17,8 @@ description: |+
 properties:
   compatible:
     enum:
+      - google,gs101-wdt                      # for Google gs101
+      - google,gs201-wdt                      # for Google gs201
       - samsung,s3c2410-wdt                   # for S3C2410
       - samsung,s3c6410-wdt                   # for S3C6410, S5PV210 and Exynos4
       - samsung,exynos5250-wdt                # for Exynos5250
@@ -42,13 +44,13 @@ properties:
   samsung,cluster-index:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
-      Index of CPU cluster on which watchdog is running (in case of Exynos850)
+      Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01)
 
   samsung,syscon-phandle:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
       Phandle to the PMU system controller node (in case of Exynos5250,
-      Exynos5420, Exynos7 and Exynos850).
+      Exynos5420, Exynos7, Exynos850 and gsx01).
 
 required:
   - compatible
@@ -69,6 +71,8 @@ allOf:
               - samsung,exynos7-wdt
               - samsung,exynos850-wdt
               - samsung,exynosautov9-wdt
+              - google,gs101-wdt
+              - google,gs201-wdt
     then:
       required:
         - samsung,syscon-phandle
@@ -79,6 +83,8 @@ allOf:
             enum:
               - samsung,exynos850-wdt
               - samsung,exynosautov9-wdt
+              - google,gs101-wdt
+              - google,gs201-wdt
     then:
       properties:
         clocks:
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 05/20] dt-bindings: arm: google: Add bindings for Google ARM platforms

[Peter Griffin]

This introduces bindings and dt-schema for the Google tensor SoCs.
Currently just gs101 and pixel 6 are supported.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/arm/google.yaml       | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/google.yaml

diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml
new file mode 100644
index 000000000000..167945e4d5ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/google.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/google.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor platforms
+
+maintainers:
+  - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+  ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
+  devices.
+
+  Currently upstream this is devices using "gs101" SoC which is found in Pixel
+  6, Pixel 6 Pro and Pixel 6a.
+
+  Google have a few different names for the SoC.
+  - Marketing name ("Tensor")
+  - Codename ("Whitechapel")
+  - SoC ID ("gs101")
+  - Die ID ("S5P9845");
+
+  Likewise there are a couple of names for the actual device
+  - Marketing name ("Pixel 6")
+  - Codename ("Oriole")
+
+  Devicetrees should use the lowercased SoC ID and lowercased board codename.
+  e.g. gs101 and gs101-oriole
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+
+      - description: Google Pixel 6 / Oriole
+        items:
+          - enum:
+              - google,gs101-oriole
+          - const: google,gs101
+
+additionalProperties: true
+
+...
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 06/20] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible

[Peter Griffin]

Add the "google,gs101-pinctrl" compatible to the dt-schema bindings
documentation.

Add maxItems of 50 for the interrupts property as gs101 can have
multiple irqs.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 .../bindings/pinctrl/samsung,pinctrl.yaml     | 22 ++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index 26614621774a..6dc648490668 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -35,6 +35,7 @@ properties:
 
   compatible:
     enum:
+      - google,gs101-pinctrl
       - samsung,s3c2412-pinctrl
       - samsung,s3c2416-pinctrl
       - samsung,s3c2440-pinctrl
@@ -58,7 +59,8 @@ properties:
   interrupts:
     description:
       Required for GPIO banks supporting external GPIO interrupts.
-    maxItems: 1
+    minItems: 1
+    maxItems: 50
 
   power-domains:
     maxItems: 1
@@ -134,6 +136,24 @@ allOf:
           minItems: 1
           maxItems: 1
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-pinctrl
+    then:
+      properties:
+        interrupts:
+          description:
+            Required for external wakeup interrupts. List all external
+            wakeup interrupts supported by this bank.
+          minItems: 1
+          maxItems: 50
+    else:
+      properties:
+        interrupts:
+          maxItems: 1
+
 additionalProperties: false
 
 examples:
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 07/20] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible

[Peter Griffin]

gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9
where more than one pin controller can do external wake-up interrupt.
So add a dedicated compatible for it.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml      | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
index 1de91a51234d..7cddce761c46 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
@@ -29,6 +29,7 @@ description: |
 properties:
   compatible:
     enum:
+      - google,gs101-wakeup-eint
       - samsung,s3c2410-wakeup-eint
       - samsung,s3c2412-wakeup-eint
       - samsung,s3c64xx-wakeup-eint
@@ -99,6 +100,7 @@ allOf:
             enum:
               - samsung,exynos850-wakeup-eint
               - samsung,exynosautov9-wakeup-eint
+              - google,gs101-wakeup-eint
     then:
       properties:
         interrupts: false
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 08/20] dt-bindings: serial: samsung: Add google-gs101-uart compatible

[Peter Griffin]

Add dedicated google-gs101-uart compatible to the dt-schema for
representing uart of the Google Tensor gs101 SoC.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
index 8bd88d5cbb11..6e807b1b4d8c 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
@@ -24,6 +24,7 @@ properties:
       - enum:
           - apple,s5l-uart
           - axis,artpec8-uart
+          - google,gs101-uart
           - samsung,s3c2410-uart
           - samsung,s3c2412-uart
           - samsung,s3c2440-uart
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 09/20] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}

[Peter Griffin]

These plls are found in the Tensor gs101 SoC found in the Pixel 6.

pll0516x: Integer PLL with high frequency
pll0517x: Integer PLL with middle frequency
pll0518x: Integer PLL with low frequency

PLL0516x
FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)

PLL0517x and PLL0518x
FOUT = (MDIV * FIN)/PDIV*2^SDIV)

The PLLs are similar enough to pll_0822x that the same code can handle
both. The main difference is the change in the fout formula for the
high frequency 0516 pll.

Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.

When defining the PLL the "con" parameter should be set to CON3
register, like this

PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
    PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
    NULL),

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 drivers/clk/samsung/clk-pll.c | 9 ++++++++-
 drivers/clk/samsung/clk-pll.h | 3 +++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 74934c6182ce..4ef9fea2a425 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
 	pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
 	sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
 
-	fvco *= mdiv;
+	if (pll->type == pll_0516x)
+		fvco = fvco * 2 * mdiv;
+	else
+		fvco *= mdiv;
+
 	do_div(fvco, (pdiv << sdiv));
 
 	return (unsigned long)fvco;
@@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	case pll_1417x:
 	case pll_0818x:
 	case pll_0822x:
+	case pll_0516x:
+	case pll_0517x:
+	case pll_0518x:
 		pll->enable_offs = PLL0822X_ENABLE_SHIFT;
 		pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
 		if (!pll->rate_table)
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 0725d485c6ee..ffd3d52c0dec 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -38,6 +38,9 @@ enum samsung_pll_type {
 	pll_0822x,
 	pll_0831x,
 	pll_142xx,
+	pll_0516x,
+	pll_0517x,
+	pll_0518x,
 };
 
 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Peter Griffin]

CMU_TOP is the top level clock management unit which contains PLLs, muxes
and gates that feed the other clock management units.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 drivers/clk/samsung/Kconfig     |    9 +
 drivers/clk/samsung/Makefile    |    2 +
 drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
 3 files changed, 1562 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-gs101.c

diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 76a494e95027..14362ec9c543 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
 	select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
 	select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
 	select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
+	select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
 	select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
 
 config S3C64XX_COMMON_CLK
@@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
 	  status of the certains clocks from SoC, but it could also be tied to
 	  other devices as an input clock.
 
+config GOOGLE_GS101_COMMON_CLK
+	bool "Google gs101 clock controller support" if COMPILE_TEST
+	depends on COMMON_CLK_SAMSUNG
+	depends on EXYNOS_ARM64_COMMON_CLK
+	help
+	  Support for the clock controller present on the Google gs101 SoC.
+	  Choose Y here only if you build for this SoC.
+
 config TESLA_FSD_COMMON_CLK
 	bool "Tesla FSD clock controller support" if COMPILE_TEST
 	depends on COMMON_CLK_SAMSUNG
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index ebbeacabe88f..49146937d957 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7885.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o
+obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK)	+= clk-gs101.o
 obj-$(CONFIG_S3C64XX_COMMON_CLK)	+= clk-s3c64xx.o
 obj-$(CONFIG_S5PV210_COMMON_CLK)	+= clk-s5pv210.o clk-s5pv210-audss.o
 obj-$(CONFIG_TESLA_FSD_COMMON_CLK)	+= clk-fsd.o
+
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
new file mode 100644
index 000000000000..e2c62754b1eb
--- /dev/null
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -0,0 +1,1551 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Common Clock Framework support for GS101.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/google,gs101.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
+
+/* ---- CMU_TOP ------------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_TOP (0x1e080000) */
+
+#define PLL_LOCKTIME_PLL_SHARED0			0x0000
+#define PLL_LOCKTIME_PLL_SHARED1			0x0004
+#define PLL_LOCKTIME_PLL_SHARED2			0x0008
+#define PLL_LOCKTIME_PLL_SHARED3			0x000c
+#define PLL_LOCKTIME_PLL_SPARE				0x0010
+#define PLL_CON0_PLL_SHARED0				0x0100
+#define PLL_CON1_PLL_SHARED0				0x0104
+#define PLL_CON2_PLL_SHARED0				0x0108
+#define PLL_CON3_PLL_SHARED0				0x010c
+#define PLL_CON4_PLL_SHARED0				0x0110
+#define PLL_CON0_PLL_SHARED1				0x0140
+#define PLL_CON1_PLL_SHARED1				0x0144
+#define PLL_CON2_PLL_SHARED1				0x0148
+#define PLL_CON3_PLL_SHARED1				0x014c
+#define PLL_CON4_PLL_SHARED1				0x0150
+#define PLL_CON0_PLL_SHARED2				0x0180
+#define PLL_CON1_PLL_SHARED2				0x0184
+#define PLL_CON2_PLL_SHARED2				0x0188
+#define PLL_CON3_PLL_SHARED2				0x018c
+#define PLL_CON4_PLL_SHARED2				0x0190
+#define PLL_CON0_PLL_SHARED3				0x01c0
+#define PLL_CON1_PLL_SHARED3				0x01c4
+#define PLL_CON2_PLL_SHARED3				0x01c8
+#define PLL_CON3_PLL_SHARED3				0x01cc
+#define PLL_CON4_PLL_SHARED3				0x01d0
+#define PLL_CON0_PLL_SPARE				0x0200
+#define PLL_CON1_PLL_SPARE				0x0204
+#define PLL_CON2_PLL_SPARE				0x0208
+#define PLL_CON3_PLL_SPARE				0x020c
+#define PLL_CON4_PLL_SPARE				0x0210
+#define CMU_CMU_TOP_CONTROLLER_OPTION			0x0800
+#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0		0x0810
+#define CMU_HCHGEN_CLKMUX_CMU_BOOST			0x0840
+#define CMU_HCHGEN_CLKMUX_TOP_BOOST			0x0844
+#define CMU_HCHGEN_CLKMUX				0x0850
+#define POWER_FAIL_DETECT_PLL				0x0864
+#define EARLY_WAKEUP_FORCED_0_ENABLE			0x0870
+#define EARLY_WAKEUP_FORCED_1_ENABLE			0x0874
+#define EARLY_WAKEUP_APM_CTRL				0x0878
+#define EARLY_WAKEUP_CLUSTER0_CTRL			0x087c
+#define EARLY_WAKEUP_DPU_CTRL				0x0880
+#define EARLY_WAKEUP_CSIS_CTRL				0x0884
+#define EARLY_WAKEUP_APM_DEST				0x0890
+#define EARLY_WAKEUP_CLUSTER0_DEST			0x0894
+#define EARLY_WAKEUP_DPU_DEST				0x0898
+#define EARLY_WAKEUP_CSIS_DEST				0x089c
+#define EARLY_WAKEUP_SW_TRIG_APM			0x08c0
+#define EARLY_WAKEUP_SW_TRIG_APM_SET			0x08c4
+#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR			0x08c8
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0			0x08d0
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET		0x08d4
+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR		0x08d8
+#define EARLY_WAKEUP_SW_TRIG_DPU			0x08e0
+#define EARLY_WAKEUP_SW_TRIG_DPU_SET			0x08e4
+#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR			0x08e8
+#define EARLY_WAKEUP_SW_TRIG_CSIS			0x08f0
+#define EARLY_WAKEUP_SW_TRIG_CSIS_SET			0x08f4
+#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR			0x08f8
+
+#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS			0x1000
+#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS			0x1004
+#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS			0x1008
+#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS			0x100c
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0			0x1010
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1			0x1014
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2			0x1018
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3			0x101c
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4			0x1020
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5			0x1024
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6			0x1028
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7			0x102c
+#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST		0x1030
+#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1	0x1034
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS			0x1038
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG		0x103c
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH		0x1040
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH		0x1044
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH		0x1048
+#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS			0x104c
+#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS			0x1050
+#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS			0x1054
+#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS			0x1058
+#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS			0x105c
+#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D			0x1060
+#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL			0x1064
+#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA		0x1068
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD			0x106c
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB			0x1070
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH		0x1074
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0			0x1078
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1			0x107c
+#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC			0x1080
+#define CLK_CON_MUX_MUX_CLKCMU_HPM			0x1084
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS			0x1088
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC		0x108c
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD		0x1090
+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG		0x1094
+#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS			0x1098
+#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE		0x109c
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS			0x10a0
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD		0x10a4
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE		0x10a8
+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD		0x10ac
+#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS			0x10b0
+#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS			0x10b4
+#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC		0x10b8
+#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC		0x10bc
+#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC			0x10c0
+#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP			0x10c4
+#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH		0x10c8
+#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS			0x10cc
+#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS			0x10d0
+#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS			0x10d4
+#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA			0x10d8
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS		0x10dc
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP		0x10e0
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS		0x10e4
+#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP		0x10e8
+#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS			0x10ec
+#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1	0x10f0
+#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF		0x10f4
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS			0x10f8
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU			0x10fc
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL		0x1100
+#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART			0x1104
+#define CLK_CON_MUX_MUX_CMU_CMUREF			0x1108
+
+#define CLK_CON_DIV_CLKCMU_BO_BUS			0x1800
+#define CLK_CON_DIV_CLKCMU_BUS0_BUS			0x1804
+#define CLK_CON_DIV_CLKCMU_BUS1_BUS			0x1808
+#define CLK_CON_DIV_CLKCMU_BUS2_BUS			0x180c
+#define CLK_CON_DIV_CLKCMU_CIS_CLK0			0x1810
+#define CLK_CON_DIV_CLKCMU_CIS_CLK1			0x1814
+#define CLK_CON_DIV_CLKCMU_CIS_CLK2			0x1818
+#define CLK_CON_DIV_CLKCMU_CIS_CLK3			0x181c
+#define CLK_CON_DIV_CLKCMU_CIS_CLK4			0x1820
+#define CLK_CON_DIV_CLKCMU_CIS_CLK5			0x1824
+#define CLK_CON_DIV_CLKCMU_CIS_CLK6			0x1828
+#define CLK_CON_DIV_CLKCMU_CIS_CLK7			0x182c
+#define CLK_CON_DIV_CLKCMU_CORE_BUS			0x1830
+#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG			0x1834
+#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH		0x1838
+#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH		0x183c
+#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH		0x1840
+#define CLK_CON_DIV_CLKCMU_CSIS_BUS			0x1844
+#define CLK_CON_DIV_CLKCMU_DISP_BUS			0x1848
+#define CLK_CON_DIV_CLKCMU_DNS_BUS			0x184c
+#define CLK_CON_DIV_CLKCMU_DPU_BUS			0x1850
+#define CLK_CON_DIV_CLKCMU_EH_BUS			0x1854
+#define CLK_CON_DIV_CLKCMU_G2D_G2D			0x1858
+#define CLK_CON_DIV_CLKCMU_G2D_MSCL			0x185c
+#define CLK_CON_DIV_CLKCMU_G3AA_G3AA			0x1860
+#define CLK_CON_DIV_CLKCMU_G3D_BUSD			0x1864
+#define CLK_CON_DIV_CLKCMU_G3D_GLB			0x1868
+#define CLK_CON_DIV_CLKCMU_G3D_SWITCH			0x186c
+#define CLK_CON_DIV_CLKCMU_GDC_GDC0			0x1870
+#define CLK_CON_DIV_CLKCMU_GDC_GDC1			0x1874
+#define CLK_CON_DIV_CLKCMU_GDC_SCSC			0x1878
+#define CLK_CON_DIV_CLKCMU_HPM				0x187c
+#define CLK_CON_DIV_CLKCMU_HSI0_BUS			0x1880
+#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC			0x1884
+#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD		0x1888
+#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG		0x188c
+#define CLK_CON_DIV_CLKCMU_HSI1_BUS			0x1890
+#define CLK_CON_DIV_CLKCMU_HSI1_PCIE			0x1894
+#define CLK_CON_DIV_CLKCMU_HSI2_BUS			0x1898
+#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD		0x189c
+#define CLK_CON_DIV_CLKCMU_HSI2_PCIE			0x18a0
+#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD		0x18a4
+#define CLK_CON_DIV_CLKCMU_IPP_BUS			0x18a8
+#define CLK_CON_DIV_CLKCMU_ITP_BUS			0x18ac
+#define CLK_CON_DIV_CLKCMU_MCSC_ITSC			0x18b0
+#define CLK_CON_DIV_CLKCMU_MCSC_MCSC			0x18b4
+#define CLK_CON_DIV_CLKCMU_MFC_MFC			0x18b8
+#define CLK_CON_DIV_CLKCMU_MIF_BUSP			0x18bc
+#define CLK_CON_DIV_CLKCMU_MISC_BUS			0x18c0
+#define CLK_CON_DIV_CLKCMU_MISC_SSS			0x18c4
+#define CLK_CON_DIV_CLKCMU_OTP				0x18c8
+#define CLK_CON_DIV_CLKCMU_PDP_BUS			0x18cc
+#define CLK_CON_DIV_CLKCMU_PDP_VRA			0x18d0
+#define CLK_CON_DIV_CLKCMU_PERIC0_BUS			0x18d4
+#define CLK_CON_DIV_CLKCMU_PERIC0_IP			0x18d8
+#define CLK_CON_DIV_CLKCMU_PERIC1_BUS			0x18dc
+#define CLK_CON_DIV_CLKCMU_PERIC1_IP			0x18e0
+#define CLK_CON_DIV_CLKCMU_TNR_BUS			0x18e4
+#define CLK_CON_DIV_CLKCMU_TPU_BUS			0x18e8
+#define CLK_CON_DIV_CLKCMU_TPU_TPU			0x18ec
+#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL			0x18f0
+#define CLK_CON_DIV_CLKCMU_TPU_UART			0x18f4
+#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST		0x18f8
+#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF			0x18fc
+#define CLK_CON_DIV_PLL_SHARED0_DIV2			0x1900
+#define CLK_CON_DIV_PLL_SHARED0_DIV3			0x1904
+#define CLK_CON_DIV_PLL_SHARED0_DIV4			0x1908
+#define CLK_CON_DIV_PLL_SHARED0_DIV5			0x190c
+#define CLK_CON_DIV_PLL_SHARED1_DIV2			0x1910
+#define CLK_CON_DIV_PLL_SHARED1_DIV3			0x1914
+#define CLK_CON_DIV_PLL_SHARED1_DIV4			0x1918
+#define CLK_CON_DIV_PLL_SHARED2_DIV2			0x191c
+#define CLK_CON_DIV_PLL_SHARED3_DIV2			0x1920
+
+/* CLK_CON_GAT_UPDATES */
+#define CLK_CON_GAT_CLKCMU_BUS0_BOOST			0x2000
+#define CLK_CON_GAT_CLKCMU_BUS1_BOOST			0x2004
+#define CLK_CON_GAT_CLKCMU_BUS2_BOOST			0x2008
+#define CLK_CON_GAT_CLKCMU_CORE_BOOST			0x200c
+#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST			0x2010
+#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST			0x2014
+#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST			0x2018
+#define CLK_CON_GAT_CLKCMU_MIF_BOOST			0x201c
+#define CLK_CON_GAT_CLKCMU_MIF_SWITCH			0x2020
+#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS			0x2024
+#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS		0x2028
+#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS		0x202c
+#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS		0x2030
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0		0x2034
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1		0x2038
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2		0x203c
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3		0x2040
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4		0x2044
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5		0x2048
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6		0x204c
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7		0x2050
+#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST		0x2054
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS		0x2058
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS		0x205c
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH		0x2060
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH		0x2064
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH		0x2068
+#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS		0x206c
+#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS		0x2070
+#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS			0x2074
+#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS			0x2078
+#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS			0x207c
+#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D			0x2080
+#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL		0x2084
+#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA		0x2088
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD		0x208c
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB			0x2090
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH		0x2094
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0		0x2098
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1		0x209c
+#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC		0x20a0
+#define CLK_CON_GAT_GATE_CLKCMU_HPM			0x20a4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS		0x20a8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC		0x20ac
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD		0x20b0
+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG		0x20b4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS		0x20b8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE		0x20bc
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS		0x20c0
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD		0x20c4
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE		0x20c8
+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD		0x20cc
+#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS			0x20d0
+#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS			0x20d4
+#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC		0x20d8
+#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC		0x20dc
+#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC			0x20e0
+#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP		0x20e4
+#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS		0x20e8
+#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS		0x20ec
+#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS			0x20f0
+#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA			0x20f4
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS		0x20f8
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP		0x20fc
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS		0x2100
+#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP		0x2104
+#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS			0x2108
+#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF		0x210c
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS			0x2110
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU			0x2114
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL		0x2118
+#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART		0x211c
+
+#define DMYQCH_CON_CMU_TOP_CMUREF_QCH			0x3000
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0		0x3004
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1		0x3008
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2		0x300c
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3		0x3010
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4		0x3014
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5		0x3018
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6		0x301c
+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7		0x3020
+#define DMYQCH_CON_OTP_QCH				0x3024
+#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP			0x3c00
+#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP			0x3c10
+#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP			0x3c14
+#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP			0x3c18
+#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP			0x3c1c
+#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP			0x3c20
+#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP			0x3c24
+#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP			0x3c28
+#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP			0x3c2c
+#define MIFMIRROR_QUEUE_CTRL_REG			0x3e00
+#define MIFMIRROR_QUEUE_ENTRY0				0x3e10
+#define MIFMIRROR_QUEUE_ENTRY1				0x3e14
+#define MIFMIRROR_QUEUE_ENTRY2				0x3e18
+#define MIFMIRROR_QUEUE_ENTRY3				0x3e1c
+#define MIFMIRROR_QUEUE_ENTRY4				0x3e20
+#define MIFMIRROR_QUEUE_ENTRY5				0x3e24
+#define MIFMIRROR_QUEUE_ENTRY6				0x3e28
+#define MIFMIRROR_QUEUE_ENTRY7				0x3e2c
+#define MIFMIRROR_QUEUE_BUSY				0x3e30
+#define GENERALIO_ACD_CHANNEL_0				0x3f00
+#define GENERALIO_ACD_CHANNEL_1				0x3f04
+#define GENERALIO_ACD_CHANNEL_2				0x3f08
+#define GENERALIO_ACD_CHANNEL_3				0x3f0c
+#define GENERALIO_ACD_MASK				0x3f14
+
+static const unsigned long cmu_top_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_SHARED0,
+	PLL_LOCKTIME_PLL_SHARED1,
+	PLL_LOCKTIME_PLL_SHARED2,
+	PLL_LOCKTIME_PLL_SHARED3,
+	PLL_LOCKTIME_PLL_SPARE,
+	PLL_CON0_PLL_SHARED0,
+	PLL_CON1_PLL_SHARED0,
+	PLL_CON2_PLL_SHARED0,
+	PLL_CON3_PLL_SHARED0,
+	PLL_CON4_PLL_SHARED0,
+	PLL_CON0_PLL_SHARED1,
+	PLL_CON1_PLL_SHARED1,
+	PLL_CON2_PLL_SHARED1,
+	PLL_CON3_PLL_SHARED1,
+	PLL_CON4_PLL_SHARED1,
+	PLL_CON0_PLL_SHARED2,
+	PLL_CON1_PLL_SHARED2,
+	PLL_CON2_PLL_SHARED2,
+	PLL_CON3_PLL_SHARED2,
+	PLL_CON4_PLL_SHARED2,
+	PLL_CON0_PLL_SHARED3,
+	PLL_CON1_PLL_SHARED3,
+	PLL_CON2_PLL_SHARED3,
+	PLL_CON3_PLL_SHARED3,
+	PLL_CON4_PLL_SHARED3,
+	PLL_CON0_PLL_SPARE,
+	PLL_CON1_PLL_SPARE,
+	PLL_CON2_PLL_SPARE,
+	PLL_CON3_PLL_SPARE,
+	PLL_CON4_PLL_SPARE,
+	CMU_CMU_TOP_CONTROLLER_OPTION,
+	CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
+	CMU_HCHGEN_CLKMUX_CMU_BOOST,
+	CMU_HCHGEN_CLKMUX_TOP_BOOST,
+	CMU_HCHGEN_CLKMUX,
+	POWER_FAIL_DETECT_PLL,
+	EARLY_WAKEUP_FORCED_0_ENABLE,
+	EARLY_WAKEUP_FORCED_1_ENABLE,
+	EARLY_WAKEUP_APM_CTRL,
+	EARLY_WAKEUP_CLUSTER0_CTRL,
+	EARLY_WAKEUP_DPU_CTRL,
+	EARLY_WAKEUP_CSIS_CTRL,
+	EARLY_WAKEUP_APM_DEST,
+	EARLY_WAKEUP_CLUSTER0_DEST,
+	EARLY_WAKEUP_DPU_DEST,
+	EARLY_WAKEUP_CSIS_DEST,
+	EARLY_WAKEUP_SW_TRIG_APM,
+	EARLY_WAKEUP_SW_TRIG_APM_SET,
+	EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
+	EARLY_WAKEUP_SW_TRIG_CLUSTER0,
+	EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
+	EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
+	EARLY_WAKEUP_SW_TRIG_DPU,
+	EARLY_WAKEUP_SW_TRIG_DPU_SET,
+	EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
+	EARLY_WAKEUP_SW_TRIG_CSIS,
+	EARLY_WAKEUP_SW_TRIG_CSIS_SET,
+	EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
+	CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
+	CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
+	CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
+	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
+	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
+	CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
+	CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
+	CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
+	CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
+	CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
+	CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
+	CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
+	CLK_CON_MUX_MUX_CLKCMU_HPM,
+	CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
+	CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
+	CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
+	CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
+	CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
+	CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
+	CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
+	CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
+	CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
+	CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
+	CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
+	CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
+	CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
+	CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
+	CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
+	CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
+	CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
+	CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
+	CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
+	CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
+	CLK_CON_MUX_MUX_CMU_CMUREF,
+	CLK_CON_DIV_CLKCMU_BO_BUS,
+	CLK_CON_DIV_CLKCMU_BUS0_BUS,
+	CLK_CON_DIV_CLKCMU_BUS1_BUS,
+	CLK_CON_DIV_CLKCMU_BUS2_BUS,
+	CLK_CON_DIV_CLKCMU_CIS_CLK0,
+	CLK_CON_DIV_CLKCMU_CIS_CLK1,
+	CLK_CON_DIV_CLKCMU_CIS_CLK2,
+	CLK_CON_DIV_CLKCMU_CIS_CLK3,
+	CLK_CON_DIV_CLKCMU_CIS_CLK4,
+	CLK_CON_DIV_CLKCMU_CIS_CLK5,
+	CLK_CON_DIV_CLKCMU_CIS_CLK6,
+	CLK_CON_DIV_CLKCMU_CIS_CLK7,
+	CLK_CON_DIV_CLKCMU_CORE_BUS,
+	CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
+	CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
+	CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
+	CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
+	CLK_CON_DIV_CLKCMU_CSIS_BUS,
+	CLK_CON_DIV_CLKCMU_DISP_BUS,
+	CLK_CON_DIV_CLKCMU_DNS_BUS,
+	CLK_CON_DIV_CLKCMU_DPU_BUS,
+	CLK_CON_DIV_CLKCMU_EH_BUS,
+	CLK_CON_DIV_CLKCMU_G2D_G2D,
+	CLK_CON_DIV_CLKCMU_G2D_MSCL,
+	CLK_CON_DIV_CLKCMU_G3AA_G3AA,
+	CLK_CON_DIV_CLKCMU_G3D_BUSD,
+	CLK_CON_DIV_CLKCMU_G3D_GLB,
+	CLK_CON_DIV_CLKCMU_G3D_SWITCH,
+	CLK_CON_DIV_CLKCMU_GDC_GDC0,
+	CLK_CON_DIV_CLKCMU_GDC_GDC1,
+	CLK_CON_DIV_CLKCMU_GDC_SCSC,
+	CLK_CON_DIV_CLKCMU_HPM,
+	CLK_CON_DIV_CLKCMU_HSI0_BUS,
+	CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
+	CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
+	CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
+	CLK_CON_DIV_CLKCMU_HSI1_BUS,
+	CLK_CON_DIV_CLKCMU_HSI1_PCIE,
+	CLK_CON_DIV_CLKCMU_HSI2_BUS,
+	CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
+	CLK_CON_DIV_CLKCMU_HSI2_PCIE,
+	CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
+	CLK_CON_DIV_CLKCMU_IPP_BUS,
+	CLK_CON_DIV_CLKCMU_ITP_BUS,
+	CLK_CON_DIV_CLKCMU_MCSC_ITSC,
+	CLK_CON_DIV_CLKCMU_MCSC_MCSC,
+	CLK_CON_DIV_CLKCMU_MFC_MFC,
+	CLK_CON_DIV_CLKCMU_MIF_BUSP,
+	CLK_CON_DIV_CLKCMU_MISC_BUS,
+	CLK_CON_DIV_CLKCMU_MISC_SSS,
+	CLK_CON_DIV_CLKCMU_OTP,
+	CLK_CON_DIV_CLKCMU_PDP_BUS,
+	CLK_CON_DIV_CLKCMU_PDP_VRA,
+	CLK_CON_DIV_CLKCMU_PERIC0_BUS,
+	CLK_CON_DIV_CLKCMU_PERIC0_IP,
+	CLK_CON_DIV_CLKCMU_PERIC1_BUS,
+	CLK_CON_DIV_CLKCMU_PERIC1_IP,
+	CLK_CON_DIV_CLKCMU_TNR_BUS,
+	CLK_CON_DIV_CLKCMU_TPU_BUS,
+	CLK_CON_DIV_CLKCMU_TPU_TPU,
+	CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
+	CLK_CON_DIV_CLKCMU_TPU_UART,
+	CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
+	CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
+	CLK_CON_DIV_PLL_SHARED0_DIV2,
+	CLK_CON_DIV_PLL_SHARED0_DIV3,
+	CLK_CON_DIV_PLL_SHARED0_DIV4,
+	CLK_CON_DIV_PLL_SHARED0_DIV5,
+	CLK_CON_DIV_PLL_SHARED1_DIV2,
+	CLK_CON_DIV_PLL_SHARED1_DIV3,
+	CLK_CON_DIV_PLL_SHARED1_DIV4,
+	CLK_CON_DIV_PLL_SHARED2_DIV2,
+	CLK_CON_DIV_PLL_SHARED3_DIV2,
+	CLK_CON_GAT_CLKCMU_BUS0_BOOST,
+	CLK_CON_GAT_CLKCMU_BUS1_BOOST,
+	CLK_CON_GAT_CLKCMU_BUS2_BOOST,
+	CLK_CON_GAT_CLKCMU_CORE_BOOST,
+	CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
+	CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
+	CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
+	CLK_CON_GAT_CLKCMU_MIF_BOOST,
+	CLK_CON_GAT_CLKCMU_MIF_SWITCH,
+	CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
+	CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
+	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
+	CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
+	CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
+	CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
+	CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
+	CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
+	CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
+	CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
+	CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
+	CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
+	CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
+	CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
+	CLK_CON_GAT_GATE_CLKCMU_HPM,
+	CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
+	CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
+	CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
+	CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
+	CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
+	CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
+	CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
+	CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
+	CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
+	CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
+	CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
+	CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
+	CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
+	CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
+	CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
+	CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
+	CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
+	CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
+	CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
+	DMYQCH_CON_CMU_TOP_CMUREF_QCH,
+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
+	DMYQCH_CON_OTP_QCH,
+	QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
+	QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
+	QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
+	QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
+	QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
+	QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
+	QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
+	QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
+	QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
+	MIFMIRROR_QUEUE_CTRL_REG,
+	MIFMIRROR_QUEUE_ENTRY0,
+	MIFMIRROR_QUEUE_ENTRY1,
+	MIFMIRROR_QUEUE_ENTRY2,
+	MIFMIRROR_QUEUE_ENTRY3,
+	MIFMIRROR_QUEUE_ENTRY4,
+	MIFMIRROR_QUEUE_ENTRY5,
+	MIFMIRROR_QUEUE_ENTRY6,
+	MIFMIRROR_QUEUE_ENTRY7,
+	MIFMIRROR_QUEUE_BUSY,
+	GENERALIO_ACD_CHANNEL_0,
+	GENERALIO_ACD_CHANNEL_1,
+	GENERALIO_ACD_CHANNEL_2,
+	GENERALIO_ACD_CHANNEL_3,
+	GENERALIO_ACD_MASK,
+};
+
+static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
+	/* CMU_TOP_PURECLKCOMP */
+	PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
+	    NULL),
+	PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
+	    NULL),
+	PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
+	    NULL),
+	PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
+	    NULL),
+	PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
+	    NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_TOP */
+PNAME(mout_shared0_pll_p)	= { "oscclk", "fout_shared0_pll" };
+PNAME(mout_shared1_pll_p)	= { "oscclk", "fout_shared1_pll" };
+PNAME(mout_shared2_pll_p)	= { "oscclk", "fout_shared2_pll" };
+PNAME(mout_shared3_pll_p)	= { "oscclk", "fout_shared3_pll" };
+PNAME(mout_spare_pll_p)		= { "oscclk", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */
+PNAME(mout_cmu_bus0_bus_p)	= { "dout_shared0_div4", "dout_shared1_div4",
+				    "dout_shared2_div2", "dout_shared3_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_cmu_boost_p)	= { "dout_shared0_div4", "dout_shared1_div4",
+				    "dout_shared2_div2", "dout_shared3_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */
+PNAME(mout_cmu_bus1_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */
+PNAME(mout_cmu_bus2_bus_p)	= { "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div3", "dout_shared1_div3",
+				    "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
+PNAME(mout_cmu_core_bus_p)	= { "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div3", "dout_shared1_div3",
+				    "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */
+PNAME(mout_cmu_eh_bus_p)	= { "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div3", "dout_shared1_div3",
+				    "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */
+PNAME(mout_cmu_cpucl2_switch_p)	= { "fout_shared1_pll", "dout_shared0_div2",
+				    "dout_shared1_div2", "fout_shared2_pll",
+				    "fout_shared3_pll", "dout_shared0_div3",
+				    "dout_shared1_div3", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
+PNAME(mout_cmu_cpucl1_switch_p)	= { "fout_shared1_pll", "dout_shared0_div2",
+				    "dout_shared1_div2", "fout_shared2_pll",
+				    "fout_shared3_pll", "dout_shared0_div3",
+				    "dout_shared1_div3", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
+PNAME(mout_cmu_cpucl0_switch_p)	= { "fout_shared1_pll", "dout_shared0_div2",
+				    "dout_shared1_div2", "fout_shared2_pll",
+				    "fout_shared3_pll", "dout_shared0_div3",
+				    "dout_shared1_div3", "fout_spare_pll" };
+
+PNAME(mout_cmu_cpucl0_dbg_p)	= { "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div4", "dout_shared1_div4",
+				    "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hpm_p)		= { "oscclk", "dout_shared1_div3",
+				    "dout_shared0_div4", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
+PNAME(mout_cmu_g3d_switch_p)	= { "fout_shared2_pll", "dout_shared0_div3",
+				    "fout_shared3_pll", "dout_shared1_div3",
+				    "dout_shared0_div4", "dout_shared1_div4",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_g3d_busd_p)	= { "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div3", "dout_shared1_div3",
+				    "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_g3d_glb_p)	= { "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div3", "dout_shared1_div3",
+				    "dout_shared0_div4", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
+PNAME(mout_cmu_dpu_p)		= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */
+PNAME(mout_cmu_disp_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
+PNAME(mout_cmu_g2d_g2d_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_g2d_mscl_p)	= { "dout_shared0_div4", "dout_shared1_div4",
+				    "dout_shared2_div2", "dout_shared3_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */
+PNAME(mout_cmu_hsi0_usb31drd_p)	= { "oscclk", "dout_shared2_div2" };
+
+PNAME(mout_cmu_hsi0_bus_p)	= { "dout_shared0_div4", "dout_shared1_div4",
+				    "dout_shared2_div2", "dout_shared3_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi0_dpgtc_p)	= { "oscclk", "dout_shared0_div4",
+				    "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi0_usbdpdbg_p)	= { "oscclk", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */
+PNAME(mout_cmu_hsi1_bus_p)	= { "dout_shared0_div4", "dout_shared1_div4",
+				    "dout_shared2_div2", "dout_shared3_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi1_pcie_p)	= { "oscclk", "dout_shared2_div2" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */
+PNAME(mout_cmu_hsi2_bus_p)	= { "dout_shared0_div4", "dout_shared1_div4",
+				    "dout_shared2_div2", "dout_shared3_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi2_pcie0_p)	= { "oscclk", "dout_shared2_div2" };
+
+PNAME(mout_cmu_hsi2_ufs_embd_p)	= { "oscclk", "dout_shared0_div4",
+				    "dout_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_cmu_hsi2_mmc_card_p)	= { "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div4", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
+PNAME(mout_cmu_csis_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
+PNAME(mout_cmu_pdp_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_pdp_vra_p)	= { "fout_shared2_pll", "dout_shared0_div3",
+				    "fout_shared3_pll", "dout_shared1_div3",
+				    "dout_shared0_div4", "dout_shared1_div4",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
+PNAME(mout_cmu_ipp_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
+PNAME(mout_cmu_g3aa_p)		= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
+PNAME(mout_cmu_itp_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
+PNAME(mout_cmu_dns_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
+PNAME(mout_cmu_tnr_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
+PNAME(mout_cmu_mcsc_itsc_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_mcsc_mcsc_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
+PNAME(mout_cmu_gdc_scsc_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_gdc_gdc0_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+PNAME(mout_cmu_gdc_gdc1_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
+PNAME(mout_cmu_mfc_mfc_p)	= { "dout_shared0_div3", "fout_shared3_pll",
+				    "dout_shared1_div3", "dout_shared0_div4",
+				    "dout_shared1_div4", "dout_shared2_div2",
+				    "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
+
+PNAME(mout_cmu_mif_switch_p)	= { "fout_shared0_pll", "fout_shared1_pll",
+				    "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "dout_shared0_div3",
+				    "fout_shared3_pll", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
+PNAME(mout_cmu_mif_busp_p)	= { "dout_shared0_div4", "dout_shared1_div4",
+				    "dout_shared0_div5", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
+PNAME(mout_cmu_misc_bus_p)	= { "dout_shared0_div4", "dout_shared2_div2",
+				    "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_misc_sss_p)	= { "dout_shared0_div4", "dout_shared2_div2",
+				    "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
+PNAME(mout_cmu_peric0_bus_p)	= { "dout_shared0_div4", "dout_shared2_div2",
+				    "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_peric0_ip_p)	= { "dout_shared0_div4", "dout_shared2_div2",
+				    "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
+PNAME(mout_cmu_peric1_bus_p)	= { "dout_shared0_div4", "dout_shared2_div2",
+				    "dout_shared3_div2", "fout_spare_pll" };
+PNAME(mout_cmu_peric1_ip_p)	= { "dout_shared0_div4", "dout_shared2_div2",
+				    "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
+PNAME(mout_cmu_tpu_tpu_p)	= { "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div3", "dout_shared1_div3",
+				    "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_tpuctl_p)	= { "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div3", "dout_shared1_div3",
+				    "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_bus_p)	= { "dout_shared0_div2", "dout_shared1_div2",
+				    "fout_shared2_pll", "fout_shared3_pll",
+				    "dout_shared0_div3", "dout_shared1_div3",
+				    "dout_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_cmu_tpu_uart_p)	= { "dout_shared0_div4", "dout_shared2_div2",
+				    "dout_shared3_div2", "fout_spare_pll" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
+PNAME(mout_cmu_bo_bus_p)	= { "fout_shared2_pll", "dout_shared0_div3",
+				    "fout_shared3_pll", "dout_shared1_div3",
+				    "dout_shared0_div4", "dout_shared1_div4",
+				    "fout_spare_pll" };
+
+/* gs101 */
+static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
+	/* CMU_TOP_PURECLKCOMP */
+	MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
+	    PLL_CON0_PLL_SHARED0, 4, 1),
+	MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
+	    PLL_CON0_PLL_SHARED1, 4, 1),
+	MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
+	    PLL_CON0_PLL_SHARED2, 4, 1),
+	MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
+	    PLL_CON0_PLL_SHARED3, 4, 1),
+	MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
+	    PLL_CON0_PLL_SPARE, 4, 1),
+
+	/* BUS0 */
+	MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
+	MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
+
+	/* BUS1 */
+	MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
+
+	/* BUS2 */
+	MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
+
+	/* CORE */
+	MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+
+	/* EH */
+	MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+
+	/* CPUCL{0,1,2,} */
+	MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
+
+	MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
+
+	MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
+
+	MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
+	    CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
+
+	MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
+
+	/* G3D */
+	MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
+
+	MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2),
+
+	MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2),
+	/* DPU */
+	MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
+	    CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2),
+
+	/* DISP */
+	MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2),
+
+	/* G2D */
+	MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
+
+	MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
+
+	/* HSI0 */
+	MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2),
+
+	MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2),
+
+	MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
+
+	MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2),
+
+	/* HSI1 */
+	MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2),
+
+	MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2),
+	/* HSI2 */
+	MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
+
+	MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
+
+	MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2),
+
+	MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2),
+
+	/* CSIS */
+	MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
+
+	/* PDP */
+	MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
+
+	/* PDP */
+	MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
+
+	/* IPP */
+	MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
+
+	/* G3AA */
+	MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
+
+	/* ITP */
+	MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
+
+	/* DNS */
+	MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
+
+	/* TNR */
+	MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
+
+	/* MCSC*/
+	MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
+
+	MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
+
+	/* GDC */
+	MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
+
+	MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
+	    CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
+
+	MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
+	    CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
+
+	/* MFC */
+	MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
+
+	/* DDRPHY0/1/2/3 */
+	MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
+
+	/* MIF0/1/2/3 */
+	MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
+
+	/* MISC */
+	MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
+	MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
+
+	/* PERI0 */
+	MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
+	MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
+	/* PERI1 */
+	MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
+	MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
+
+	/* TPU */
+	MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
+	    CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
+
+	MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
+	    CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
+
+	MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
+
+	MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
+	    CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
+
+	/* BO */
+	MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
+};
+
+static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
+	/* CMU_TOP_PURECLKCOMP */
+	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
+	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+	DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
+	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
+	    CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
+	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
+	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+
+	DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
+	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
+	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
+	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+
+	DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
+	    CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
+
+	DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
+	    CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
+
+	/* BUS0 */
+	DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
+	    CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
+	    CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
+
+	/* BUS1 */
+	DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
+	    CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
+
+	/* BUS2 */
+	DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
+	    CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
+
+	/* CORE */
+	DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
+	    CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
+
+	/* EH */
+	DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
+	    CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
+
+	/* CPUCL{0,1,2,} */
+	DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch",
+	    CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
+
+	DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
+	    CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
+
+	DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch",
+	    CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
+
+	DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
+	    CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
+
+	DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
+	    CLK_CON_DIV_CLKCMU_HPM, 0, 2),
+
+	/* G3D */
+	DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
+	    CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
+
+	DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
+	    CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
+
+	DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
+	    CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
+
+	/* DPU */
+	DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
+	    CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
+
+	/* DISP */
+	DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
+	    CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
+
+	/* G2D */
+	DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
+	    CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
+
+	DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
+	    CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
+
+	/* HSI0 */
+	DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd",
+	    CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
+
+	DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
+	    CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
+
+	DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
+	    CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
+
+	/* TODO register exists but all lower bits are reserved */
+	DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg",
+	    CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
+
+	/* HSI1 */
+	DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
+	    CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
+
+	DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
+	    CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
+	/* HSI2 */
+	DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
+	    CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
+
+	DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
+	    CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
+
+	DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd",
+	    CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
+
+	DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card",
+	    CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
+
+	/* CSIS */
+	DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
+	    CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
+
+	/* PDP */
+	DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
+	    CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
+
+	DIV(CLK_DOUT_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",
+	    CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
+
+	/* IPP */
+	DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
+	    CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
+
+	/* G3AA */
+	DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa",
+	    CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
+
+	/* ITP */
+	DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
+	    CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
+
+	/* DNS */
+	DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
+	    CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
+
+	/* TNR */
+	DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
+	    CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
+
+	/* MCSC*/
+	DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
+	    CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
+
+	DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
+	    CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
+
+	/* GDC */
+	DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
+	    CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
+
+	DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
+	    CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
+
+	DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
+	    CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
+
+	/* MFC */
+	DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
+	    CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
+
+	/* MIF0/1/2/3 */
+	DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
+	    CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
+
+	/* MISC */
+	DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
+	    CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
+	DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
+	    CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
+
+	/* PERI0 */
+	DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
+	    CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
+	DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
+	    CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
+
+	/* PERI1 */
+	DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
+	    CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
+	DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
+	    CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
+
+	/* TPU */
+	DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
+	    CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
+
+	DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
+	    CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
+
+	DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
+	    CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
+
+	DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
+	    CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
+
+	/* BO */
+	DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
+	    CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
+
+};
+
+static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
+	/* BUS0 */
+	GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
+
+	/* BUS1 */
+	GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
+
+	/* BUS2 */
+	GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
+
+	/* CORE */
+	GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
+
+	/* EH */
+	GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
+
+	/* CPUCL{0,1,2,} */
+	GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch",
+	     CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0),
+
+	GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
+	     CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
+
+	GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
+	     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
+
+	GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
+	     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
+
+	GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
+	     CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
+
+	/* G3D */
+	GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
+	     CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
+
+	GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
+	     CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
+
+	GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
+	     CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
+	/* DPU */
+	GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
+	/* DISP */
+	GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
+
+	/* G2D */
+	GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
+	     CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
+
+	GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
+	     CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
+	/* HSI0 */
+	GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0),
+
+	GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
+
+	GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
+
+	GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0),
+	/* HSI1 */
+	GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
+
+	GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
+	/* HSI2 */
+	GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
+
+	GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0),
+	GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card",
+	     CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0),
+	/* CSIS */
+	GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
+	/* PDP */
+	GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
+
+	GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
+	     CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
+
+	/* IPP */
+	GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
+	/* G3AA */
+	GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
+	     CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
+
+	/* ITP */
+	GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
+
+	/* DNS */
+	GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
+
+	/* TNR */
+	GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
+
+	/* MCSC*/
+	GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
+	     CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
+
+	GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
+	     CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
+
+	/* GDC */
+	GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
+	     CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
+
+	GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
+	     CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
+
+	GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
+	     CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
+
+	/* MFC */
+	GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
+	     CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
+
+	/* DDRPHY0/1/2/3 */
+	GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
+	     CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
+
+	/* MIF0/1/2/3 */
+	GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
+	     CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
+
+	GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost",
+	     CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
+
+	/* MISC */
+	GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
+	     CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
+
+	/* PERI0 */
+	GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
+	     CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
+
+	/* PERI1 */
+	GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
+	     CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
+
+	/* TPU */
+	GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
+	     CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
+	GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
+	     CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
+	GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
+	     CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
+
+	/* BO */
+	GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
+
+};
+
+static const struct samsung_cmu_info top_cmu_info __initconst = {
+	.pll_clks		= cmu_top_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(cmu_top_pll_clks),
+	.mux_clks		= cmu_top_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_top_mux_clks),
+	.div_clks		= cmu_top_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_top_div_clks),
+	.gate_clks		= cmu_top_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(cmu_top_gate_clks),
+	.nr_clk_ids		= TOP_NR_CLK,
+	.clk_regs		= cmu_top_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_top_clk_regs),
+};
+
+static void __init gs101_cmu_top_init(struct device_node *np)
+{
+	exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
+}
+
+/* Register CMU_TOP early, as it's a dependency for other early domains */
+CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
+	       gs101_cmu_top_init);
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 11/20] clk: samsung: clk-gs101: add CMU_APM support

[Peter Griffin]

This patch adds all the registers for the APM clock controller unit.

We register all the muxes and dividers, but only a few of the
gates currently for PMU and GPIO.

One clock is marked CLK_IS_CRITICAL because the system
hangs if this clock is disabled.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 drivers/clk/samsung/clk-gs101.c | 301 ++++++++++++++++++++++++++++++++
 1 file changed, 301 insertions(+)

diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index e2c62754b1eb..525f95e60665 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -19,6 +19,7 @@
 
 /* NOTE: Must be equal to the last clock ID increased by one */
 #define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
+#define APM_NR_CLK                     (CLK_APM_PLL_DIV16_APM + 1)
 
 /* ---- CMU_TOP ------------------------------------------------------------- */
 
@@ -1549,3 +1550,303 @@ static void __init gs101_cmu_top_init(struct device_node *np)
 /* Register CMU_TOP early, as it's a dependency for other early domains */
 CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
 	       gs101_cmu_top_init);
+
+/* ---- CMU_APM ------------------------------------------------------------- */
+/* Register Offset definitions for CMU_APM (0x17400000) */
+#define APM_CMU_APM_CONTROLLER_OPTION							0x0800
+#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0						0x0810
+#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC							0x1000
+#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC						0x1004
+#define CLK_CON_DIV_DIV_CLK_APM_BOOST							0x1800
+#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART						0x1804
+#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI						0x1808
+#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART						0x180c
+#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK				0x2000
+#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1						0x2004
+#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1						0x2008
+#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1						0x200c
+#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC						0x2010
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK			0x2014
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK		0x2018
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK			0x201c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK				0x2020
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK				0x2024
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK			0x2028
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK			0x202c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK			0x2030
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK			0x2034
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK			0x2038
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK			0x203c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK				0x2040
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK				0x2044
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK			0x2048
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK				0x204c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK				0x2050
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK			0x2054
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK			0x2058
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK			0x205c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK			0x2060
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK			0x2064
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK		0x2068
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK			0x206c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK			0x2070
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK			0x2074
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK			0x207c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK			0x2080
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK			0x2084
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK			0x2088
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK			0x208c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK			0x2090
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK			0x2094
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK			0x2098
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK		0x209c
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK		0x20a0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK		0x20a4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK				0x20a8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK			0x20ac
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK				0x20b0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK				0x20b4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK			0x20b8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK			0x20bc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK	0x20c0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2			0x20c4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK				0x20cc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK				0x20d0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK				0x20d4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK			0x20d8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK			0x20dc
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK				0x20e0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK				0x20e4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK			0x20e8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK			0x20ec
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK				0x20f0
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK				0x20f4
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK				0x20f8
+#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK				0x20fc
+#define PCH_CON_LHM_AXI_G_SWD_PCH			0x3000
+#define PCH_CON_LHM_AXI_P_AOCAPM_PCH			0x3004
+#define PCH_CON_LHM_AXI_P_APM_PCH			0x3008
+#define PCH_CON_LHS_AXI_D_APM_PCH			0x300c
+#define PCH_CON_LHS_AXI_G_DBGCORE_PCH			0x3010
+#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH			0x3014
+#define QCH_CON_APBIF_GPIO_ALIVE_QCH			0x3018
+#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH		0x301c
+#define QCH_CON_APBIF_PMU_ALIVE_QCH			0x3020
+#define QCH_CON_APBIF_RTC_QCH				0x3024
+#define QCH_CON_APBIF_TRTC_QCH				0x3028
+#define QCH_CON_APM_CMU_APM_QCH				0x302c
+#define QCH_CON_APM_USI0_UART_QCH			0x3030
+#define QCH_CON_APM_USI0_USI_QCH			0x3034
+#define QCH_CON_APM_USI1_UART_QCH			0x3038
+#define QCH_CON_D_TZPC_APM_QCH				0x303c
+#define QCH_CON_GPC_APM_QCH				0x3040
+#define QCH_CON_GREBEINTEGRATION_QCH_DBG		0x3044
+#define QCH_CON_GREBEINTEGRATION_QCH_GREBE		0x3048
+#define QCH_CON_INTMEM_QCH				0x304c
+#define QCH_CON_LHM_AXI_G_SWD_QCH			0x3050
+#define QCH_CON_LHM_AXI_P_AOCAPM_QCH			0x3054
+#define QCH_CON_LHM_AXI_P_APM_QCH			0x3058
+#define QCH_CON_LHS_AXI_D_APM_QCH			0x305c
+#define QCH_CON_LHS_AXI_G_DBGCORE_QCH			0x3060
+#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH			0x3064
+#define QCH_CON_MAILBOX_APM_AOC_QCH			0x3068
+#define QCH_CON_MAILBOX_APM_AP_QCH			0x306c
+#define QCH_CON_MAILBOX_APM_GSA_QCH			0x3070
+#define QCH_CON_MAILBOX_APM_SWD_QCH			0x3078
+#define QCH_CON_MAILBOX_APM_TPU_QCH			0x307c
+#define QCH_CON_MAILBOX_AP_AOC_QCH			0x3080
+#define QCH_CON_MAILBOX_AP_DBGCORE_QCH			0x3084
+#define QCH_CON_PMU_INTR_GEN_QCH			0x3088
+#define QCH_CON_ROM_CRC32_HOST_QCH			0x308c
+#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE		0x3090
+#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG	0x3094
+#define QCH_CON_SPEEDY_APM_QCH				0x3098
+#define QCH_CON_SPEEDY_SUB_APM_QCH			0x309c
+#define QCH_CON_SSMT_D_APM_QCH				0x30a0
+#define QCH_CON_SSMT_G_DBGCORE_QCH			0x30a4
+#define QCH_CON_SS_DBGCORE_QCH_DBG			0x30a8
+#define QCH_CON_SS_DBGCORE_QCH_GREBE			0x30ac
+#define QCH_CON_SYSMMU_D_APM_QCH			0x30b0
+#define QCH_CON_SYSREG_APM_QCH				0x30b8
+#define QCH_CON_UASC_APM_QCH				0x30bc
+#define QCH_CON_UASC_DBGCORE_QCH			0x30c0
+#define QCH_CON_UASC_G_SWD_QCH				0x30c4
+#define QCH_CON_UASC_P_AOCAPM_QCH			0x30c8
+#define QCH_CON_UASC_P_APM_QCH				0x30cc
+#define QCH_CON_WDT_APM_QCH				0x30d0
+#define QUEUE_CTRL_REG_BLK_APM_CMU_APM			0x3c00
+
+static const unsigned long apm_clk_regs[] __initconst = {
+	APM_CMU_APM_CONTROLLER_OPTION,
+	CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
+	CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
+	CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
+	CLK_CON_DIV_DIV_CLK_APM_BOOST,
+	CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
+	CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
+	CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
+	CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
+	CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
+	CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
+	CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
+};
+
+PNAME(mout_apm_func_p)	= { "oscclk_apmgsa", "mout_apm_funcsrc", "pad_clk_apm" };
+PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
+
+static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
+	FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
+	FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
+	FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
+};
+
+static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
+	    CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
+	MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
+};
+
+static const struct samsung_div_clock apm_div_clks[] __initconst = {
+	DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
+	    CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
+	DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
+	    CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
+	DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
+	    CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
+	DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
+	    CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
+};
+
+static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
+	     CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
+
+	GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+	     "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
+	     21, 0, 0),
+
+	GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+	     "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
+	     21, 0, 0),
+
+	GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+	     "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
+	     21, CLK_IS_CRITICAL, 0),
+
+	GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+	     "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
+	     21, 0, 0),
+};
+
+static const struct samsung_cmu_info apm_cmu_info __initconst = {
+	.mux_clks		= apm_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(apm_mux_clks),
+	.div_clks		= apm_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(apm_div_clks),
+	.gate_clks		= apm_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(apm_gate_clks),
+	.fixed_clks		= apm_fixed_clks,
+	.nr_fixed_clks		= ARRAY_SIZE(apm_fixed_clks),
+	.nr_clk_ids		= APM_NR_CLK,
+	.clk_regs		= apm_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
+};
+
+/* ---- platform_driver ----------------------------------------------------- */
+
+static int __init gs101_cmu_probe(struct platform_device *pdev)
+{
+	const struct samsung_cmu_info *info;
+	struct device *dev = &pdev->dev;
+
+	info = of_device_get_match_data(dev);
+	exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+	return 0;
+}
+
+static const struct of_device_id gs101_cmu_of_match[] = {
+	{
+		.compatible = "google,gs101-cmu-apm",
+		.data = &apm_cmu_info,
+	}, {
+	},
+};
+
+static struct platform_driver gs101_cmu_driver __refdata = {
+	.driver	= {
+		.name = "gs101-cmu",
+		.of_match_table = gs101_cmu_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = gs101_cmu_probe,
+};
+
+static int __init gs101_cmu_init(void)
+{
+	return platform_driver_register(&gs101_cmu_driver);
+}
+core_initcall(gs101_cmu_init);
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 12/20] clk: samsung: clk-gs101: Add support for CMU_MISC clock unit

[Peter Griffin]

CMU Misc clocks IPs such as Watchdog. Add support for the
muxes, dividers and gates in this CMU.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 drivers/clk/samsung/clk-gs101.c | 312 ++++++++++++++++++++++++++++++++
 1 file changed, 312 insertions(+)

diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 525f95e60665..bf2bd8cd39d0 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -20,6 +20,7 @@
 /* NOTE: Must be equal to the last clock ID increased by one */
 #define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
 #define APM_NR_CLK                     (CLK_APM_PLL_DIV16_APM + 1)
+#define MISC_NR_CLK                    (CLK_GOUT_MISC_WDT_CLUSTER1 + 1)
 
 /* ---- CMU_TOP ------------------------------------------------------------- */
 
@@ -1815,6 +1816,314 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
 	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
 };
 
+/* ---- CMU_MISC ------------------------------------------------------------- */
+/* Register Offset definitions for CMU_MISC (0x10010000) */
+#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER	0x0600
+#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER	0x0604
+#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER	0x0610
+#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER	0x0614
+#define MISC_CMU_MISC_CONTROLLER_OPTION		0x0800
+#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0	0x0810
+#define CLK_CON_MUX_MUX_CLK_MISC_GIC		0x1000
+#define CLK_CON_DIV_DIV_CLK_MISC_BUSP		0x1800
+#define CLK_CON_DIV_DIV_CLK_MISC_GIC		0x1804
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK		0x2000
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK		0x2004
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK		0x2008
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK		0x200c
+#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK	0x2010
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM		0x2014
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM		0x2018
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM		0x201c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A			0x2020
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK		0x2024
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK			0x2028
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK			0x202c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK	0x2030
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK		0x2034
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK		0x2038
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK		0x203c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK		0x2040
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK	0x2044
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK		0x2048
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK			0x204c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK		0x2050
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK		0x2054
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK		0x2058
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK			0x205c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK			0x2060
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK			0x2064
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK			0x2068
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK			0x206c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK			0x2070
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK			0x2074
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK			0x2078
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK			0x207c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK		0x2080
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK		0x2084
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK			0x2088
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK			0x208c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK			0x2090
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK			0x2094
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK			0x2098
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK			0x209c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK	0x20a0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK	0x20a4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK	0x20a8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK	0x20ac
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK			0x20b0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK			0x20b4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK			0x20b8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK			0x20bc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK			0x20c0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK			0x20c4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK			0x20c8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK		0x20cc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK		0x20d0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK			0x20d4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK			0x20d8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK			0x20dc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK			0x20e0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK			0x20e4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK			0x20e8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK			0x20ec
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK			0x20f0
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2		0x20f4
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1		0x20f8
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK		0x20fc
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK			0x2100
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK			0x2104
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK		0x2108
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK		0x210c
+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK			0x2110
+#define DMYQCH_CON_PPMU_DMA_QCH			0x3000
+#define DMYQCH_CON_PUF_QCH			0x3004
+#define PCH_CON_LHM_AXI_D_SSS_PCH		0x300c
+#define PCH_CON_LHM_AXI_P_GIC_PCH		0x3010
+#define PCH_CON_LHM_AXI_P_MISC_PCH		0x3014
+#define PCH_CON_LHS_ACEL_D_MISC_PCH		0x3018
+#define PCH_CON_LHS_AST_IRI_GICCPU_PCH		0x301c
+#define PCH_CON_LHS_AXI_D_SSS_PCH		0x3020
+#define QCH_CON_ADM_AHB_SSS_QCH			0x3024
+#define QCH_CON_DIT_QCH				0x3028
+#define QCH_CON_GIC_QCH				0x3030
+#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH		0x3038
+#define QCH_CON_LHM_AXI_D_SSS_QCH		0x303c
+#define QCH_CON_LHM_AXI_P_GIC_QCH		0x3040
+#define QCH_CON_LHM_AXI_P_MISC_QCH		0x3044
+#define QCH_CON_LHS_ACEL_D_MISC_QCH		0x3048
+#define QCH_CON_LHS_AST_IRI_GICCPU_QCH		0x304c
+#define QCH_CON_LHS_AXI_D_SSS_QCH		0x3050
+#define QCH_CON_MCT_QCH				0x3054
+#define QCH_CON_MISC_CMU_MISC_QCH		0x3058
+#define QCH_CON_OTP_CON_BIRA_QCH		0x305c
+#define QCH_CON_OTP_CON_BISR_QCH		0x3060
+#define QCH_CON_OTP_CON_TOP_QCH			0x3064
+#define QCH_CON_PDMA_QCH			0x3068
+#define QCH_CON_PPMU_MISC_QCH			0x306c
+#define QCH_CON_QE_DIT_QCH			0x3070
+#define QCH_CON_QE_PDMA_QCH			0x3074
+#define QCH_CON_QE_PPMU_DMA_QCH			0x3078
+#define QCH_CON_QE_RTIC_QCH			0x307c
+#define QCH_CON_QE_SPDMA_QCH			0x3080
+#define QCH_CON_QE_SSS_QCH			0x3084
+#define QCH_CON_RTIC_QCH			0x3088
+#define QCH_CON_SPDMA_QCH			0x308c
+#define QCH_CON_SSMT_DIT_QCH			0x3090
+#define QCH_CON_SSMT_PDMA_QCH			0x3094
+#define QCH_CON_SSMT_PPMU_DMA_QCH		0x3098
+#define QCH_CON_SSMT_RTIC_QCH			0x309c
+#define QCH_CON_SSMT_SPDMA_QCH			0x30a0
+#define QCH_CON_SSMT_SSS_QCH			0x30a4
+#define QCH_CON_SSS_QCH				0x30a8
+#define QCH_CON_SYSMMU_MISC_QCH			0x30ac
+#define QCH_CON_SYSMMU_SSS_QCH			0x30b0
+#define QCH_CON_SYSREG_MISC_QCH			0x30b4
+#define QCH_CON_TMU_SUB_QCH			0x30b8
+#define QCH_CON_TMU_TOP_QCH			0x30bc
+#define QCH_CON_WDT_CLUSTER0_QCH		0x30c0
+#define QCH_CON_WDT_CLUSTER1_QCH		0x30c4
+#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC	0x3c00
+
+static const unsigned long misc_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
+	PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
+	PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
+	PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
+	MISC_CMU_MISC_CONTROLLER_OPTION,
+	CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
+	CLK_CON_MUX_MUX_CLK_MISC_GIC,
+	CLK_CON_DIV_DIV_CLK_MISC_BUSP,
+	CLK_CON_DIV_DIV_CLK_MISC_GIC,
+	CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
+	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
+	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
+	CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
+	DMYQCH_CON_PPMU_DMA_QCH,
+	DMYQCH_CON_PUF_QCH,
+	PCH_CON_LHM_AXI_D_SSS_PCH,
+	PCH_CON_LHM_AXI_P_GIC_PCH,
+	PCH_CON_LHM_AXI_P_MISC_PCH,
+	PCH_CON_LHS_ACEL_D_MISC_PCH,
+	PCH_CON_LHS_AST_IRI_GICCPU_PCH,
+	PCH_CON_LHS_AXI_D_SSS_PCH,
+	QCH_CON_ADM_AHB_SSS_QCH,
+	QCH_CON_DIT_QCH,
+	QCH_CON_GIC_QCH,
+	QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
+	QCH_CON_LHM_AXI_D_SSS_QCH,
+	QCH_CON_LHM_AXI_P_GIC_QCH,
+	QCH_CON_LHM_AXI_P_MISC_QCH,
+	QCH_CON_LHS_ACEL_D_MISC_QCH,
+	QCH_CON_LHS_AST_IRI_GICCPU_QCH,
+	QCH_CON_LHS_AXI_D_SSS_QCH,
+	QCH_CON_MCT_QCH,
+	QCH_CON_MISC_CMU_MISC_QCH,
+	QCH_CON_OTP_CON_BIRA_QCH,
+	QCH_CON_OTP_CON_BISR_QCH,
+	QCH_CON_OTP_CON_TOP_QCH,
+	QCH_CON_PDMA_QCH,
+	QCH_CON_PPMU_MISC_QCH,
+	QCH_CON_QE_DIT_QCH,
+	QCH_CON_QE_PDMA_QCH,
+	QCH_CON_QE_PPMU_DMA_QCH,
+	QCH_CON_QE_RTIC_QCH,
+	QCH_CON_QE_SPDMA_QCH,
+	QCH_CON_QE_SSS_QCH,
+	QCH_CON_RTIC_QCH,
+	QCH_CON_SPDMA_QCH,
+	QCH_CON_SSMT_DIT_QCH,
+	QCH_CON_SSMT_PDMA_QCH,
+	QCH_CON_SSMT_PPMU_DMA_QCH,
+	QCH_CON_SSMT_RTIC_QCH,
+	QCH_CON_SSMT_SPDMA_QCH,
+	QCH_CON_SSMT_SSS_QCH,
+	QCH_CON_SSS_QCH,
+	QCH_CON_SYSMMU_MISC_QCH,
+	QCH_CON_SYSMMU_SSS_QCH,
+	QCH_CON_SYSREG_MISC_QCH,
+	QCH_CON_TMU_SUB_QCH,
+	QCH_CON_TMU_TOP_QCH,
+	QCH_CON_WDT_CLUSTER0_QCH,
+	QCH_CON_WDT_CLUSTER1_QCH,
+	QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
+};
+
+/* List of parent clocks for Muxes in CMU_MISC */
+PNAME(mout_misc_bus_user_p)		= { "oscclk", "dout_cmu_misc_bus" };
+PNAME(mout_misc_sss_user_p)		= { "oscclk", "dout_cmu_misc_sss" };
+
+static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
+	    PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
+	MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
+	    PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
+};
+
+static const struct samsung_div_clock misc_div_clks[] __initconst = {
+	DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
+	    CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
+	DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
+	    CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
+};
+
+static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_MISC_PCLK, "gout_misc_pclk", "dout_misc_busp",
+	     CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
+	     21, 0, 0),
+
+	GATE(CLK_GOUT_MISC_SYSREG_PCLK, "gout_misc_sysreg_pclk", "dout_misc_busp",
+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
+	     21, 0, 0),
+
+	GATE(CLK_GOUT_MISC_WDT_CLUSTER0, "gout_misc_wdt_cluster0", "dout_misc_busp",
+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
+	     21, 0, 0),
+
+	GATE(CLK_GOUT_MISC_WDT_CLUSTER1, "gout_misc_wdt_cluster1", "dout_misc_busp",
+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
+	     21, 0, 0),
+
+};
+
+static const struct samsung_cmu_info misc_cmu_info __initconst = {
+	.mux_clks		= misc_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(misc_mux_clks),
+	.div_clks		= misc_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(misc_div_clks),
+	.gate_clks		= misc_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(misc_gate_clks),
+	.nr_clk_ids		= MISC_NR_CLK,
+	.clk_regs		= misc_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(misc_clk_regs),
+	.clk_name		= "dout_misc_bus",
+};
+
 /* ---- platform_driver ----------------------------------------------------- */
 
 static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -1832,6 +2141,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
 	{
 		.compatible = "google,gs101-cmu-apm",
 		.data = &apm_cmu_info,
+	}, {
+		.compatible = "google,gs101-cmu-misc",
+		.data = &misc_cmu_info,
 	}, {
 	},
 };
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 13/20] pinctrl: samsung: Add filter selection support for alive banks

[Peter Griffin]

Newer Exynos SoCs have a filter selection register on alive bank pins.
This allows the selection of a digital or delay filter for each pin. If
the filter selection register is not available then the default filter
(digital) is applied.

On suspend we apply the analog filter to all pins in the bank, and on
resume the digital filter is reapplied to all pins in the bank.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c  | 82 ++++++++++++++++++++++-
 drivers/pinctrl/samsung/pinctrl-exynos.h  |  7 ++
 drivers/pinctrl/samsung/pinctrl-samsung.c |  2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h | 23 +++++++
 4 files changed, 113 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index a8212fc126bf..800831aa8357 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -269,6 +269,68 @@ struct exynos_eint_gpio_save {
 	u32 eint_mask;
 };
 
+static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d,
+				   struct samsung_pin_bank *bank, int filter)
+{
+	unsigned int flt_reg, flt_con = 0;
+	unsigned int val, shift;
+	int i;
+	int loop_cnt;
+
+	/*
+	 * This function sets the desired filter (digital or delay) to
+	 * every pin in the bank. Note the filter selection bitfield is
+	 * only found on alive banks. The FLTCON register has the
+	 * following layout
+	 *
+	 * BitfieldName[PinNum][Bit:Bit]
+	 *
+	 * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
+	 * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
+	 * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
+	 * FLT_EN[0][7]  FLT_SEL[0][6]  FLT_WIDTH[0][5:0]
+	 */
+
+	flt_con |= EXYNOS9_FLTCON_EN;
+
+	if (filter)
+		flt_con |= EXYNOS9_FLTCON_SEL_DIGITAL;
+
+	flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
+
+	if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN)
+		/*
+		 * if nr_pins > 4, we should set FLTCON0 register fully.
+		 * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
+		 */
+		loop_cnt = EXYNOS9_FLTCON_NR_PIN;
+	else
+		loop_cnt = bank->nr_pins;
+
+	val = readl(d->virt_base + flt_reg);
+
+	for (i = 0; i < loop_cnt; i++) {
+		shift = i * EXYNOS9_FLTCON_LEN;
+		val &= ~(EXYNOS9_FLTCON_MASK << shift);
+		val |= (flt_con << shift);
+	}
+
+	writel(val, d->virt_base + flt_reg);
+
+	/* loop for FLTCON1 pin 4 ~ 7 */
+	if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) {
+		val = readl(d->virt_base + flt_reg + 0x4);
+		loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN);
+
+		for (i = 0; i < loop_cnt; i++) {
+			shift = i * EXYNOS9_FLTCON_LEN;
+			val &= ~(EXYNOS9_FLTCON_MASK << shift);
+			val |= (flt_con << shift);
+		}
+		writel(val, d->virt_base + flt_reg + 0x4);
+	}
+}
+
 /*
  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
  * @d: driver data of samsung pinctrl driver.
@@ -321,6 +383,9 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 			goto err_domains;
 		}
 
+		/* Set Delay Analog Filter */
+		if (bank->fltcon_type != FLT_DEFAULT)
+			exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DELAY);
 	}
 
 	return 0;
@@ -555,6 +620,10 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 		if (bank->eint_type != EINT_TYPE_WKUP)
 			continue;
 
+		/* Set Digital Filter */
+		if (bank->fltcon_type != FLT_DEFAULT)
+			exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DIGITAL);
+
 		bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
 					      GFP_KERNEL);
 		if (!bank->irq_chip) {
@@ -658,6 +727,7 @@ static void exynos_pinctrl_suspend_bank(
 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
 {
 	struct samsung_pin_bank *bank = drvdata->pin_banks;
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
 	struct exynos_irq_chip *irq_chip = NULL;
 	int i;
 
@@ -665,6 +735,9 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
 		if (bank->eint_type == EINT_TYPE_GPIO)
 			exynos_pinctrl_suspend_bank(drvdata, bank);
 		else if (bank->eint_type == EINT_TYPE_WKUP) {
+			/* Setting Delay (Analog) Filter */
+			if (bank->fltcon_type != FLT_DEFAULT)
+				exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DELAY);
 			if (!irq_chip) {
 				irq_chip = bank->irq_chip;
 				irq_chip->set_eint_wakeup_mask(drvdata,
@@ -707,11 +780,18 @@ static void exynos_pinctrl_resume_bank(
 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
 {
 	struct samsung_pin_bank *bank = drvdata->pin_banks;
+	struct samsung_pinctrl_drv_data *d = bank->drvdata;
 	int i;
 
 	for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
-		if (bank->eint_type == EINT_TYPE_GPIO)
+		if (bank->eint_type == EINT_TYPE_GPIO) {
 			exynos_pinctrl_resume_bank(drvdata, bank);
+		} else if (bank->eint_type == EINT_TYPE_WKUP ||
+			bank->eint_type == EINT_TYPE_WKUP_MUX) {
+			/* Set Digital Filter */
+			if (bank->fltcon_type != FLT_DEFAULT)
+				exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DIGITAL);
+		}
 }
 
 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 7bd6d82c9f36..63b2426ad5d6 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -50,6 +50,13 @@
 
 #define EXYNOS_EINT_MAX_PER_BANK	8
 #define EXYNOS_EINT_NR_WKUP_EINT
+/* EINT filter configuration */
+#define EXYNOS9_FLTCON_EN		BIT(7)
+#define EXYNOS9_FLTCON_SEL_DIGITAL	BIT(6)
+#define EXYNOS9_FLTCON_SEL_DELAY	0
+#define EXYNOS9_FLTCON_MASK		0xff
+#define EXYNOS9_FLTCON_LEN		8
+#define EXYNOS9_FLTCON_NR_PIN		4
 
 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id)		\
 	{						\
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index e54847040b4a..449f8109d8b5 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1104,6 +1104,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
 		bank->eint_func = bdata->eint_func;
 		bank->eint_type = bdata->eint_type;
 		bank->eint_mask = bdata->eint_mask;
+		bank->fltcon_type = bdata->fltcon_type;
+		bank->fltcon_offset = bdata->fltcon_offset;
 		bank->eint_offset = bdata->eint_offset;
 		bank->name = bdata->name;
 
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 9af93e3d8d9f..de2ca8e8b378 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -82,6 +82,21 @@ enum eint_type {
 	EINT_TYPE_WKUP_MUX,
 };
 
+/**
+ * enum fltcon_type - filter selection
+ * @FLT_DEFAULT: filter not selectable, default digital filter
+ * @FLT_SELECT: filter selectable (digital or delay)
+ *
+ * Some banks on some SoCs (gs101 and possibly others) have a selectable
+ * filter on alive banks of 'delay/analog' or 'digital'. If the filter
+ * selection is not available then the default filter is used (digital).
+ */
+
+enum fltcon_type {
+	FLT_DEFAULT,
+	FLT_SELECTABLE,
+};
+
 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
 #define PIN_NAME_LENGTH	10
 
@@ -122,6 +137,8 @@ struct samsung_pin_bank_type {
  * @eint_type: type of the external interrupt supported by the bank.
  * @eint_mask: bit mask of pins which support EINT function.
  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
+ * @fltcon_type: whether the filter (delay/digital) is selectable
+ * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
  * @name: name to be prefixed for each pin in this pin bank.
  */
 struct samsung_pin_bank_data {
@@ -133,6 +150,8 @@ struct samsung_pin_bank_data {
 	enum eint_type	eint_type;
 	u32		eint_mask;
 	u32		eint_offset;
+	enum fltcon_type fltcon_type;
+	u32		fltcon_offset;
 	const char	*name;
 };
 
@@ -147,6 +166,8 @@ struct samsung_pin_bank_data {
  * @eint_type: type of the external interrupt supported by the bank.
  * @eint_mask: bit mask of pins which support EINT function.
  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
+ * @fltcon_type: whether the filter (delay/digital) is selectable
+ * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
  * @name: name to be prefixed for each pin in this pin bank.
  * @pin_base: starting pin number of the bank.
  * @soc_priv: per-bank private data for SoC-specific code.
@@ -169,6 +190,8 @@ struct samsung_pin_bank {
 	enum eint_type	eint_type;
 	u32		eint_mask;
 	u32		eint_offset;
+	enum fltcon_type fltcon_type;
+	u32		fltcon_offset;
 	const char	*name;
 
 	u32		pin_base;
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 14/20] pinctrl: samsung: Add gs101 SoC pinctrl configuration

[Peter Griffin]

Add support for the pin-controller found on the gs101 SoC used in
Pixel 6 phones.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 163 ++++++++++++++++++
 drivers/pinctrl/samsung/pinctrl-exynos.c      |   2 +
 drivers/pinctrl/samsung/pinctrl-exynos.h      |  34 ++++
 drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
 5 files changed, 202 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index cb965cf93705..db47001d1b35 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
 	.ctrl		= fsd_pin_ctrl,
 	.num_ctrl	= ARRAY_SIZE(fsd_pin_ctrl),
 };
+
+/*
+ * bank type for non-alive type
+ * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
+ * (CONPDN bit field: 2, PUDPDN bit field: 4)
+ */
+static struct samsung_pin_bank_type gs101_bank_type_off  = {
+	.fld_width = { 4, 1, 4, 4, 2, 4, },
+	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
+};
+
+/*
+ * bank type for alive type
+ * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
+ */
+static const struct samsung_pin_bank_type gs101_bank_type_alive = {
+	.fld_width = { 4, 1, 4, 4, },
+	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
+/* pin banks of gs101 pin-controller (ALIVE) */
+static const struct samsung_pin_bank_data gs101_pin_alive[] = {
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
+};
+
+/* pin banks of gs101 pin-controller (FAR_ALIVE) */
+static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
+};
+
+/* pin banks of gs101 pin-controller (GSACORE) */
+static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (GSACTRL) */
+static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
+	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (PERIC0) */
+static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (PERIC1) */
+static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (HSI1) */
+static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
+};
+
+/* pin banks of gs101 pin-controller (HSI2) */
+static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
+	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
+};
+
+static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
+	{
+		/* pin banks of gs101 pin-controller (ALIVE) */
+		.pin_banks	= gs101_pin_alive,
+		.nr_banks	= ARRAY_SIZE(gs101_pin_alive),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+	}, {
+		/* pin banks of gs101 pin-controller (FAR_ALIVE) */
+		.pin_banks	= gs101_pin_far_alive,
+		.nr_banks	= ARRAY_SIZE(gs101_pin_far_alive),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+	}, {
+		/* pin banks of gs101 pin-controller (GSACORE) */
+		.pin_banks	= gs101_pin_gsacore,
+		.nr_banks	= ARRAY_SIZE(gs101_pin_gsacore),
+		.eint_gpio_init = exynos_eint_gpio_init,
+	}, {
+		/* pin banks of gs101 pin-controller (GSACTRL) */
+		.pin_banks	= gs101_pin_gsactrl,
+		.nr_banks	= ARRAY_SIZE(gs101_pin_gsactrl),
+		.eint_gpio_init = exynos_eint_gpio_init,
+	}, {
+		/* pin banks of gs101 pin-controller (PERIC0) */
+		.pin_banks	= gs101_pin_peric0,
+		.nr_banks	= ARRAY_SIZE(gs101_pin_peric0),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+	}, {
+		/* pin banks of gs101 pin-controller (PERIC1) */
+		.pin_banks	= gs101_pin_peric1,
+		.nr_banks	= ARRAY_SIZE(gs101_pin_peric1),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume	= exynos_pinctrl_resume,
+	}, {
+		/* pin banks of gs101 pin-controller (HSI1) */
+		.pin_banks	= gs101_pin_hsi1,
+		.nr_banks	= ARRAY_SIZE(gs101_pin_hsi1),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+	}, {
+		/* pin banks of gs101 pin-controller (HSI2) */
+		.pin_banks	= gs101_pin_hsi2,
+		.nr_banks	= ARRAY_SIZE(gs101_pin_hsi2),
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.suspend	= exynos_pinctrl_suspend,
+		.resume		= exynos_pinctrl_resume,
+	},
+};
+
+const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
+	.ctrl		= gs101_pin_ctrl,
+	.num_ctrl	= ARRAY_SIZE(gs101_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 800831aa8357..014f0c37f97f 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -533,6 +533,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
 			.data = &exynos7_wkup_irq_chip },
 	{ .compatible = "samsung,exynosautov9-wakeup-eint",
 			.data = &exynos7_wkup_irq_chip },
+	{ .compatible = "google,gs101-wakeup-eint",
+			.data = &exynos7_wkup_irq_chip },
 	{ }
 };
 
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 63b2426ad5d6..0dd013654bd2 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -147,6 +147,40 @@
 		.name		= id				\
 	}
 
+#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id)	\
+	{						\
+		.type		= &types,		\
+		.pctl_offset	= reg,			\
+		.nr_pins	= pins,			\
+		.eint_type	= EINT_TYPE_NONE,	\
+		.fltcon_type	= FLT_DEFAULT		\
+		.name		= id			\
+	}
+
+#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
+	{						\
+		.type		= &types,		\
+		.pctl_offset	= reg,			\
+		.nr_pins	= pins,			\
+		.eint_type	= EINT_TYPE_GPIO,	\
+		.eint_offset	= offs,			\
+		.fltcon_type    = fltcontype,		\
+		.fltcon_offset	= fltcon_offs,		\
+		.name		= id			\
+	}
+
+#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
+	{						\
+		.type		= &types,		\
+		.pctl_offset	= reg,			\
+		.nr_pins	= pins,			\
+		.eint_type	= EINT_TYPE_WKUP,	\
+		.eint_offset	= offs,			\
+		.fltcon_type    = fltcontype,		\
+		.fltcon_offset	= fltcon_offs,		\
+		.name		= id			\
+	}
+
 /**
  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
  * generated by the external wakeup interrupt controller.
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 449f8109d8b5..12176f98440d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
 		.data = &exynosautov9_of_data },
 	{ .compatible = "tesla,fsd-pinctrl",
 		.data = &fsd_of_data },
+	{ .compatible = "google,gs101-pinctrl",
+		.data = &gs101_of_data },
 #endif
 #ifdef CONFIG_PINCTRL_S3C64XX
 	{ .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index de2ca8e8b378..e62e909fb10d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -374,6 +374,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
 extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
 extern const struct samsung_pinctrl_of_match_data fsd_of_data;
+extern const struct samsung_pinctrl_of_match_data gs101_of_data;
 extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
 extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
 extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 15/20] watchdog: s3c2410_wdt: Add support for Google tensor SoCs

[Peter Griffin]

This patch adds the compatibles and drvdata for the Google
gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
to Exynos850 it has two watchdog instances, one for each cluster
and has some control bits in PMU registers.

The watchdog IP found in gs101 SoCs also supports a few
additional bits/features in the WTCON register which we add
support for and an additional register detailed below.

dbgack-mask - Enables masking WDT interrupt and reset request
according to asserted DBGACK input

windowed-mode - Enabled Windowed watchdog mode

Windowed watchdog mode also has an additional register WTMINCNT.
If windowed watchdog is enabled and you reload WTCNT when the
value is greater than WTMINCNT, it prompts interrupt or reset
request as if the watchdog time has expired.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 drivers/watchdog/s3c2410_wdt.c | 127 ++++++++++++++++++++++++++++++---
 1 file changed, 116 insertions(+), 11 deletions(-)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 0b4bd883ff28..36c170047180 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -31,12 +31,14 @@
 #define S3C2410_WTDAT		0x04
 #define S3C2410_WTCNT		0x08
 #define S3C2410_WTCLRINT	0x0c
-
+#define S3C2410_WTMINCNT	0x10
 #define S3C2410_WTCNT_MAXCNT	0xffff
 
-#define S3C2410_WTCON_RSTEN	(1 << 0)
-#define S3C2410_WTCON_INTEN	(1 << 2)
-#define S3C2410_WTCON_ENABLE	(1 << 5)
+#define S3C2410_WTCON_RSTEN		(1 << 0)
+#define S3C2410_WTCON_INTEN		(1 << 2)
+#define S3C2410_WTCON_ENABLE		(1 << 5)
+#define S3C2410_WTCON_DBGACK_MASK	(1 << 16)
+#define S3C2410_WTCON_WINDOWED_WD	(1 << 20)
 
 #define S3C2410_WTCON_DIV16	(0 << 3)
 #define S3C2410_WTCON_DIV32	(1 << 3)
@@ -51,6 +53,7 @@
 
 #define S3C2410_WATCHDOG_ATBOOT		(0)
 #define S3C2410_WATCHDOG_DEFAULT_TIME	(15)
+#define S3C2410_WINDOW_MULTIPLIER	2
 
 #define EXYNOS5_RST_STAT_REG_OFFSET		0x0404
 #define EXYNOS5_WDT_DISABLE_REG_OFFSET		0x0408
@@ -67,6 +70,13 @@
 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT	25
 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT	24
 
+#define GS_CLUSTER0_NONCPU_OUT			0x1220
+#define GS_CLUSTER1_NONCPU_OUT			0x1420
+#define GS_CLUSTER0_NONCPU_INT_EN		0x1244
+#define GS_CLUSTER1_NONCPU_INT_EN		0x1444
+#define GS_CLUSTER2_NONCPU_INT_EN		0x1644
+#define GS_RST_STAT_REG_OFFSET			0x3B44
+
 /**
  * DOC: Quirk flags for different Samsung watchdog IP-cores
  *
@@ -106,6 +116,8 @@
 #define QUIRK_HAS_PMU_RST_STAT			(1 << 2)
 #define QUIRK_HAS_PMU_AUTO_DISABLE		(1 << 3)
 #define QUIRK_HAS_PMU_CNT_EN			(1 << 4)
+#define QUIRK_HAS_DBGACK_BIT			(1 << 5)
+#define QUIRK_HAS_WTMINCNT_REG			(1 << 6)
 
 /* These quirks require that we have a PMU register map */
 #define QUIRKS_HAVE_PMUREG \
@@ -263,6 +275,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
 		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
 };
 
+static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
+	.mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
+	.mask_bit = 2,
+	.mask_reset_inv = true,
+	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+	.rst_stat_bit = 0,
+	.cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
+	.cnt_en_bit = 8,
+	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
+	.mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
+	.mask_bit = 2,
+	.mask_reset_inv = true,
+	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+	.rst_stat_bit = 1,
+	.cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
+	.cnt_en_bit = 7,
+	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
+	.mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
+	.mask_bit = 2,
+	.mask_reset_inv = true,
+	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+	.rst_stat_bit = 0,
+	.cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
+	.cnt_en_bit = 8,
+	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
+static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
+	.mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
+	.mask_bit = 2,
+	.mask_reset_inv = true,
+	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
+	.rst_stat_bit = 1,
+	.cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
+	.cnt_en_bit = 7,
+	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
+		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
+};
+
 static const struct of_device_id s3c2410_wdt_match[] = {
 	{ .compatible = "samsung,s3c2410-wdt",
 	  .data = &drv_data_s3c2410 },
@@ -278,6 +338,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
 	  .data = &drv_data_exynos850_cl0 },
 	{ .compatible = "samsung,exynosautov9-wdt",
 	  .data = &drv_data_exynosautov9_cl0 },
+	{ .compatible = "google,gs101-wdt",
+	  .data = &drv_data_gs101_cl0 },
+	{ .compatible = "google,gs201-wdt",
+	  .data = &drv_data_gs201_cl0 },
 	{},
 };
 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
@@ -375,6 +439,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
 	return 0;
 }
 
+static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
+{
+	unsigned long wtcon;
+
+	if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
+		return;
+
+	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
+	if (mask)
+		wtcon |= S3C2410_WTCON_DBGACK_MASK;
+	else
+		wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
+	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
+}
+
 static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
 {
 	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
@@ -410,7 +489,7 @@ static int s3c2410wdt_stop(struct watchdog_device *wdd)
 
 static int s3c2410wdt_start(struct watchdog_device *wdd)
 {
-	unsigned long wtcon;
+	unsigned long wtcon, wtmincnt;
 	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 	unsigned long flags;
 
@@ -432,6 +511,12 @@ static int s3c2410wdt_start(struct watchdog_device *wdd)
 	dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
 		wdt->count, wtcon);
 
+	if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) {
+		wtcon |= S3C2410_WTCON_WINDOWED_WD;
+		wtmincnt = wdt->count * S3C2410_WINDOW_MULTIPLIER;
+		writel(wtmincnt, wdt->reg_base + S3C2410_WTMINCNT);
+	}
+
 	writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
 	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
 	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
@@ -447,7 +532,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
 	unsigned long freq = s3c2410wdt_get_freq(wdt);
 	unsigned int count;
 	unsigned int divisor = 1;
-	unsigned long wtcon;
+	unsigned long wtcon, wtmincnt;
 
 	if (timeout < 1)
 		return -EINVAL;
@@ -478,6 +563,11 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
 	count = DIV_ROUND_UP(count, divisor);
 	wdt->count = count;
 
+	if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) {
+		wtmincnt = count * S3C2410_WINDOW_MULTIPLIER;
+		writel(wtmincnt, wdt->reg_base + S3C2410_WTMINCNT);
+	}
+
 	/* update the pre-scaler */
 	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 	wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
@@ -496,14 +586,20 @@ static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
 {
 	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 	void __iomem *wdt_base = wdt->reg_base;
+	unsigned long wtcon;
 
 	/* disable watchdog, to be safe  */
 	writel(0, wdt_base + S3C2410_WTCON);
 
 	/* put initial values into count and data */
+	if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
+		writel(0x100, wdt_base + S3C2410_WTMINCNT);
 	writel(0x80, wdt_base + S3C2410_WTCNT);
 	writel(0x80, wdt_base + S3C2410_WTDAT);
 
+	if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
+		wtcon |= S3C2410_WTCON_WINDOWED_WD;
+
 	/* set the watchdog to go and reset... */
 	writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
 		S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
@@ -585,9 +681,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
 	}
 
 #ifdef CONFIG_OF
-	/* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
+	/* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
 	if (variant == &drv_data_exynos850_cl0 ||
-	    variant == &drv_data_exynosautov9_cl0) {
+	    variant == &drv_data_exynosautov9_cl0 ||
+	    variant == &drv_data_gs101_cl0 ||
+	    variant == &drv_data_gs201_cl0) {
 		u32 index;
 		int err;
 
@@ -600,9 +698,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
 		case 0:
 			break;
 		case 1:
-			variant = (variant == &drv_data_exynos850_cl0) ?
-				&drv_data_exynos850_cl1 :
-				&drv_data_exynosautov9_cl1;
+			if (variant == &drv_data_exynos850_cl0)
+				variant = &drv_data_exynos850_cl1;
+			else if (variant == &drv_data_exynosautov9_cl0)
+				variant = &drv_data_exynosautov9_cl1;
+			else if (variant == &drv_data_gs101_cl0)
+				variant = &drv_data_gs101_cl1;
+			else if (variant == &drv_data_gs201_cl0)
+				variant = &drv_data_gs201_cl1;
 			break;
 		default:
 			return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
@@ -700,6 +803,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
 	wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
 	wdt->wdt_device.parent = dev;
 
+	s3c2410wdt_mask_dbgack(wdt, true);
+
 	/*
 	 * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
 	 * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data

[Peter Griffin]

Add serial driver data for Google Tensor gs101 SoC.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 drivers/tty/serial/samsung_tty.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index 07fb8a9dac63..26bc52e681a4 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -2597,14 +2597,22 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
 	.fifosize = { 256, 64, 64, 64 },
 };
 
+static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
+	EXYNOS_COMMON_SERIAL_DRV_DATA(),
+	/* rely on samsung,uart-fifosize DT property for fifosize */
+	.fifosize = { 0 },
+};
+
 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
+#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
 
 #else
 #define EXYNOS4210_SERIAL_DRV_DATA NULL
 #define EXYNOS5433_SERIAL_DRV_DATA NULL
 #define EXYNOS850_SERIAL_DRV_DATA NULL
+#define GS101_SERIAL_DRV_DATA NULL
 #endif
 
 #ifdef CONFIG_ARCH_APPLE
@@ -2688,6 +2696,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
 	}, {
 		.name		= "artpec8-uart",
 		.driver_data	= (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
+	}, {
+		.name		= "gs101-uart",
+		.driver_data	= (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
 	},
 	{ },
 };
@@ -2709,6 +2720,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
 		.data = EXYNOS850_SERIAL_DRV_DATA },
 	{ .compatible = "axis,artpec8-uart",
 		.data = ARTPEC8_SERIAL_DRV_DATA },
+	{ .compatible = "google,gs101-uart",
+		.data =  GS101_SERIAL_DRV_DATA },
 	{},
 };
 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Peter Griffin]

Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
(oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
phones. It features:
* 4xA55 little cluster
* 2xA76 Mid cluster
* 2xX1 Big cluster

This commit adds the basic device tree for gs101 (SoC).
Further platform support will be added over time.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm64/Kconfig.platforms                  |    6 +
 arch/arm64/boot/dts/Makefile                  |    1 +
 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 +++++++++++++++++
 arch/arm64/boot/dts/google/gs101-pinctrl.h    |   32 +
 arch/arm64/boot/dts/google/gs101.dtsi         |  504 +++++++
 5 files changed, 1818 insertions(+)
 create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
 create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6069120199bb..a5ed1b719488 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -107,6 +107,12 @@ config ARCH_EXYNOS
 	help
 	  This enables support for ARMv8 based Samsung Exynos SoC family.
 
+config ARCH_GOOGLE_TENSOR
+	bool "Google Tensor SoC fmaily"
+	depends on ARCH_EXYNOS
+	help
+	  Support for ARMv8 based Google Tensor platforms.
+
 config ARCH_SPARX5
 	bool "Microchip Sparx5 SoC family"
 	select PINCTRL
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 30dd6347a929..a4ee7b628114 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -13,6 +13,7 @@ subdir-y += broadcom
 subdir-y += cavium
 subdir-y += exynos
 subdir-y += freescale
+subdir-y += google
 subdir-y += hisilicon
 subdir-y += intel
 subdir-y += lg
diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
new file mode 100644
index 000000000000..ba88000c3ed8
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
@@ -0,0 +1,1275 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * GS101 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright 2019-2023 Google LLC
+ *
+ */
+
+#include "gs101-pinctrl.h"
+
+/* GPIO_ALIVE */
+&pinctrl_0 {
+	gpa0: gpa0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa1: gpa1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa2: gpa2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa3: gpa3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa4: gpa4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa5: gpa5-gpio-bank  {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa9: gpa9-gpio-bank  {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa10: gpa10-gpio-bank  {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	uart15_bus: uart15-bus-pins {
+	       samsung,pins = "gpa2-3", "gpa2-4";
+	       samsung,pin-function = <2>;
+	       samsung,pin-pud = <0>;
+	};
+
+	uart16_bus: uart16-bus-pins {
+	       samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
+	       samsung,pin-function = <GS101_PIN_FUNC_2>;
+	       samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+	};
+
+	uart16_bus_rts: uart1-bus-rts-pins {
+		samsung,pins = "gpa3-2";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-val = <1>;
+	};
+
+	uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
+		samsung,pins = "gpa3-1";
+		samsung,pin-val = <1>;
+	};
+
+	uart16_bus_tx_con: uart1-bus-tx-con-pins {
+		samsung,pins = "gpa3-1";
+		samsung,pin-function = <1>;
+	};
+
+	uart17_bus: uart17-bus-pins {
+	       samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
+	       samsung,pin-function = <2>;
+	       samsung,pin-pud = <0>;
+	};
+
+	spi15_bus: spi15-bus-pins {
+		samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi15_cs: spi15-cs-pins {
+		samsung,pins = "gpa4-3";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+};
+
+/* GPIO_FAR_ALIVE */
+&pinctrl_1 {
+	gpa6: gpa6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa7: gpa7-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa8: gpa8-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpa11: gpa11-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+/* GPIO_GSACORE */
+&pinctrl_2 {
+	gps0: gps0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gps1: gps1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gps2: gps2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+/* GPIO_GSACTRL */
+&pinctrl_3 {
+	gps3: gps3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+/* GPIO_HSI1 */
+&pinctrl_6 {
+	gph0: gph0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph1: gph1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	pcie0_clkreq: pcie0-clkreq-pins{
+		samsung,pins = "gph0-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+		samsung,pin-con-pdn = <3>;
+		samsung,pin-pud-pdn = <3>;
+	};
+
+	pcie0_perst: pcie0-perst-pins {
+		samsung,pins = "gph0-0";
+		samsung,pin-function = <1>;
+		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+		samsung,pin-con-pdn = <3>;
+	};
+};
+
+/* GPIO_HSI2 */
+&pinctrl_7 {
+	gph2: gph2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph3: gph3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph4: gph4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	sd2_clk: sd2-clk-pins {
+		samsung,pins = "gph4-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+	};
+
+	sd2_cmd: sd2-cmd-pins {
+		samsung,pins = "gph4-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+	};
+
+	sd2_bus1: sd2-bus-width1-pins {
+		samsung,pins = "gph4-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+	};
+
+	sd2_bus4: sd2-bus-width4-pins {
+		samsung,pins = "gph4-3", "gph4-4", "gph4-5";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+	};
+
+	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
+		samsung,pins = "gph4-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
+		samsung,pins = "gph4-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
+		samsung,pins = "gph4-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+	};
+
+	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
+		samsung,pins = "gph4-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+	};
+
+	ufs_rst_n: ufs-rst-n-pins {
+		samsung,pins = "gph3-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-con-pdn = <3>;
+		samsung,pin-pud-pdn = <0>;
+	};
+
+	ufs_refclk_out: ufs-refclk-out-pins {
+		samsung,pins = "gph3-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-con-pdn = <3>;
+		samsung,pin-pud-pdn = <0>;
+	};
+
+	pcie1_clkreq: pcie1-clkreq-pins {
+		samsung,pins = "gph2-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+		samsung,pin-con-pdn = <3>;
+		samsung,pin-pud-pdn = <3>;
+	};
+
+	pcie1_perst: pcie1-perst-pins {
+		samsung,pins = "gph2-0";
+		samsung,pin-function = <1>;
+		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+		samsung,pin-con-pdn = <3>;
+	};
+};
+
+/* GPIO_PERIC0 */
+&pinctrl_4 {
+	gpp0: gpp0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp1: gpp1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp2: gpp2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp3: gpp3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp4: gpp4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp5: gpp5-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp6: gpp6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp7: gpp7-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp8: gpp8-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp9: gpp9-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp10: gpp10-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp11: gpp11-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp12: gpp12-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp13: gpp13-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp14: gpp14-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp15: gpp15-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp16: gpp16-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp17: gpp17-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp18: gpp18-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp19: gpp19-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	/* USI_PERIC0_UART_DBG */
+	uart0_bus: uart0-bus-pins {
+		samsung,pins = "gpp1-2", "gpp1-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+	};
+
+	disp_te_pri_on: disp-te-pri-on-pins {
+		samsung,pins = "gpp0-3";
+		samsung,pin-function = <0xf>;
+	};
+
+	disp_te_pri_off: disp-te-pri-off-pins {
+		samsung,pins = "gpp0-3";
+		samsung,pin-function = <0>;
+	};
+
+	disp_te_sec_on: disp-te-sec-on-pins {
+		samsung,pins = "gpp0-4";
+		samsung,pin-function = <0xf>;
+	};
+
+	disp_te_sec_off: disp-te-sec-off-pins {
+		samsung,pins = "gpp0-4";
+		samsung,pin-function = <0>;
+	};
+
+	sensor_mclk1_out: sensor-mclk1-out-pins {
+		samsung,pins = "gpp3-0";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk1_fn: sensor-mclk1-fn-pins {
+		samsung,pins = "gpp3-0";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk2_out: sensor-mclk2-out-pins {
+		samsung,pins = "gpp5-0";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk2_fn: sensor-mclk2-fn-pins {
+		samsung,pins = "gpp5-0";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk3_out: sensor-mclk3-out-pins {
+		samsung,pins = "gpp7-0";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk3_fn: sensor-mclk3-fn-pins {
+		samsung,pins = "gpp7-0";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk4_out: sensor-mclk4-out-pins {
+		samsung,pins = "gpp9-0";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk4_fn: sensor-mclk4-fn-pins {
+		samsung,pins = "gpp9-0";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk5_out: sensor-mclk5-out-pins {
+		samsung,pins = "gpp11-0";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk5_fn: sensor-mclk5-fn-pins {
+		samsung,pins = "gpp11-0";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk6_out: sensor-mclk6-out-pins {
+		samsung,pins = "gpp13-0";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk6_fn: sensor-mclk6-fn-pins {
+		samsung,pins = "gpp13-0";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk7_out: sensor-mclk7-out-pins {
+		samsung,pins = "gpp15-0";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk7_fn: sensor-mclk7-fn-pins {
+		samsung,pins = "gpp15-0";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk8_out: sensor-mclk8-out-pins {
+		samsung,pins = "gpp17-0";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	sensor_mclk8_fn: sensor-mclk8-fn-pins {
+		samsung,pins = "gpp17-0";
+		samsung,pin-function = <GS101_PIN_FUNC_2>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+	};
+
+	hsi2c14_bus: hsi2c14-bus-pins {
+		samsung,pins = "gpp18-0", "gpp18-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart14_bus_single: uart14-bus-pins {
+		samsung,pins = "gpp18-0", "gpp18-1",
+			       "gpp18-2", "gpp18-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi14_bus: spi14-bus-pins {
+		samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi14_cs: spi14-cs-pins {
+		samsung,pins = "gpp18-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi14_cs_func: spi14-cs-func-pins {
+		samsung,pins = "gpp18-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c8_bus: hsi2c8-bus-pins {
+		samsung,pins = "gpp16-0", "gpp16-1";
+		samsung,pin-function = <GS101_PIN_FUNC_3>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+		samsung,pin-pud-pdn = <GS101_PIN_PDN_OUT0>;
+	};
+
+	uart8_bus_single: uart8-bus-pins {
+		samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
+			       "gpp16-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi8_bus: spi8-bus-pins {
+		samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi8_cs: spi8-cs-pins {
+		samsung,pins = "gpp16-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi8_cs_func: spi8-cs-func-pins {
+		samsung,pins = "gpp16-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c7_bus: hsi2c7-bus-pins {
+		samsung,pins = "gpp14-0", "gpp14-1";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart7_bus_single: uart7-bus-pins {
+		samsung,pins = "gpp14-0", "gpp14-1",
+			       "gpp14-2", "gpp14-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi7_bus: spi7-bus-pins {
+		samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi7_cs: spi7-cs-pins {
+		samsung,pins = "gpp14-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi7_cs_func: spi7-cs-func-pins {
+		samsung,pins = "gpp14-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c6_bus: hsi2c6-bus-pins {
+		samsung,pins = "gpp12-0", "gpp12-1";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart6_bus_single: uart6-bus-pins {
+		samsung,pins = "gpp12-0", "gpp12-1",
+			       "gpp12-2", "gpp12-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi6_bus: spi6-bus-pins {
+		samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi6_cs: spi6-cs-pins {
+		samsung,pins = "gpp12-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi6_cs_func: spi6-cs-func-pins {
+		samsung,pins = "gpp12-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c5_bus: hsi2c5-bus-pins {
+		samsung,pins = "gpp10-0", "gpp10-1";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart5_bus_single: uart5-bus-pins {
+		samsung,pins = "gpp10-0", "gpp10-1",
+			       "gpp10-2", "gpp10-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi5_bus: spi5-bus-pins {
+		samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+		samsung,pin-function = <GS101_PIN_FUNC_3>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+		samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
+	};
+
+	spi5_cs_func: spi5-cs-func-pins {
+		samsung,pins = "gpp10-3";
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+		samsung,pin-function = <GS101_PIN_FUNC_3>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+		samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
+	};
+
+	hsi2c4_bus: hsi2c4-bus-pins {
+		samsung,pins = "gpp8-0", "gpp8-1";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart4_bus_single: uart4-bus-pins {
+		samsung,pins = "gpp8-0", "gpp8-1",
+			       "gpp8-2", "gpp8-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi4_bus: spi4-bus-pins {
+		samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi4_cs: spi4-cs-pins {
+		samsung,pins = "gpp8-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi4_cs_func: spi4-cs-func-pins {
+		samsung,pins = "gpp8-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c3_bus: hsi2c3-bus-pins {
+		samsung,pins = "gpp6-0", "gpp6-1";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart3_bus_single: uart3-bus-pins {
+		samsung,pins = "gpp6-0", "gpp6-1",
+			       "gpp6-2", "gpp6-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi3_bus: spi3-bus-pins {
+		samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi3_cs: spi3-cs-pins {
+		samsung,pins = "gpp6-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi3_cs_func: spi3-cs-func-pins {
+		samsung,pins = "gpp6-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c2_bus: hsi2c2-bus-pins {
+		samsung,pins = "gpp4-0", "gpp4-1";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart2_bus_single: uart2-bus-pins {
+		samsung,pins = "gpp4-0", "gpp4-1",
+			       "gpp4-2", "gpp4-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi2_bus: spi2-bus-pins {
+		samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi2_cs: spi2-cs-pins {
+		samsung,pins = "gpp4-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi2_cs_func: spi2-cs-func-pins {
+		samsung,pins = "gpp4-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c1_bus: hsi2c1-bus-pins {
+		samsung,pins = "gpp2-0", "gpp2-1";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart1_bus_single: uart1-bus-pins {
+		samsung,pins = "gpp2-0", "gpp2-1",
+			       "gpp2-2", "gpp2-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi1_bus: spi1-bus-pins {
+		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi1_cs: spi1-cs-pins {
+		samsung,pins = "gpp2-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi1_cs_func: spi1-cs-func-pins {
+		samsung,pins = "gpp2-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+};
+
+/* GPIO_PERIC1 */
+&pinctrl_5 {
+	gpp20: gpp20-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp21: gpp21-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp22: gpp22-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp23: gpp23-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp24: gpp24-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp25: gpp25-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp26: gpp26-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp27: gpp27-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	hsi2c13_bus: hsi2c13-bus-pins  {
+		samsung,pins = "gpp25-0", "gpp25-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart13_bus_single: uart13-bus-pins {
+	       samsung,pins = "gpp25-0", "gpp25-1",
+			      "gpp25-2", "gpp25-3";
+	       samsung,pin-function = <2>;
+	       samsung,pin-pud = <0>;
+	};
+
+	spi13_bus: spi13-bus-pins {
+		samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi13_cs: spi13-cs-pins {
+		samsung,pins = "gpp25-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi13_cs_func: spi13-cs-func-pins {
+		samsung,pins = "gpp25-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c12_bus: hsi2c12-bus-pins {
+		samsung,pins = "gpp23-4", "gpp23-5";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart12_bus_single: uart12-bus-pins {
+		samsung,pins = "gpp23-4", "gpp23-5",
+			       "gpp23-6", "gpp23-7";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi12_bus: spi12-bus-pins {
+		samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi14_cs2: spi14-cs2-pins {
+		samsung,pins = "gpp23-6";
+		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi12_cs: spi12-cs-pins {
+		samsung,pins = "gpp23-7";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi12_cs_func: spi12-cs-func-pins {
+		samsung,pins = "gpp23-7";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c11_bus: hsi2c11-bus-pins {
+		samsung,pins = "gpp23-0", "gpp23-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart11_bus_single: uart11-bus-pins {
+		samsung,pins = "gpp23-0", "gpp23-1",
+			       "gpp23-2", "gpp23-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi11_bus: spi11-bus-pins {
+		samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi11_cs: spi11-cs-pins {
+		samsung,pins = "gpp23-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi11_cs_func: spi11-cs-func-pins {
+		samsung,pins = "gpp23-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c10_bus: hsi2c10-bus-pins {
+		samsung,pins = "gpp21-0", "gpp21-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart10_bus_single: uart10-bus-pins {
+		samsung,pins = "gpp21-0", "gpp21-1",
+			       "gpp21-2", "gpp21-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi10_bus: spi10-bus-pins {
+		samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi10_cs: spi10-cs-pins {
+		samsung,pins = "gpp21-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi10_cs_func: spi10-cs-func-pins {
+		samsung,pins = "gpp21-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c9_bus: hsi2c9-bus-pins {
+		samsung,pins = "gpp20-4", "gpp20-5";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart9_bus_single: uart9-bus-pins {
+		samsung,pins = "gpp20-4", "gpp20-5",
+			       "gpp20-6", "gpp20-7";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi9_bus: spi9-bus-pins {
+		samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi9_cs: spi9-cs-pins {
+		samsung,pins = "gpp20-7";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi9_cs_func: spi9-cs-func-pins {
+		samsung,pins = "gpp20-7";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	hsi2c0_bus: hsi2c0-bus-pins {
+		samsung,pins = "gpp20-0", "gpp20-1";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	uart0_bus_single: uart0-bus-pins {
+		samsung,pins = "gpp20-0", "gpp20-1",
+			       "gpp20-2", "gpp20-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+	};
+
+	spi0_bus: spi0-bus-pins {
+		samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi0_cs: spi0-cs-pins {
+		samsung,pins = "gpp20-3";
+		samsung,pin-function = <1>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	spi0_cs_func: spi0-cs-func-pins {
+		samsung,pins = "gpp20-3";
+		samsung,pin-function = <3>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+};
+
diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
new file mode 100644
index 000000000000..16c54888f4bb
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl binding constants for GS101
+ *
+ * Copyright (c) 2020-2023 Google, LLC.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
+#define __DT_BINDINGS_PINCTRL_GS101_H__
+
+#define GS101_PIN_PULL_NONE		0
+#define GS101_PIN_PULL_DOWN		1
+#define GS101_PIN_PULL_UP		3
+
+/* Pin function in power down mode */
+#define GS101_PIN_PDN_OUT0		0
+#define GS101_PIN_PDN_OUT1		1
+#define GS101_PIN_PDN_INPUT		2
+#define GS101_PIN_PDN_PREV		3
+
+/* GS101 drive strengths */
+#define GS101_PIN_DRV_2_5_MA		0
+#define GS101_PIN_DRV_5_MA		1
+#define GS101_PIN_DRV_7_5_MA		2
+#define GS101_PIN_DRV_10_MA		3
+
+#define GS101_PIN_FUNC_INPUT		0
+#define GS101_PIN_FUNC_OUTPUT		1
+#define GS101_PIN_FUNC_2		2
+#define GS101_PIN_FUNC_3		3
+
+#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
new file mode 100644
index 000000000000..37fb0a4dc8d3
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101.dtsi
@@ -0,0 +1,504 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * GS101 SoC
+ *
+ * Copyright 2019-2023 Google LLC
+ *
+ */
+
+#include <dt-bindings/clock/google,gs101.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "google,gs101";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	aliases {
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
+		pinctrl3 = &pinctrl_3;
+		pinctrl4 = &pinctrl_4;
+		pinctrl5 = &pinctrl_5;
+		pinctrl6 = &pinctrl_6;
+		pinctrl7 = &pinctrl_7;
+		serial0 = &serial_0;
+	};
+
+	arm-pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	dsu-pmu-0 {
+		compatible = "arm,dsu-pmu";
+		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+		       <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+	};
+
+	/* TODO replace with CCF clock */
+	dummy_clk: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12345>;
+		clock-output-names = "pclk";
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&cpu6>;
+				};
+				core1 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0000>;
+			enable-method = "psci";
+			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
+			capacity-dmips-mhz = <250>;
+			dynamic-power-coefficient = <70>;
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0100>;
+			enable-method = "psci";
+			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
+			capacity-dmips-mhz = <250>;
+			dynamic-power-coefficient = <70>;
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0200>;
+			enable-method = "psci";
+			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
+			capacity-dmips-mhz = <250>;
+			dynamic-power-coefficient = <70>;
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0300>;
+			enable-method = "psci";
+			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
+			capacity-dmips-mhz = <250>;
+			dynamic-power-coefficient = <70>;
+		};
+
+		cpu4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0400>;
+			enable-method = "psci";
+			cpu-idle-states =  <&ENYO_CPU_SLEEP>;
+			capacity-dmips-mhz = <620>;
+			dynamic-power-coefficient = <284>;
+		};
+
+		cpu5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0500>;
+			enable-method = "psci";
+			cpu-idle-states =  <&ENYO_CPU_SLEEP>;
+			capacity-dmips-mhz = <620>;
+			dynamic-power-coefficient = <284>;
+		};
+
+		cpu6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0600>;
+			enable-method = "psci";
+			cpu-idle-states =  <&HERA_CPU_SLEEP>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <650>;
+		};
+
+		cpu7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0700>;
+			enable-method = "psci";
+			cpu-idle-states =  <&HERA_CPU_SLEEP>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <650>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			ANANKE_CPU_SLEEP: cpu-ananke-sleep {
+				idle-state-name = "c2";
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				entry-latency-us = <70>;
+				exit-latency-us = <160>;
+				min-residency-us = <2000>;
+			};
+
+			ENYO_CPU_SLEEP: cpu-enyo-sleep {
+				idle-state-name = "c2";
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				entry-latency-us = <150>;
+				exit-latency-us = <190>;
+				min-residency-us = <2500>;
+			};
+
+			HERA_CPU_SLEEP: cpu-hera-sleep {
+				idle-state-name = "c2";
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				entry-latency-us = <235>;
+				exit-latency-us = <220>;
+				min-residency-us = <3500>;
+			};
+		};
+	};
+
+	/* bootloader requires ect node */
+	ect {
+		parameter_address = <0x90000000>;
+		parameter_size = <0x53000>;
+	};
+
+	ext_24_5m: clock-1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+		clock-output-names = "oscclk";
+	};
+
+	ext_200m: clock-2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		clock-output-names = "ext-200m";
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		gsa_reserved_protected: gsa@90200000 {
+			reg = <0x0 0x90200000 0x400000>;
+			no-map;
+		};
+
+		tpu_fw_reserved: tpu-fw@93000000 {
+			reg = <0x0 0x93000000 0x1000000>;
+			no-map;
+		};
+
+		aoc_reserve: aoc@94000000 {
+			reg = <0x0 0x94000000 0x03000000>;
+			no-map;
+		};
+
+		abl_reserved: abl@f8800000 {
+			reg = <0x0 0xf8800000 0x02000000>;
+			no-map;
+		};
+
+		dss_log_reserved: dss-log-reserved@fd3f0000 {
+			reg = <0 0xfd3f0000 0x0000e000>;
+			no-map;
+		};
+
+		debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
+			reg = <0 0xfd3fe000 0x00001000>;
+			no-map;
+		};
+
+		bldr_log_reserved: bldr-log-reserved@fd800000 {
+			reg = <0 0xfd800000 0x00100000>;
+			no-map;
+		};
+
+		bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
+			reg = <0 0xfd900000 0x00002000>;
+			no-map;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24576000>;
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		cmu_misc: clock-controller@10010000 {
+			compatible = "google,gs101-cmu-misc";
+			reg = <0x0 0x10010000 0x8000>;
+			#clock-cells = <1>;
+			clocks =  <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
+			clock-names = "oscclk", "dout_cmu_misc_bus";
+		};
+
+		watchdog_cl0: watchdog@10060000 {
+			compatible = "google,gs101-wdt";
+			reg = <0x0 0x10060000 0x100>;
+			interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <0>;
+		};
+
+		watchdog_cl1: watchdog@10070000 {
+			compatible = "google,gs101-wdt";
+			reg = <0x0 0x10070000 0x100>;
+			interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <1>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@10400000 {
+		     compatible = "arm,gic-v3";
+		     #interrupt-cells = <3>;
+		     interrupt-controller;
+		     reg = <0x0 0x10400000 0x10000>,	/* GICD */
+			   <0x0 0x10440000 0x100000>;	/* GICR * 8 */
+		     interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sysreg_peric0: syscon@10821000 {
+			compatible = "google,gs101-peric0-sysreg", "syscon";
+			reg = <0x0 0x10821000 0x40000>;
+		};
+
+		/* GPIO_PERIC0 */
+		pinctrl_4: pinctrl@10840000 {
+			compatible = "google,gs101-pinctrl";
+			reg = <0x0 0x10840000 0x00001000>;
+			interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		serial_0: serial@10a00000 {
+			compatible = "google,gs101-uart";
+			reg = <0x0 0x10a00000 0xc0>;
+			reg-io-width = <4>;
+			samsung,uart-fifosize = <256>;
+			interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk 0>, <&dummy_clk 0>;
+			clock-names = "uart", "clk_uart_baud0";
+		};
+
+		/* GPIO_PERIC1 */
+		pinctrl_5: pinctrl@10c40000 {
+			compatible = "google,gs101-pinctrl";
+			reg = <0x0 0x10C40000 0x00001000>;
+			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sysreg_peric1: syscon@10c21000 {
+			compatible = "google,gs101-peric1-sysreg", "syscon";
+			reg = <0x0 0x10C21000 0x40000>;
+		};
+
+		/* GPIO_HSI1 */
+		pinctrl_6: pinctrl@11840000 {
+			compatible = "google,gs101-pinctrl";
+			reg = <0x0 0x11840000 0x00001000>;
+			interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		/* GPIO_HSI2 */
+		pinctrl_7: pinctrl@14440000 {
+			compatible = "google,gs101-pinctrl";
+			reg = <0x0 0x14440000 0x00001000>;
+			interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		cmu_apm: clock-controller@17400000 {
+			compatible = "google,gs101-cmu-apm";
+			reg = <0x0 0x17400000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&ext_24_5m>;
+			clock-names = "oscclk";
+		};
+
+		sysreg_apm: syscon@174204e0 {
+			compatible = "google,gs101-apm-sysreg", "syscon";
+			reg = <0x0 0x174204e0 0x1000>;
+		};
+
+		pmu_system_controller: system-controller@17460000 {
+			compatible = "google,gs101-pmu", "syscon";
+			reg = <0x0 0x17460000 0x10000>;
+		};
+
+		/* GPIO_ALIVE */
+		pinctrl_0: pinctrl@174d0000 {
+			compatible = "google,gs101-pinctrl";
+			reg = <0x0 0x174d0000 0x00001000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+
+			wakeup-interrupt-controller {
+				compatible = "google,gs101-wakeup-eint";
+			};
+		};
+
+		/* GPIO_FAR_ALIVE */
+		pinctrl_1: pinctrl@174e0000 {
+			compatible = "google,gs101-pinctrl";
+			reg = <0x0 0x174e0000 0x00001000>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+
+			wakeup-interrupt-controller {
+				compatible = "google,gs101-wakeup-eint";
+			};
+		};
+
+		/* GPIO_GSACTRL */
+		pinctrl_3: pinctrl@17940000 {
+			compatible = "google,gs101-pinctrl";
+			reg = <0x0 0x17940000 0x00001000>;
+		};
+
+		/* GPIO_GSACORE */
+		pinctrl_2: pinctrl@17a80000 {
+			compatible = "google,gs101-pinctrl";
+			reg = <0x0 0x17a80000 0x00001000>;
+		};
+
+		cmu_top: clock-controller@1e080000 {
+			compatible = "google,gs101-cmu-top";
+			reg = <0x0 0x1e080000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&ext_24_5m>;
+			clock-names = "oscclk";
+		};
+	};
+};
+
+#include "gs101-pinctrl.dtsi"
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 18/20] arm64: dts: google: Add initial Oriole/pixel 6 board support

[Peter Griffin]

Add initial board support for the Pixel 6 phone code named Oriole. This
has been tested with a minimal busybox initramfs and boots to a shell.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm64/boot/dts/google/Makefile         |  4 ++
 arch/arm64/boot/dts/google/gs101-oriole.dts | 79 +++++++++++++++++++++
 2 files changed, 83 insertions(+)
 create mode 100644 arch/arm64/boot/dts/google/Makefile
 create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts

diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
new file mode 100644
index 000000000000..5cea8ff27141
--- /dev/null
+++ b/arch/arm64/boot/dts/google/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
+	gs101-oriole.dtb \
diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
new file mode 100644
index 000000000000..3bebca989d34
--- /dev/null
+++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Oriole Device Tree
+ *
+ * Copyright 2021-2023 Google,LLC
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "gs101-pinctrl.h"
+#include "gs101.dtsi"
+
+/ {
+	model = "Oriole";
+	compatible = "google,gs101-oriole", "google,gs101";
+
+	chosen {
+		bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_voldown &key_volup &key_power>;
+
+		button-vol-down {
+			label = "KEY_VOLUMEDOWN";
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-vol-up {
+			label = "KEY_VOLUMEUP";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-power {
+			label = "KEY_POWER";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+	};
+};
+
+&pinctrl_1 {
+	key_voldown: key-voldown-pins {
+		samsung,pins = "gpa7-3";
+		samsung,pin-function = <0xf>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+
+	key_volup: key-volup-pins {
+		samsung,pins = "gpa8-1";
+		samsung,pin-function = <0xf>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+};
+
+&pinctrl_0 {
+	key_power: key-power-pins {
+		samsung,pins = "gpa10-1";
+		samsung,pin-function = <0xf>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
+};
+
+&watchdog_cl0 {
+	timeout-sec = <30>;
+};
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 19/20] arm64: defconfig: Enable Google Tensor SoC

[Peter Griffin]

Add the Google Tensor SoC to the arm64 defconfig

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5315789f4868..8a34603b1822 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -41,6 +41,7 @@ CONFIG_ARCH_BCMBCA=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_GOOGLE_TENSOR=y
 CONFIG_ARCH_SPARX5=y
 CONFIG_ARCH_K3=y
 CONFIG_ARCH_LG1K=y
-- 
2.42.0.655.g421f12c284-goog

[PATCH v3 20/20] MAINTAINERS: add entry for Google Tensor SoC

[Peter Griffin]

Add maintainers entry for the Google tensor SoC based
platforms.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..149a0c364309 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8836,6 +8836,16 @@ S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git
 F:	drivers/firmware/google/
 
+GOOGLE TENSOR SoC SUPPORT
+M:	Peter Griffin <peter.griffin@linaro.org>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	linux-samsung-soc@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+F:	arch/arm64/boot/dts/google/
+F:	drivers/clk/samsung/clk-gs101.c
+F:	include/dt-bindings/clock/google,clk-gs101.h
+
 GPD POCKET FAN DRIVER
 M:	Hans de Goede <hdegoede@redhat.com>
 L:	platform-driver-x86@vger.kernel.org
-- 
2.42.0.655.g421f12c284-goog

Re: [PATCH v3 01/20] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add gs101-pmu compatible to the bindings documentation.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> index e1d716df5dfa..9e497c310532 100644
> --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
> @@ -15,6 +15,7 @@ select:
>      compatible:
>        contains:
>          enum:
> +          - google,gs101-pmu
>            - samsung,exynos3250-pmu
>            - samsung,exynos4210-pmu
>            - samsung,exynos4212-pmu
> @@ -35,6 +36,7 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> +              - google,gs101-pmu
>                - samsung,exynos3250-pmu
>                - samsung,exynos4210-pmu
>                - samsung,exynos4212-pmu
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 15/20] watchdog: s3c2410_wdt: Add support for Google tensor SoCs

[Guenter Roeck]

On Wed, Oct 11, 2023 at 07:48:18PM +0100, Peter Griffin wrote:
> This patch adds the compatibles and drvdata for the Google
> gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> to Exynos850 it has two watchdog instances, one for each cluster
> and has some control bits in PMU registers.
> 
> The watchdog IP found in gs101 SoCs also supports a few
> additional bits/features in the WTCON register which we add
> support for and an additional register detailed below.
> 
> dbgack-mask - Enables masking WDT interrupt and reset request
> according to asserted DBGACK input
> 
> windowed-mode - Enabled Windowed watchdog mode
> 
> Windowed watchdog mode also has an additional register WTMINCNT.
> If windowed watchdog is enabled and you reload WTCNT when the
> value is greater than WTMINCNT, it prompts interrupt or reset
> request as if the watchdog time has expired.

Sorry, I don't understand what the code is doing here.

It looks like it enables window mode unconditionally (?). If so,
what is the impact ? Does it mean that any code requesting multiple
keepalives in a row on the affected hardware will now cause an
immediate reset ? If so, what is the rationale ?

Alternatively, if it enables window mode and configures it such
that WTMINCNT is always equal or larger than WTCNT, what is the
point of enabling window mode in the first place ?

Thanks,
Guenter

> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/watchdog/s3c2410_wdt.c | 127 ++++++++++++++++++++++++++++++---
>  1 file changed, 116 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 0b4bd883ff28..36c170047180 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -31,12 +31,14 @@
>  #define S3C2410_WTDAT		0x04
>  #define S3C2410_WTCNT		0x08
>  #define S3C2410_WTCLRINT	0x0c
> -
> +#define S3C2410_WTMINCNT	0x10
>  #define S3C2410_WTCNT_MAXCNT	0xffff
>  
> -#define S3C2410_WTCON_RSTEN	(1 << 0)
> -#define S3C2410_WTCON_INTEN	(1 << 2)
> -#define S3C2410_WTCON_ENABLE	(1 << 5)
> +#define S3C2410_WTCON_RSTEN		(1 << 0)
> +#define S3C2410_WTCON_INTEN		(1 << 2)
> +#define S3C2410_WTCON_ENABLE		(1 << 5)
> +#define S3C2410_WTCON_DBGACK_MASK	(1 << 16)
> +#define S3C2410_WTCON_WINDOWED_WD	(1 << 20)
>  
>  #define S3C2410_WTCON_DIV16	(0 << 3)
>  #define S3C2410_WTCON_DIV32	(1 << 3)
> @@ -51,6 +53,7 @@
>  
>  #define S3C2410_WATCHDOG_ATBOOT		(0)
>  #define S3C2410_WATCHDOG_DEFAULT_TIME	(15)
> +#define S3C2410_WINDOW_MULTIPLIER	2
>  
>  #define EXYNOS5_RST_STAT_REG_OFFSET		0x0404
>  #define EXYNOS5_WDT_DISABLE_REG_OFFSET		0x0408
> @@ -67,6 +70,13 @@
>  #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT	25
>  #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT	24
>  
> +#define GS_CLUSTER0_NONCPU_OUT			0x1220
> +#define GS_CLUSTER1_NONCPU_OUT			0x1420
> +#define GS_CLUSTER0_NONCPU_INT_EN		0x1244
> +#define GS_CLUSTER1_NONCPU_INT_EN		0x1444
> +#define GS_CLUSTER2_NONCPU_INT_EN		0x1644
> +#define GS_RST_STAT_REG_OFFSET			0x3B44
> +
>  /**
>   * DOC: Quirk flags for different Samsung watchdog IP-cores
>   *
> @@ -106,6 +116,8 @@
>  #define QUIRK_HAS_PMU_RST_STAT			(1 << 2)
>  #define QUIRK_HAS_PMU_AUTO_DISABLE		(1 << 3)
>  #define QUIRK_HAS_PMU_CNT_EN			(1 << 4)
> +#define QUIRK_HAS_DBGACK_BIT			(1 << 5)
> +#define QUIRK_HAS_WTMINCNT_REG			(1 << 6)
>  
>  /* These quirks require that we have a PMU register map */
>  #define QUIRKS_HAVE_PMUREG \
> @@ -263,6 +275,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
>  		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
>  };
>  
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> +	.mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = 0,
> +	.cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> +	.cnt_en_bit = 8,
> +	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> +	.mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = 1,
> +	.cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> +	.cnt_en_bit = 7,
> +	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
> +	.mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = 0,
> +	.cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> +	.cnt_en_bit = 8,
> +	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
> +	.mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = 1,
> +	.cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> +	.cnt_en_bit = 7,
> +	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
>  static const struct of_device_id s3c2410_wdt_match[] = {
>  	{ .compatible = "samsung,s3c2410-wdt",
>  	  .data = &drv_data_s3c2410 },
> @@ -278,6 +338,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
>  	  .data = &drv_data_exynos850_cl0 },
>  	{ .compatible = "samsung,exynosautov9-wdt",
>  	  .data = &drv_data_exynosautov9_cl0 },
> +	{ .compatible = "google,gs101-wdt",
> +	  .data = &drv_data_gs101_cl0 },
> +	{ .compatible = "google,gs201-wdt",
> +	  .data = &drv_data_gs201_cl0 },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> @@ -375,6 +439,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
>  	return 0;
>  }
>  
> +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
> +{
> +	unsigned long wtcon;
> +
> +	if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
> +		return;
> +
> +	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> +	if (mask)
> +		wtcon |= S3C2410_WTCON_DBGACK_MASK;
> +	else
> +		wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
> +	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> +}
> +
>  static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
>  {
>  	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> @@ -410,7 +489,7 @@ static int s3c2410wdt_stop(struct watchdog_device *wdd)
>  
>  static int s3c2410wdt_start(struct watchdog_device *wdd)
>  {
> -	unsigned long wtcon;
> +	unsigned long wtcon, wtmincnt;
>  	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
>  	unsigned long flags;
>  
> @@ -432,6 +511,12 @@ static int s3c2410wdt_start(struct watchdog_device *wdd)
>  	dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
>  		wdt->count, wtcon);
>  
> +	if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) {
> +		wtcon |= S3C2410_WTCON_WINDOWED_WD;
> +		wtmincnt = wdt->count * S3C2410_WINDOW_MULTIPLIER;
> +		writel(wtmincnt, wdt->reg_base + S3C2410_WTMINCNT);
> +	}
> +
>  	writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
>  	writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
>  	writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> @@ -447,7 +532,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
>  	unsigned long freq = s3c2410wdt_get_freq(wdt);
>  	unsigned int count;
>  	unsigned int divisor = 1;
> -	unsigned long wtcon;
> +	unsigned long wtcon, wtmincnt;
>  
>  	if (timeout < 1)
>  		return -EINVAL;
> @@ -478,6 +563,11 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
>  	count = DIV_ROUND_UP(count, divisor);
>  	wdt->count = count;
>  
> +	if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) {
> +		wtmincnt = count * S3C2410_WINDOW_MULTIPLIER;
> +		writel(wtmincnt, wdt->reg_base + S3C2410_WTMINCNT);
> +	}
> +
>  	/* update the pre-scaler */
>  	wtcon = readl(wdt->reg_base + S3C2410_WTCON);
>  	wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
> @@ -496,14 +586,20 @@ static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
>  {
>  	struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
>  	void __iomem *wdt_base = wdt->reg_base;
> +	unsigned long wtcon;
>  
>  	/* disable watchdog, to be safe  */
>  	writel(0, wdt_base + S3C2410_WTCON);
>  
>  	/* put initial values into count and data */
> +	if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> +		writel(0x100, wdt_base + S3C2410_WTMINCNT);
>  	writel(0x80, wdt_base + S3C2410_WTCNT);
>  	writel(0x80, wdt_base + S3C2410_WTDAT);
>  
> +	if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> +		wtcon |= S3C2410_WTCON_WINDOWED_WD;
> +
>  	/* set the watchdog to go and reset... */
>  	writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
>  		S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
> @@ -585,9 +681,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
>  	}
>  
>  #ifdef CONFIG_OF
> -	/* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> +	/* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
>  	if (variant == &drv_data_exynos850_cl0 ||
> -	    variant == &drv_data_exynosautov9_cl0) {
> +	    variant == &drv_data_exynosautov9_cl0 ||
> +	    variant == &drv_data_gs101_cl0 ||
> +	    variant == &drv_data_gs201_cl0) {
>  		u32 index;
>  		int err;
>  
> @@ -600,9 +698,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
>  		case 0:
>  			break;
>  		case 1:
> -			variant = (variant == &drv_data_exynos850_cl0) ?
> -				&drv_data_exynos850_cl1 :
> -				&drv_data_exynosautov9_cl1;
> +			if (variant == &drv_data_exynos850_cl0)
> +				variant = &drv_data_exynos850_cl1;
> +			else if (variant == &drv_data_exynosautov9_cl0)
> +				variant = &drv_data_exynosautov9_cl1;
> +			else if (variant == &drv_data_gs101_cl0)
> +				variant = &drv_data_gs101_cl1;
> +			else if (variant == &drv_data_gs201_cl0)
> +				variant = &drv_data_gs201_cl1;
>  			break;
>  		default:
>  			return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> @@ -700,6 +803,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
>  	wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
>  	wdt->wdt_device.parent = dev;
>  
> +	s3c2410wdt_mask_dbgack(wdt, true);
> +
>  	/*
>  	 * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
>  	 * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Provide dt-schema documentation for Google gs101 SoC clock controller.
> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
>  include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
>  2 files changed, 357 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>  create mode 100644 include/dt-bindings/clock/google,gs101.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..f74494594b3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,125 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 SoC clock controller
> +
> +maintainers:
> +  - Peter Griffin <peter.griffin@linaro.org>
> +
> +description: |
> +  Google GS101 clock controller is comprised of several CMU units, generating
> +  clocks for different domains. Those CMU units are modeled as separate device
> +  tree nodes, and might depend on each other. The root clock in that clock tree
> +  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> +  clock in dts.
> +
> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> +  Each clock is assigned an identifier and client nodes can use this identifier
> +  to specify the clock which they consume. All clocks available for usage
> +  in clock consumer nodes are defined as preprocessor macros in
> +  'dt-bindings/clock/gs101.h' header.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - google,gs101-cmu-top
> +      - google,gs101-cmu-apm
> +      - google,gs101-cmu-misc
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-top
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-misc
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +            - description: Misc bus clock (from CMU_TOP)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +            - const: dout_cmu_misc_bus
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-apm
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +required:
> +  - compatible
> +  - "#clock-cells"
> +  - clocks
> +  - clock-names
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock controller node for CMU_TOP
> +  - |
> +    #include <dt-bindings/clock/google,gs101.h>
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <1>;
> +
> +        cmu_top: clock-controller@1e080000 {
> +            compatible = "google,gs101-cmu-top";
> +            reg = <0x0 0x1e080000 0x8000>;
> +            #clock-cells = <1>;
> +            clocks = <&ext_24_5m>;
> +            clock-names = "oscclk";
> +        };
> +    };
> +
> +...
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> new file mode 100644
> index 000000000000..7765ba68f734
> --- /dev/null
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -0,0 +1,232 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Device Tree binding constants for Google gs101 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +
> +/* CMU_TOP PLL*/
> +#define CLK_FOUT_SHARED0_PLL		1
> +#define CLK_FOUT_SHARED1_PLL		2
> +#define CLK_FOUT_SHARED2_PLL		3
> +#define CLK_FOUT_SHARED3_PLL		4
> +#define CLK_FOUT_SPARE_PLL		5
> +
> +/* CMU_TOP MUX*/
> +#define CLK_MOUT_SHARED0_PLL		6
> +#define CLK_MOUT_SHARED1_PLL		7
> +#define CLK_MOUT_SHARED2_PLL		8
> +#define CLK_MOUT_SHARED3_PLL		9
> +#define CLK_MOUT_SPARE_PLL		10
> +#define CLK_MOUT_BUS0_BUS		11
> +#define CLK_MOUT_CMU_BOOST		12
> +#define CLK_MOUT_BUS1_BUS		13
> +#define CLK_MOUT_BUS2_BUS		14
> +#define CLK_MOUT_CORE_BUS		15
> +#define CLK_MOUT_EH_BUS			16
> +#define CLK_MOUT_CPUCL2_SWITCH		17
> +#define CLK_MOUT_CPUCL1_SWITCH		18
> +#define CLK_MOUT_CPUCL0_SWITCH		19
> +#define CLK_MOUT_CPUCL0_DBG		20
> +#define CLK_MOUT_CMU_HPM		21
> +#define CLK_MOUT_G3D_SWITCH		22
> +#define CLK_MOUT_G3D_GLB		23
> +#define CLK_MOUT_DPU_BUS		24
> +#define CLK_MOUT_DISP_BUS		25
> +#define CLK_MOUT_G2D_G2D		26
> +#define CLK_MOUT_G2D_MSCL		27
> +#define CLK_MOUT_HSI0_USB31DRD		28
> +#define CLK_MOUT_HSI0_BUS		29
> +#define CLK_MOUT_HSI0_DPGTC		30
> +#define CLK_MOUT_HSI0_USBDPDGB		31
> +#define CLK_MOUT_HSI1_BUS		32
> +#define CLK_MOUT_HSI1_PCIE		33
> +#define CLK_MOUT_HSI2_BUS		34
> +#define CLK_MOUT_HSI2_PCIE		35
> +#define CLK_MOUT_HSI2_UFS_EMBD		36
> +#define CLK_MOUT_HSI2_MMC_CARD		37
> +#define CLK_MOUT_CSIS			38
> +#define CLK_MOUT_PDP_BUS		39
> +#define CLK_MOUT_PDP_VRA		40
> +#define CLK_MOUT_IPP_BUS		41
> +#define CLK_MOUT_G3AA			42
> +#define CLK_MOUT_ITP			43
> +#define CLK_MOUT_DNS_BUS		44
> +#define CLK_MOUT_TNR_BUS		45
> +#define CLK_MOUT_MCSC_ITSC		46
> +#define CLK_MOUT_MCSC_MCSC		47
> +#define CLK_MOUT_GDC_SCSC		48
> +#define CLK_MOUT_GDC_GDC0		49
> +#define CLK_MOUT_GDC_GDC1		50
> +#define CLK_MOUT_MFC_MFC		51
> +#define CLK_MOUT_MIF_SWITCH		52
> +#define CLK_MOUT_MIF_BUS		53
> +#define CLK_MOUT_MISC_BUS		54
> +#define CLK_MOUT_MISC_SSS		55
> +#define CLK_MOUT_PERIC0_IP		56
> +#define CLK_MOUT_PERIC0_BUS		57
> +#define CLK_MOUT_PERIC1_IP		58
> +#define CLK_MOUT_PERIC1_BUS		59
> +#define CLK_MOUT_TPU_TPU		60
> +#define CLK_MOUT_TPU_TPUCTL		61
> +#define CLK_MOUT_TPU_BUS		62
> +#define CLK_MOUT_TPU_UART		63
> +#define CLK_MOUT_TPU_HPM		64
> +#define CLK_MOUT_BO_BUS			65
> +#define CLK_MOUT_G3D_BUSD		66
> +
> +/* CMU_TOP Dividers*/
> +#define CLK_DOUT_SHARED0_DIV3		67
> +#define CLK_DOUT_SHARED0_DIV2		68
> +#define CLK_DOUT_SHARED0_DIV4		69
> +#define CLK_DOUT_SHARED0_DIV5		70
> +#define CLK_DOUT_SHARED1_DIV3		71
> +#define CLK_DOUT_SHARED1_DIV2		72
> +#define CLK_DOUT_SHARED1_DIV4		73
> +#define CLK_DOUT_SHARED2_DIV2		74
> +#define CLK_DOUT_SHARED3_DIV2		75
> +#define CLK_DOUT_BUS0_BUS		76
> +#define CLK_DOUT_CMU_BOOST		77
> +#define CLK_DOUT_BUS1_BUS		78
> +#define CLK_DOUT_BUS2_BUS		79
> +#define CLK_DOUT_CORE_BUS		80
> +#define CLK_DOUT_EH_BUS			81
> +#define CLK_DOUT_CPUCL2_SWITCH		82
> +#define CLK_DOUT_CPUCL1_SWITCH		83
> +#define CLK_DOUT_CPUCL0_SWITCH		84
> +#define CLK_DOUT_CPUCL0_DBG		85
> +#define CLK_DOUT_CMU_HPM		86
> +#define CLK_DOUT_G3D_SWITCH		87
> +#define CLK_DOUT_G3D_GLB		88
> +#define CLK_DOUT_DPU_BUS		89
> +#define CLK_DOUT_DISP_BUS		90
> +#define CLK_DOUT_G2D_G2D		91
> +#define CLK_DOUT_G2D_MSCL		92
> +#define CLK_DOUT_HSI0_USB31DRD		93
> +#define CLK_DOUT_HSI0_BUS		94
> +#define CLK_DOUT_HSI0_DPGTC		95
> +#define CLK_DOUT_HSI0_USBDPDGB		96
> +#define CLK_DOUT_HSI1_BUS		97
> +#define CLK_DOUT_HSI1_PCIE		98
> +#define CLK_DOUT_HSI2_BUS		100
> +#define CLK_DOUT_HSI2_PCIE		101
> +#define CLK_DOUT_HSI2_UFS_EMBD		102
> +#define CLK_DOUT_HSI2_MMC_CARD		103
> +#define CLK_DOUT_CSIS			104
> +#define CLK_DOUT_PDP_BUS		105
> +#define CLK_DOUT_PDP_VRA		106
> +#define CLK_DOUT_IPP_BUS		107
> +#define CLK_DOUT_G3AA			108
> +#define CLK_DOUT_ITP			109
> +#define CLK_DOUT_DNS_BUS		110
> +#define CLK_DOUT_TNR_BUS		111
> +#define CLK_DOUT_MCSC_ITSC		112
> +#define CLK_DOUT_MCSC_MCSC		113
> +#define CLK_DOUT_GDC_SCSC		114
> +#define CLK_DOUT_GDC_GDC0		115
> +#define CLK_DOUT_GDC_GDC1		116
> +#define CLK_DOUT_MFC_MFC		117
> +#define CLK_DOUT_MIF_BUS		118
> +#define CLK_DOUT_MISC_BUS		119
> +#define CLK_DOUT_MISC_SSS		120
> +#define CLK_DOUT_PERIC0_BUS		121
> +#define CLK_DOUT_PERIC0_IP		122
> +#define CLK_DOUT_PERIC1_BUS		123
> +#define CLK_DOUT_PERIC1_IP		124
> +#define CLK_DOUT_TPU_TPU		125
> +#define CLK_DOUT_TPU_TPUCTL		126
> +#define CLK_DOUT_TPU_BUS		127
> +#define CLK_DOUT_TPU_UART		128
> +#define CLK_DOUT_TPU_HPM		129
> +#define CLK_DOUT_BO_BUS			130
> +
> +/* CMU_TOP Gates*/
> +#define CLK_GOUT_BUS0_BUS		131
> +#define CLK_GOUT_BUS1_BUS		132
> +#define CLK_GOUT_BUS2_BUS		133
> +#define CLK_GOUT_CORE_BUS		134
> +#define CLK_GOUT_EH_BUS			135
> +#define CLK_GOUT_CPUCL2_SWITCH		136
> +#define CLK_GOUT_CPUCL1_SWITCH		137
> +#define CLK_GOUT_CPUCL0_SWITCH		138
> +#define CLK_GOUT_CPUCL0_DBG		139
> +#define CLK_GOUT_CMU_HPM		140
> +#define CLK_GOUT_G3D_SWITCH		141
> +#define CLK_GOUT_G3D_GLB		142
> +#define CLK_GOUT_DPU_BUS		143
> +#define CLK_GOUT_DISP_BUS		144
> +#define CLK_GOUT_G2D_G2D		145
> +#define CLK_GOUT_G2D_MSCL		146
> +#define CLK_GOUT_HSI0_USB31DRD		147
> +#define CLK_GOUT_HSI0_BUS		148
> +#define CLK_GOUT_HSI0_DPGTC		149
> +#define CLK_GOUT_HSI0_USBDPDGB		150
> +#define CLK_GOUT_HSI1_BUS		151
> +#define CLK_GOUT_HSI1_PCIE		152
> +#define CLK_GOUT_HSI2_BUS		153
> +#define CLK_GOUT_HSI2_PCIE		154
> +#define CLK_GOUT_HSI2_UFS_EMBD		155
> +#define CLK_GOUT_HSI2_MMC_CARD		156
> +#define CLK_GOUT_CSIS			157
> +#define CLK_GOUT_PDP_BUS		158
> +#define CLK_GOUT_PDP_VRA		159
> +#define CLK_GOUT_IPP_BUS		160
> +#define CLK_GOUT_G3AA			161
> +#define CLK_GOUT_ITP			162
> +#define CLK_GOUT_DNS_BUS		163
> +#define CLK_GOUT_TNR_BUS		164
> +#define CLK_GOUT_MCSC_ITSC		165
> +#define CLK_GOUT_MCSC_MCSC		166
> +#define CLK_GOUT_GDC_SCSC		167
> +#define CLK_GOUT_GDC_GDC0		168
> +#define CLK_GOUT_GDC_GDC1		169
> +#define CLK_GOUT_MFC_MFC		170
> +#define CLK_GOUT_MIF_SWITCH		171
> +#define CLK_GOUT_MIF_BUS		172
> +#define CLK_GOUT_MISC_BUS		173
> +#define CLK_GOUT_MISC_SSS		174
> +#define CLK_GOUT_PERIC0_BUS		175
> +#define CLK_GOUT_PERIC0_IP		176
> +#define CLK_GOUT_PERIC1_BUS		177
> +#define CLK_GOUT_PERIC1_IP		178
> +#define CLK_GOUT_TPU_TPU		179
> +#define CLK_GOUT_TPU_TPUCTL		180
> +#define CLK_GOUT_TPU_BUS		181
> +#define CLK_GOUT_TPU_UART		182
> +#define CLK_GOUT_TPU_HPM		183
> +#define CLK_GOUT_BO_BUS			184
> +#define CLK_GOUT_CMU_BOOST		185
> +
> +/* CMU_APM */
> +
> +#define CLK_MOUT_APM_FUNC					1
> +#define CLK_MOUT_APM_FUNCSRC					2
> +#define CLK_DOUT_APM_BOOST					3
> +#define CLK_DOUT_APM_USI0_UART					4
> +#define CLK_DOUT_APM_USI0_USI					5
> +#define CLK_DOUT_APM_USI1_UART					6
> +#define CLK_GOUT_APM_FUNC					7
> +#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK	8
> +#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK	9
> +#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK		10
> +#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK		11
> +#define CLK_APM_PLL_DIV2_APM					12
> +#define CLK_APM_PLL_DIV4_APM					13
> +#define CLK_APM_PLL_DIV16_APM					14
> +
> +/* CMU_MISC */
> +
> +#define CLK_MOUT_MISC_BUS_USER					1
> +#define CLK_MOUT_MISC_SSS_USER					2
> +#define CLK_DOUT_MISC_BUSP					3
> +#define CLK_DOUT_MISC_GIC					4
> +#define CLK_GOUT_MISC_PCLK					5
> +#define CLK_GOUT_MISC_SYSREG_PCLK				6
> +#define CLK_GOUT_MISC_WDT_CLUSTER0				7
> +#define CLK_GOUT_MISC_WDT_CLUSTER1				8
> +
> +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 09/20] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> These plls are found in the Tensor gs101 SoC found in the Pixel 6.
> 
> pll0516x: Integer PLL with high frequency
> pll0517x: Integer PLL with middle frequency
> pll0518x: Integer PLL with low frequency
> 
> PLL0516x
> FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
> 
> PLL0517x and PLL0518x
> FOUT = (MDIV * FIN)/PDIV*2^SDIV)
> 
> The PLLs are similar enough to pll_0822x that the same code can handle
> both. The main difference is the change in the fout formula for the
> high frequency 0516 pll.
> 
> Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
> 
> When defining the PLL the "con" parameter should be set to CON3
> register, like this
> 
> PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
>     PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
>     NULL),
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  drivers/clk/samsung/clk-pll.c | 9 ++++++++-
>  drivers/clk/samsung/clk-pll.h | 3 +++
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 74934c6182ce..4ef9fea2a425 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
>  	pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
>  	sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
>  
> -	fvco *= mdiv;
> +	if (pll->type == pll_0516x)
> +		fvco = fvco * 2 * mdiv;
> +	else
> +		fvco *= mdiv;
> +
>  	do_div(fvco, (pdiv << sdiv));
>  
>  	return (unsigned long)fvco;
> @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>  	case pll_1417x:
>  	case pll_0818x:
>  	case pll_0822x:
> +	case pll_0516x:
> +	case pll_0517x:
> +	case pll_0518x:
>  		pll->enable_offs = PLL0822X_ENABLE_SHIFT;
>  		pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
>  		if (!pll->rate_table)
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 0725d485c6ee..ffd3d52c0dec 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -38,6 +38,9 @@ enum samsung_pll_type {
>  	pll_0822x,
>  	pll_0831x,
>  	pll_142xx,
> +	pll_0516x,
> +	pll_0517x,
> +	pll_0518x,
>  };
>  
>  #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> CMU_TOP is the top level clock management unit which contains PLLs, muxes
> and gates that feed the other clock management units.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  drivers/clk/samsung/Kconfig     |    9 +
>  drivers/clk/samsung/Makefile    |    2 +
>  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
>  3 files changed, 1562 insertions(+)
>  create mode 100644 drivers/clk/samsung/clk-gs101.c
> 
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..14362ec9c543 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
>  	select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
>  	select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
>  	select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> +	select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
>  	select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
>  
>  config S3C64XX_COMMON_CLK
> @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
>  	  status of the certains clocks from SoC, but it could also be tied to
>  	  other devices as an input clock.
>  
> +config GOOGLE_GS101_COMMON_CLK
> +	bool "Google gs101 clock controller support" if COMPILE_TEST
> +	depends on COMMON_CLK_SAMSUNG
> +	depends on EXYNOS_ARM64_COMMON_CLK
> +	help
> +	  Support for the clock controller present on the Google gs101 SoC.
> +	  Choose Y here only if you build for this SoC.
> +
>  config TESLA_FSD_COMMON_CLK
>  	bool "Tesla FSD clock controller support" if COMPILE_TEST
>  	depends on COMMON_CLK_SAMSUNG
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index ebbeacabe88f..49146937d957 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -21,6 +21,8 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7885.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o
> +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK)	+= clk-gs101.o
>  obj-$(CONFIG_S3C64XX_COMMON_CLK)	+= clk-s3c64xx.o
>  obj-$(CONFIG_S5PV210_COMMON_CLK)	+= clk-s5pv210.o clk-s5pv210-audss.o
>  obj-$(CONFIG_TESLA_FSD_COMMON_CLK)	+= clk-fsd.o
> +
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> new file mode 100644
> index 000000000000..e2c62754b1eb
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -0,0 +1,1551 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Common Clock Framework support for GS101.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/google,gs101.h>
> +
> +#include "clk.h"
> +#include "clk-exynos-arm64.h"
> +
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
> +
> +/* ---- CMU_TOP ------------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_TOP (0x1e080000) */
> +
> +#define PLL_LOCKTIME_PLL_SHARED0			0x0000
> +#define PLL_LOCKTIME_PLL_SHARED1			0x0004
> +#define PLL_LOCKTIME_PLL_SHARED2			0x0008
> +#define PLL_LOCKTIME_PLL_SHARED3			0x000c
> +#define PLL_LOCKTIME_PLL_SPARE				0x0010
> +#define PLL_CON0_PLL_SHARED0				0x0100
> +#define PLL_CON1_PLL_SHARED0				0x0104
> +#define PLL_CON2_PLL_SHARED0				0x0108
> +#define PLL_CON3_PLL_SHARED0				0x010c
> +#define PLL_CON4_PLL_SHARED0				0x0110
> +#define PLL_CON0_PLL_SHARED1				0x0140
> +#define PLL_CON1_PLL_SHARED1				0x0144
> +#define PLL_CON2_PLL_SHARED1				0x0148
> +#define PLL_CON3_PLL_SHARED1				0x014c
> +#define PLL_CON4_PLL_SHARED1				0x0150
> +#define PLL_CON0_PLL_SHARED2				0x0180
> +#define PLL_CON1_PLL_SHARED2				0x0184
> +#define PLL_CON2_PLL_SHARED2				0x0188
> +#define PLL_CON3_PLL_SHARED2				0x018c
> +#define PLL_CON4_PLL_SHARED2				0x0190
> +#define PLL_CON0_PLL_SHARED3				0x01c0
> +#define PLL_CON1_PLL_SHARED3				0x01c4
> +#define PLL_CON2_PLL_SHARED3				0x01c8
> +#define PLL_CON3_PLL_SHARED3				0x01cc
> +#define PLL_CON4_PLL_SHARED3				0x01d0
> +#define PLL_CON0_PLL_SPARE				0x0200
> +#define PLL_CON1_PLL_SPARE				0x0204
> +#define PLL_CON2_PLL_SPARE				0x0208
> +#define PLL_CON3_PLL_SPARE				0x020c
> +#define PLL_CON4_PLL_SPARE				0x0210
> +#define CMU_CMU_TOP_CONTROLLER_OPTION			0x0800
> +#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0		0x0810
> +#define CMU_HCHGEN_CLKMUX_CMU_BOOST			0x0840
> +#define CMU_HCHGEN_CLKMUX_TOP_BOOST			0x0844
> +#define CMU_HCHGEN_CLKMUX				0x0850
> +#define POWER_FAIL_DETECT_PLL				0x0864
> +#define EARLY_WAKEUP_FORCED_0_ENABLE			0x0870
> +#define EARLY_WAKEUP_FORCED_1_ENABLE			0x0874
> +#define EARLY_WAKEUP_APM_CTRL				0x0878
> +#define EARLY_WAKEUP_CLUSTER0_CTRL			0x087c
> +#define EARLY_WAKEUP_DPU_CTRL				0x0880
> +#define EARLY_WAKEUP_CSIS_CTRL				0x0884
> +#define EARLY_WAKEUP_APM_DEST				0x0890
> +#define EARLY_WAKEUP_CLUSTER0_DEST			0x0894
> +#define EARLY_WAKEUP_DPU_DEST				0x0898
> +#define EARLY_WAKEUP_CSIS_DEST				0x089c
> +#define EARLY_WAKEUP_SW_TRIG_APM			0x08c0
> +#define EARLY_WAKEUP_SW_TRIG_APM_SET			0x08c4
> +#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR			0x08c8
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0			0x08d0
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET		0x08d4
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR		0x08d8
> +#define EARLY_WAKEUP_SW_TRIG_DPU			0x08e0
> +#define EARLY_WAKEUP_SW_TRIG_DPU_SET			0x08e4
> +#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR			0x08e8
> +#define EARLY_WAKEUP_SW_TRIG_CSIS			0x08f0
> +#define EARLY_WAKEUP_SW_TRIG_CSIS_SET			0x08f4
> +#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR			0x08f8
> +
> +#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS			0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS			0x1004
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS			0x1008
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS			0x100c
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0			0x1010
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1			0x1014
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2			0x1018
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3			0x101c
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4			0x1020
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5			0x1024
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6			0x1028
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7			0x102c
> +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST		0x1030
> +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1	0x1034
> +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS			0x1038
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG		0x103c
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH		0x1040
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH		0x1044
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH		0x1048
> +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS			0x104c
> +#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS			0x1050
> +#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS			0x1054
> +#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS			0x1058
> +#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS			0x105c
> +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D			0x1060
> +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL			0x1064
> +#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA		0x1068
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD			0x106c
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB			0x1070
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH		0x1074
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0			0x1078
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1			0x107c
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC			0x1080
> +#define CLK_CON_MUX_MUX_CLKCMU_HPM			0x1084
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS			0x1088
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC		0x108c
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD		0x1090
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG		0x1094
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS			0x1098
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE		0x109c
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS			0x10a0
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD		0x10a4
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE		0x10a8
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD		0x10ac
> +#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS			0x10b0
> +#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS			0x10b4
> +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC		0x10b8
> +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC		0x10bc
> +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC			0x10c0
> +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP			0x10c4
> +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH		0x10c8
> +#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS			0x10cc
> +#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS			0x10d0
> +#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS			0x10d4
> +#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA			0x10d8
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS		0x10dc
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP		0x10e0
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS		0x10e4
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP		0x10e8
> +#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS			0x10ec
> +#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1	0x10f0
> +#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF		0x10f4
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS			0x10f8
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU			0x10fc
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL		0x1100
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART			0x1104
> +#define CLK_CON_MUX_MUX_CMU_CMUREF			0x1108
> +
> +#define CLK_CON_DIV_CLKCMU_BO_BUS			0x1800
> +#define CLK_CON_DIV_CLKCMU_BUS0_BUS			0x1804
> +#define CLK_CON_DIV_CLKCMU_BUS1_BUS			0x1808
> +#define CLK_CON_DIV_CLKCMU_BUS2_BUS			0x180c
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK0			0x1810
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK1			0x1814
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK2			0x1818
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK3			0x181c
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK4			0x1820
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK5			0x1824
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK6			0x1828
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK7			0x182c
> +#define CLK_CON_DIV_CLKCMU_CORE_BUS			0x1830
> +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG			0x1834
> +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH		0x1838
> +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH		0x183c
> +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH		0x1840
> +#define CLK_CON_DIV_CLKCMU_CSIS_BUS			0x1844
> +#define CLK_CON_DIV_CLKCMU_DISP_BUS			0x1848
> +#define CLK_CON_DIV_CLKCMU_DNS_BUS			0x184c
> +#define CLK_CON_DIV_CLKCMU_DPU_BUS			0x1850
> +#define CLK_CON_DIV_CLKCMU_EH_BUS			0x1854
> +#define CLK_CON_DIV_CLKCMU_G2D_G2D			0x1858
> +#define CLK_CON_DIV_CLKCMU_G2D_MSCL			0x185c
> +#define CLK_CON_DIV_CLKCMU_G3AA_G3AA			0x1860
> +#define CLK_CON_DIV_CLKCMU_G3D_BUSD			0x1864
> +#define CLK_CON_DIV_CLKCMU_G3D_GLB			0x1868
> +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH			0x186c
> +#define CLK_CON_DIV_CLKCMU_GDC_GDC0			0x1870
> +#define CLK_CON_DIV_CLKCMU_GDC_GDC1			0x1874
> +#define CLK_CON_DIV_CLKCMU_GDC_SCSC			0x1878
> +#define CLK_CON_DIV_CLKCMU_HPM				0x187c
> +#define CLK_CON_DIV_CLKCMU_HSI0_BUS			0x1880
> +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC			0x1884
> +#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD		0x1888
> +#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG		0x188c
> +#define CLK_CON_DIV_CLKCMU_HSI1_BUS			0x1890
> +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE			0x1894
> +#define CLK_CON_DIV_CLKCMU_HSI2_BUS			0x1898
> +#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD		0x189c
> +#define CLK_CON_DIV_CLKCMU_HSI2_PCIE			0x18a0
> +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD		0x18a4
> +#define CLK_CON_DIV_CLKCMU_IPP_BUS			0x18a8
> +#define CLK_CON_DIV_CLKCMU_ITP_BUS			0x18ac
> +#define CLK_CON_DIV_CLKCMU_MCSC_ITSC			0x18b0
> +#define CLK_CON_DIV_CLKCMU_MCSC_MCSC			0x18b4
> +#define CLK_CON_DIV_CLKCMU_MFC_MFC			0x18b8
> +#define CLK_CON_DIV_CLKCMU_MIF_BUSP			0x18bc
> +#define CLK_CON_DIV_CLKCMU_MISC_BUS			0x18c0
> +#define CLK_CON_DIV_CLKCMU_MISC_SSS			0x18c4
> +#define CLK_CON_DIV_CLKCMU_OTP				0x18c8
> +#define CLK_CON_DIV_CLKCMU_PDP_BUS			0x18cc
> +#define CLK_CON_DIV_CLKCMU_PDP_VRA			0x18d0
> +#define CLK_CON_DIV_CLKCMU_PERIC0_BUS			0x18d4
> +#define CLK_CON_DIV_CLKCMU_PERIC0_IP			0x18d8
> +#define CLK_CON_DIV_CLKCMU_PERIC1_BUS			0x18dc
> +#define CLK_CON_DIV_CLKCMU_PERIC1_IP			0x18e0
> +#define CLK_CON_DIV_CLKCMU_TNR_BUS			0x18e4
> +#define CLK_CON_DIV_CLKCMU_TPU_BUS			0x18e8
> +#define CLK_CON_DIV_CLKCMU_TPU_TPU			0x18ec
> +#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL			0x18f0
> +#define CLK_CON_DIV_CLKCMU_TPU_UART			0x18f4
> +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST		0x18f8
> +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF			0x18fc
> +#define CLK_CON_DIV_PLL_SHARED0_DIV2			0x1900
> +#define CLK_CON_DIV_PLL_SHARED0_DIV3			0x1904
> +#define CLK_CON_DIV_PLL_SHARED0_DIV4			0x1908
> +#define CLK_CON_DIV_PLL_SHARED0_DIV5			0x190c
> +#define CLK_CON_DIV_PLL_SHARED1_DIV2			0x1910
> +#define CLK_CON_DIV_PLL_SHARED1_DIV3			0x1914
> +#define CLK_CON_DIV_PLL_SHARED1_DIV4			0x1918
> +#define CLK_CON_DIV_PLL_SHARED2_DIV2			0x191c
> +#define CLK_CON_DIV_PLL_SHARED3_DIV2			0x1920
> +
> +/* CLK_CON_GAT_UPDATES */
> +#define CLK_CON_GAT_CLKCMU_BUS0_BOOST			0x2000
> +#define CLK_CON_GAT_CLKCMU_BUS1_BOOST			0x2004
> +#define CLK_CON_GAT_CLKCMU_BUS2_BOOST			0x2008
> +#define CLK_CON_GAT_CLKCMU_CORE_BOOST			0x200c
> +#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST			0x2010
> +#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST			0x2014
> +#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST			0x2018
> +#define CLK_CON_GAT_CLKCMU_MIF_BOOST			0x201c
> +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH			0x2020
> +#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS			0x2024
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS		0x2028
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS		0x202c
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS		0x2030
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0		0x2034
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1		0x2038
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2		0x203c
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3		0x2040
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4		0x2044
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5		0x2048
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6		0x204c
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7		0x2050
> +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST		0x2054
> +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS		0x2058
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS		0x205c
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH		0x2060
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH		0x2064
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH		0x2068
> +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS		0x206c
> +#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS		0x2070
> +#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS			0x2074
> +#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS			0x2078
> +#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS			0x207c
> +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D			0x2080
> +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL		0x2084
> +#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA		0x2088
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD		0x208c
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB			0x2090
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH		0x2094
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0		0x2098
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1		0x209c
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC		0x20a0
> +#define CLK_CON_GAT_GATE_CLKCMU_HPM			0x20a4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS		0x20a8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC		0x20ac
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD		0x20b0
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG		0x20b4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS		0x20b8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE		0x20bc
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS		0x20c0
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD		0x20c4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE		0x20c8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD		0x20cc
> +#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS			0x20d0
> +#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS			0x20d4
> +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC		0x20d8
> +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC		0x20dc
> +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC			0x20e0
> +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP		0x20e4
> +#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS		0x20e8
> +#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS		0x20ec
> +#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS			0x20f0
> +#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA			0x20f4
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS		0x20f8
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP		0x20fc
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS		0x2100
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP		0x2104
> +#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS			0x2108
> +#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF		0x210c
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS			0x2110
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU			0x2114
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL		0x2118
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART		0x211c
> +
> +#define DMYQCH_CON_CMU_TOP_CMUREF_QCH			0x3000
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0		0x3004
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1		0x3008
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2		0x300c
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3		0x3010
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4		0x3014
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5		0x3018
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6		0x301c
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7		0x3020
> +#define DMYQCH_CON_OTP_QCH				0x3024
> +#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP			0x3c00
> +#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP			0x3c10
> +#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP			0x3c14
> +#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP			0x3c18
> +#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP			0x3c1c
> +#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP			0x3c20
> +#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP			0x3c24
> +#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP			0x3c28
> +#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP			0x3c2c
> +#define MIFMIRROR_QUEUE_CTRL_REG			0x3e00
> +#define MIFMIRROR_QUEUE_ENTRY0				0x3e10
> +#define MIFMIRROR_QUEUE_ENTRY1				0x3e14
> +#define MIFMIRROR_QUEUE_ENTRY2				0x3e18
> +#define MIFMIRROR_QUEUE_ENTRY3				0x3e1c
> +#define MIFMIRROR_QUEUE_ENTRY4				0x3e20
> +#define MIFMIRROR_QUEUE_ENTRY5				0x3e24
> +#define MIFMIRROR_QUEUE_ENTRY6				0x3e28
> +#define MIFMIRROR_QUEUE_ENTRY7				0x3e2c
> +#define MIFMIRROR_QUEUE_BUSY				0x3e30
> +#define GENERALIO_ACD_CHANNEL_0				0x3f00
> +#define GENERALIO_ACD_CHANNEL_1				0x3f04
> +#define GENERALIO_ACD_CHANNEL_2				0x3f08
> +#define GENERALIO_ACD_CHANNEL_3				0x3f0c
> +#define GENERALIO_ACD_MASK				0x3f14
> +
> +static const unsigned long cmu_top_clk_regs[] __initconst = {
> +	PLL_LOCKTIME_PLL_SHARED0,
> +	PLL_LOCKTIME_PLL_SHARED1,
> +	PLL_LOCKTIME_PLL_SHARED2,
> +	PLL_LOCKTIME_PLL_SHARED3,
> +	PLL_LOCKTIME_PLL_SPARE,
> +	PLL_CON0_PLL_SHARED0,
> +	PLL_CON1_PLL_SHARED0,
> +	PLL_CON2_PLL_SHARED0,
> +	PLL_CON3_PLL_SHARED0,
> +	PLL_CON4_PLL_SHARED0,
> +	PLL_CON0_PLL_SHARED1,
> +	PLL_CON1_PLL_SHARED1,
> +	PLL_CON2_PLL_SHARED1,
> +	PLL_CON3_PLL_SHARED1,
> +	PLL_CON4_PLL_SHARED1,
> +	PLL_CON0_PLL_SHARED2,
> +	PLL_CON1_PLL_SHARED2,
> +	PLL_CON2_PLL_SHARED2,
> +	PLL_CON3_PLL_SHARED2,
> +	PLL_CON4_PLL_SHARED2,
> +	PLL_CON0_PLL_SHARED3,
> +	PLL_CON1_PLL_SHARED3,
> +	PLL_CON2_PLL_SHARED3,
> +	PLL_CON3_PLL_SHARED3,
> +	PLL_CON4_PLL_SHARED3,
> +	PLL_CON0_PLL_SPARE,
> +	PLL_CON1_PLL_SPARE,
> +	PLL_CON2_PLL_SPARE,
> +	PLL_CON3_PLL_SPARE,
> +	PLL_CON4_PLL_SPARE,
> +	CMU_CMU_TOP_CONTROLLER_OPTION,
> +	CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
> +	CMU_HCHGEN_CLKMUX_CMU_BOOST,
> +	CMU_HCHGEN_CLKMUX_TOP_BOOST,
> +	CMU_HCHGEN_CLKMUX,
> +	POWER_FAIL_DETECT_PLL,
> +	EARLY_WAKEUP_FORCED_0_ENABLE,
> +	EARLY_WAKEUP_FORCED_1_ENABLE,
> +	EARLY_WAKEUP_APM_CTRL,
> +	EARLY_WAKEUP_CLUSTER0_CTRL,
> +	EARLY_WAKEUP_DPU_CTRL,
> +	EARLY_WAKEUP_CSIS_CTRL,
> +	EARLY_WAKEUP_APM_DEST,
> +	EARLY_WAKEUP_CLUSTER0_DEST,
> +	EARLY_WAKEUP_DPU_DEST,
> +	EARLY_WAKEUP_CSIS_DEST,
> +	EARLY_WAKEUP_SW_TRIG_APM,
> +	EARLY_WAKEUP_SW_TRIG_APM_SET,
> +	EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
> +	EARLY_WAKEUP_SW_TRIG_CLUSTER0,
> +	EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
> +	EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
> +	EARLY_WAKEUP_SW_TRIG_DPU,
> +	EARLY_WAKEUP_SW_TRIG_DPU_SET,
> +	EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
> +	EARLY_WAKEUP_SW_TRIG_CSIS,
> +	EARLY_WAKEUP_SW_TRIG_CSIS_SET,
> +	EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
> +	CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
> +	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
> +	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
> +	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
> +	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
> +	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
> +	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
> +	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
> +	CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
> +	CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
> +	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
> +	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
> +	CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
> +	CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
> +	CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
> +	CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
> +	CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
> +	CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
> +	CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
> +	CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
> +	CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
> +	CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
> +	CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
> +	CLK_CON_MUX_MUX_CLKCMU_HPM,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
> +	CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
> +	CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
> +	CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
> +	CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
> +	CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
> +	CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
> +	CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
> +	CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
> +	CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
> +	CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
> +	CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
> +	CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
> +	CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
> +	CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
> +	CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
> +	CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
> +	CLK_CON_MUX_MUX_CMU_CMUREF,
> +	CLK_CON_DIV_CLKCMU_BO_BUS,
> +	CLK_CON_DIV_CLKCMU_BUS0_BUS,
> +	CLK_CON_DIV_CLKCMU_BUS1_BUS,
> +	CLK_CON_DIV_CLKCMU_BUS2_BUS,
> +	CLK_CON_DIV_CLKCMU_CIS_CLK0,
> +	CLK_CON_DIV_CLKCMU_CIS_CLK1,
> +	CLK_CON_DIV_CLKCMU_CIS_CLK2,
> +	CLK_CON_DIV_CLKCMU_CIS_CLK3,
> +	CLK_CON_DIV_CLKCMU_CIS_CLK4,
> +	CLK_CON_DIV_CLKCMU_CIS_CLK5,
> +	CLK_CON_DIV_CLKCMU_CIS_CLK6,
> +	CLK_CON_DIV_CLKCMU_CIS_CLK7,
> +	CLK_CON_DIV_CLKCMU_CORE_BUS,
> +	CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
> +	CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
> +	CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
> +	CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
> +	CLK_CON_DIV_CLKCMU_CSIS_BUS,
> +	CLK_CON_DIV_CLKCMU_DISP_BUS,
> +	CLK_CON_DIV_CLKCMU_DNS_BUS,
> +	CLK_CON_DIV_CLKCMU_DPU_BUS,
> +	CLK_CON_DIV_CLKCMU_EH_BUS,
> +	CLK_CON_DIV_CLKCMU_G2D_G2D,
> +	CLK_CON_DIV_CLKCMU_G2D_MSCL,
> +	CLK_CON_DIV_CLKCMU_G3AA_G3AA,
> +	CLK_CON_DIV_CLKCMU_G3D_BUSD,
> +	CLK_CON_DIV_CLKCMU_G3D_GLB,
> +	CLK_CON_DIV_CLKCMU_G3D_SWITCH,
> +	CLK_CON_DIV_CLKCMU_GDC_GDC0,
> +	CLK_CON_DIV_CLKCMU_GDC_GDC1,
> +	CLK_CON_DIV_CLKCMU_GDC_SCSC,
> +	CLK_CON_DIV_CLKCMU_HPM,
> +	CLK_CON_DIV_CLKCMU_HSI0_BUS,
> +	CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
> +	CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
> +	CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
> +	CLK_CON_DIV_CLKCMU_HSI1_BUS,
> +	CLK_CON_DIV_CLKCMU_HSI1_PCIE,
> +	CLK_CON_DIV_CLKCMU_HSI2_BUS,
> +	CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
> +	CLK_CON_DIV_CLKCMU_HSI2_PCIE,
> +	CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
> +	CLK_CON_DIV_CLKCMU_IPP_BUS,
> +	CLK_CON_DIV_CLKCMU_ITP_BUS,
> +	CLK_CON_DIV_CLKCMU_MCSC_ITSC,
> +	CLK_CON_DIV_CLKCMU_MCSC_MCSC,
> +	CLK_CON_DIV_CLKCMU_MFC_MFC,
> +	CLK_CON_DIV_CLKCMU_MIF_BUSP,
> +	CLK_CON_DIV_CLKCMU_MISC_BUS,
> +	CLK_CON_DIV_CLKCMU_MISC_SSS,
> +	CLK_CON_DIV_CLKCMU_OTP,
> +	CLK_CON_DIV_CLKCMU_PDP_BUS,
> +	CLK_CON_DIV_CLKCMU_PDP_VRA,
> +	CLK_CON_DIV_CLKCMU_PERIC0_BUS,
> +	CLK_CON_DIV_CLKCMU_PERIC0_IP,
> +	CLK_CON_DIV_CLKCMU_PERIC1_BUS,
> +	CLK_CON_DIV_CLKCMU_PERIC1_IP,
> +	CLK_CON_DIV_CLKCMU_TNR_BUS,
> +	CLK_CON_DIV_CLKCMU_TPU_BUS,
> +	CLK_CON_DIV_CLKCMU_TPU_TPU,
> +	CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
> +	CLK_CON_DIV_CLKCMU_TPU_UART,
> +	CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
> +	CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
> +	CLK_CON_DIV_PLL_SHARED0_DIV2,
> +	CLK_CON_DIV_PLL_SHARED0_DIV3,
> +	CLK_CON_DIV_PLL_SHARED0_DIV4,
> +	CLK_CON_DIV_PLL_SHARED0_DIV5,
> +	CLK_CON_DIV_PLL_SHARED1_DIV2,
> +	CLK_CON_DIV_PLL_SHARED1_DIV3,
> +	CLK_CON_DIV_PLL_SHARED1_DIV4,
> +	CLK_CON_DIV_PLL_SHARED2_DIV2,
> +	CLK_CON_DIV_PLL_SHARED3_DIV2,
> +	CLK_CON_GAT_CLKCMU_BUS0_BOOST,
> +	CLK_CON_GAT_CLKCMU_BUS1_BOOST,
> +	CLK_CON_GAT_CLKCMU_BUS2_BOOST,
> +	CLK_CON_GAT_CLKCMU_CORE_BOOST,
> +	CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
> +	CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
> +	CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
> +	CLK_CON_GAT_CLKCMU_MIF_BOOST,
> +	CLK_CON_GAT_CLKCMU_MIF_SWITCH,
> +	CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
> +	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
> +	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
> +	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
> +	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
> +	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
> +	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
> +	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
> +	CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
> +	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
> +	CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
> +	CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
> +	CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
> +	CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
> +	CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
> +	CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
> +	CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
> +	CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
> +	CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
> +	CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
> +	CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
> +	CLK_CON_GAT_GATE_CLKCMU_HPM,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
> +	CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
> +	CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
> +	CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
> +	CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
> +	CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
> +	CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
> +	CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
> +	CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
> +	CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
> +	CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
> +	CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
> +	CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
> +	CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
> +	CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
> +	DMYQCH_CON_CMU_TOP_CMUREF_QCH,
> +	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
> +	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
> +	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
> +	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
> +	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
> +	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
> +	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
> +	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
> +	DMYQCH_CON_OTP_QCH,
> +	QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
> +	QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
> +	QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
> +	QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
> +	QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
> +	QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
> +	QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
> +	QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
> +	QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
> +	MIFMIRROR_QUEUE_CTRL_REG,
> +	MIFMIRROR_QUEUE_ENTRY0,
> +	MIFMIRROR_QUEUE_ENTRY1,
> +	MIFMIRROR_QUEUE_ENTRY2,
> +	MIFMIRROR_QUEUE_ENTRY3,
> +	MIFMIRROR_QUEUE_ENTRY4,
> +	MIFMIRROR_QUEUE_ENTRY5,
> +	MIFMIRROR_QUEUE_ENTRY6,
> +	MIFMIRROR_QUEUE_ENTRY7,
> +	MIFMIRROR_QUEUE_BUSY,
> +	GENERALIO_ACD_CHANNEL_0,
> +	GENERALIO_ACD_CHANNEL_1,
> +	GENERALIO_ACD_CHANNEL_2,
> +	GENERALIO_ACD_CHANNEL_3,
> +	GENERALIO_ACD_MASK,
> +};
> +
> +static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
> +	/* CMU_TOP_PURECLKCOMP */
> +	PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> +	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> +	    NULL),
> +	PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
> +	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
> +	    NULL),
> +	PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
> +	    PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
> +	    NULL),
> +	PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
> +	    PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
> +	    NULL),
> +	PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
> +	    PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
> +	    NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_TOP */
> +PNAME(mout_shared0_pll_p)	= { "oscclk", "fout_shared0_pll" };
> +PNAME(mout_shared1_pll_p)	= { "oscclk", "fout_shared1_pll" };
> +PNAME(mout_shared2_pll_p)	= { "oscclk", "fout_shared2_pll" };
> +PNAME(mout_shared3_pll_p)	= { "oscclk", "fout_shared3_pll" };
> +PNAME(mout_spare_pll_p)		= { "oscclk", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */
> +PNAME(mout_cmu_bus0_bus_p)	= { "dout_shared0_div4", "dout_shared1_div4",
> +				    "dout_shared2_div2", "dout_shared3_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_cmu_boost_p)	= { "dout_shared0_div4", "dout_shared1_div4",
> +				    "dout_shared2_div2", "dout_shared3_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */
> +PNAME(mout_cmu_bus1_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */
> +PNAME(mout_cmu_bus2_bus_p)	= { "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div3", "dout_shared1_div3",
> +				    "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
> +PNAME(mout_cmu_core_bus_p)	= { "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div3", "dout_shared1_div3",
> +				    "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */
> +PNAME(mout_cmu_eh_bus_p)	= { "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div3", "dout_shared1_div3",
> +				    "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */
> +PNAME(mout_cmu_cpucl2_switch_p)	= { "fout_shared1_pll", "dout_shared0_div2",
> +				    "dout_shared1_div2", "fout_shared2_pll",
> +				    "fout_shared3_pll", "dout_shared0_div3",
> +				    "dout_shared1_div3", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
> +PNAME(mout_cmu_cpucl1_switch_p)	= { "fout_shared1_pll", "dout_shared0_div2",
> +				    "dout_shared1_div2", "fout_shared2_pll",
> +				    "fout_shared3_pll", "dout_shared0_div3",
> +				    "dout_shared1_div3", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
> +PNAME(mout_cmu_cpucl0_switch_p)	= { "fout_shared1_pll", "dout_shared0_div2",
> +				    "dout_shared1_div2", "fout_shared2_pll",
> +				    "fout_shared3_pll", "dout_shared0_div3",
> +				    "dout_shared1_div3", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_cpucl0_dbg_p)	= { "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div4", "dout_shared1_div4",
> +				    "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hpm_p)		= { "oscclk", "dout_shared1_div3",
> +				    "dout_shared0_div4", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
> +PNAME(mout_cmu_g3d_switch_p)	= { "fout_shared2_pll", "dout_shared0_div3",
> +				    "fout_shared3_pll", "dout_shared1_div3",
> +				    "dout_shared0_div4", "dout_shared1_div4",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g3d_busd_p)	= { "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div3", "dout_shared1_div3",
> +				    "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g3d_glb_p)	= { "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div3", "dout_shared1_div3",
> +				    "dout_shared0_div4", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
> +PNAME(mout_cmu_dpu_p)		= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */
> +PNAME(mout_cmu_disp_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> +PNAME(mout_cmu_g2d_g2d_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g2d_mscl_p)	= { "dout_shared0_div4", "dout_shared1_div4",
> +				    "dout_shared2_div2", "dout_shared3_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */
> +PNAME(mout_cmu_hsi0_usb31drd_p)	= { "oscclk", "dout_shared2_div2" };
> +
> +PNAME(mout_cmu_hsi0_bus_p)	= { "dout_shared0_div4", "dout_shared1_div4",
> +				    "dout_shared2_div2", "dout_shared3_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi0_dpgtc_p)	= { "oscclk", "dout_shared0_div4",
> +				    "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi0_usbdpdbg_p)	= { "oscclk", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */
> +PNAME(mout_cmu_hsi1_bus_p)	= { "dout_shared0_div4", "dout_shared1_div4",
> +				    "dout_shared2_div2", "dout_shared3_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi1_pcie_p)	= { "oscclk", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */
> +PNAME(mout_cmu_hsi2_bus_p)	= { "dout_shared0_div4", "dout_shared1_div4",
> +				    "dout_shared2_div2", "dout_shared3_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi2_pcie0_p)	= { "oscclk", "dout_shared2_div2" };
> +
> +PNAME(mout_cmu_hsi2_ufs_embd_p)	= { "oscclk", "dout_shared0_div4",
> +				    "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi2_mmc_card_p)	= { "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div4", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
> +PNAME(mout_cmu_csis_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
> +PNAME(mout_cmu_pdp_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_pdp_vra_p)	= { "fout_shared2_pll", "dout_shared0_div3",
> +				    "fout_shared3_pll", "dout_shared1_div3",
> +				    "dout_shared0_div4", "dout_shared1_div4",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
> +PNAME(mout_cmu_ipp_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
> +PNAME(mout_cmu_g3aa_p)		= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
> +PNAME(mout_cmu_itp_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
> +PNAME(mout_cmu_dns_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
> +PNAME(mout_cmu_tnr_bus_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
> +PNAME(mout_cmu_mcsc_itsc_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_mcsc_mcsc_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
> +PNAME(mout_cmu_gdc_scsc_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_gdc_gdc0_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +PNAME(mout_cmu_gdc_gdc1_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
> +PNAME(mout_cmu_mfc_mfc_p)	= { "dout_shared0_div3", "fout_shared3_pll",
> +				    "dout_shared1_div3", "dout_shared0_div4",
> +				    "dout_shared1_div4", "dout_shared2_div2",
> +				    "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
> +
> +PNAME(mout_cmu_mif_switch_p)	= { "fout_shared0_pll", "fout_shared1_pll",
> +				    "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "dout_shared0_div3",
> +				    "fout_shared3_pll", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
> +PNAME(mout_cmu_mif_busp_p)	= { "dout_shared0_div4", "dout_shared1_div4",
> +				    "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
> +PNAME(mout_cmu_misc_bus_p)	= { "dout_shared0_div4", "dout_shared2_div2",
> +				    "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_misc_sss_p)	= { "dout_shared0_div4", "dout_shared2_div2",
> +				    "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
> +PNAME(mout_cmu_peric0_bus_p)	= { "dout_shared0_div4", "dout_shared2_div2",
> +				    "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_peric0_ip_p)	= { "dout_shared0_div4", "dout_shared2_div2",
> +				    "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
> +PNAME(mout_cmu_peric1_bus_p)	= { "dout_shared0_div4", "dout_shared2_div2",
> +				    "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_peric1_ip_p)	= { "dout_shared0_div4", "dout_shared2_div2",
> +				    "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
> +PNAME(mout_cmu_tpu_tpu_p)	= { "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div3", "dout_shared1_div3",
> +				    "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_tpuctl_p)	= { "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div3", "dout_shared1_div3",
> +				    "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_bus_p)	= { "dout_shared0_div2", "dout_shared1_div2",
> +				    "fout_shared2_pll", "fout_shared3_pll",
> +				    "dout_shared0_div3", "dout_shared1_div3",
> +				    "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_uart_p)	= { "dout_shared0_div4", "dout_shared2_div2",
> +				    "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
> +PNAME(mout_cmu_bo_bus_p)	= { "fout_shared2_pll", "dout_shared0_div3",
> +				    "fout_shared3_pll", "dout_shared1_div3",
> +				    "dout_shared0_div4", "dout_shared1_div4",
> +				    "fout_spare_pll" };
> +
> +/* gs101 */
> +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> +	/* CMU_TOP_PURECLKCOMP */
> +	MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> +	    PLL_CON0_PLL_SHARED0, 4, 1),
> +	MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> +	    PLL_CON0_PLL_SHARED1, 4, 1),
> +	MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> +	    PLL_CON0_PLL_SHARED2, 4, 1),
> +	MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> +	    PLL_CON0_PLL_SHARED3, 4, 1),
> +	MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> +	    PLL_CON0_PLL_SPARE, 4, 1),
> +
> +	/* BUS0 */
> +	MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> +	MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> +
> +	/* BUS1 */
> +	MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> +
> +	/* BUS2 */
> +	MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> +
> +	/* CORE */
> +	MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> +	/* EH */
> +	MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> +	/* CPUCL{0,1,2,} */
> +	MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> +
> +	MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> +
> +	MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> +
> +	MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> +	    CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> +
> +	MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
> +
> +	/* G3D */
> +	MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
> +
> +	MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2),
> +
> +	MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2),
> +	/* DPU */
> +	MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2),
> +
> +	/* DISP */
> +	MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2),
> +
> +	/* G2D */
> +	MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
> +
> +	MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
> +
> +	/* HSI0 */
> +	MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2),
> +
> +	MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2),
> +
> +	MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
> +
> +	MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2),
> +
> +	/* HSI1 */
> +	MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2),
> +
> +	MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2),
> +	/* HSI2 */
> +	MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
> +
> +	MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
> +
> +	MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2),
> +
> +	MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2),
> +
> +	/* CSIS */
> +	MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
> +
> +	/* PDP */
> +	MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> +
> +	/* PDP */
> +	MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
> +
> +	/* IPP */
> +	MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> +
> +	/* G3AA */
> +	MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
> +
> +	/* ITP */
> +	MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
> +
> +	/* DNS */
> +	MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
> +
> +	/* TNR */
> +	MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
> +
> +	/* MCSC*/
> +	MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
> +
> +	MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
> +
> +	/* GDC */
> +	MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
> +
> +	MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
> +
> +	MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
> +
> +	/* MFC */
> +	MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
> +
> +	/* DDRPHY0/1/2/3 */
> +	MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
> +
> +	/* MIF0/1/2/3 */
> +	MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
> +
> +	/* MISC */
> +	MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
> +	MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
> +
> +	/* PERI0 */
> +	MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> +	MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> +	/* PERI1 */
> +	MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> +	MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> +
> +	/* TPU */
> +	MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
> +
> +	MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
> +
> +	MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
> +
> +	MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
> +
> +	/* BO */
> +	MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
> +};
> +
> +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
> +	/* CMU_TOP_PURECLKCOMP */
> +	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
> +	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> +	DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
> +	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> +	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
> +	    CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
> +	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
> +	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> +
> +	DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
> +	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> +	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
> +	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> +	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
> +	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> +
> +	DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
> +	    CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> +
> +	DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
> +	    CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
> +
> +	/* BUS0 */
> +	DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
> +	    CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
> +	DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
> +	    CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
> +
> +	/* BUS1 */
> +	DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
> +	    CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
> +
> +	/* BUS2 */
> +	DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
> +	    CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
> +
> +	/* CORE */
> +	DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
> +	    CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
> +
> +	/* EH */
> +	DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
> +	    CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
> +
> +	/* CPUCL{0,1,2,} */
> +	DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch",
> +	    CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
> +
> +	DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
> +	    CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
> +
> +	DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch",
> +	    CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
> +
> +	DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
> +	    CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
> +
> +	DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
> +	    CLK_CON_DIV_CLKCMU_HPM, 0, 2),
> +
> +	/* G3D */
> +	DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
> +	    CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
> +
> +	DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
> +	    CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
> +
> +	DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
> +	    CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
> +
> +	/* DPU */
> +	DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
> +	    CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
> +
> +	/* DISP */
> +	DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
> +	    CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
> +
> +	/* G2D */
> +	DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
> +	    CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
> +
> +	DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
> +	    CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
> +
> +	/* HSI0 */
> +	DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd",
> +	    CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
> +
> +	DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
> +	    CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
> +
> +	DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
> +	    CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
> +
> +	/* TODO register exists but all lower bits are reserved */
> +	DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg",
> +	    CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
> +
> +	/* HSI1 */
> +	DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
> +	    CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
> +
> +	DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
> +	    CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
> +	/* HSI2 */
> +	DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
> +	    CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
> +
> +	DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
> +	    CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
> +
> +	DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd",
> +	    CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
> +
> +	DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card",
> +	    CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
> +
> +	/* CSIS */
> +	DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
> +	    CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
> +
> +	/* PDP */
> +	DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
> +	    CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
> +
> +	DIV(CLK_DOUT_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",
> +	    CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
> +
> +	/* IPP */
> +	DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
> +	    CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
> +
> +	/* G3AA */
> +	DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa",
> +	    CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
> +
> +	/* ITP */
> +	DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
> +	    CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
> +
> +	/* DNS */
> +	DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
> +	    CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
> +
> +	/* TNR */
> +	DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
> +	    CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
> +
> +	/* MCSC*/
> +	DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
> +	    CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
> +
> +	DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
> +	    CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
> +
> +	/* GDC */
> +	DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
> +	    CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
> +
> +	DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
> +	    CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
> +
> +	DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
> +	    CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
> +
> +	/* MFC */
> +	DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
> +	    CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
> +
> +	/* MIF0/1/2/3 */
> +	DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
> +	    CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
> +
> +	/* MISC */
> +	DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
> +	    CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
> +	DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
> +	    CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
> +
> +	/* PERI0 */
> +	DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
> +	    CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
> +	DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
> +	    CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
> +
> +	/* PERI1 */
> +	DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
> +	    CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
> +	DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
> +	    CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
> +
> +	/* TPU */
> +	DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
> +	    CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
> +
> +	DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
> +	    CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
> +
> +	DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
> +	    CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
> +
> +	DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
> +	    CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
> +
> +	/* BO */
> +	DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
> +	    CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
> +
> +};
> +
> +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
> +	/* BUS0 */
> +	GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
> +
> +	/* BUS1 */
> +	GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
> +
> +	/* BUS2 */
> +	GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
> +
> +	/* CORE */
> +	GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
> +
> +	/* EH */
> +	GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
> +
> +	/* CPUCL{0,1,2,} */
> +	GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch",
> +	     CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
> +	     CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
> +	     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
> +	     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
> +	     CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
> +
> +	/* G3D */
> +	GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
> +	     CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
> +	     CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
> +	     CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
> +	/* DPU */
> +	GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
> +	/* DISP */
> +	GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
> +
> +	/* G2D */
> +	GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
> +	     CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
> +	     CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
> +	/* HSI0 */
> +	GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0),
> +	/* HSI1 */
> +	GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
> +	/* HSI2 */
> +	GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
> +	GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0),
> +	GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card",
> +	     CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0),
> +	/* CSIS */
> +	GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> +	/* PDP */
> +	GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
> +	     CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
> +	/* IPP */
> +	GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> +	/* G3AA */
> +	GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> +	     CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
> +
> +	/* ITP */
> +	GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
> +
> +	/* DNS */
> +	GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
> +
> +	/* TNR */
> +	GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
> +
> +	/* MCSC*/
> +	GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
> +	     CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
> +	     CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
> +
> +	/* GDC */
> +	GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
> +	     CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
> +	     CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
> +	     CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
> +
> +	/* MFC */
> +	GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
> +	     CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
> +
> +	/* DDRPHY0/1/2/3 */
> +	GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
> +	     CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
> +
> +	/* MIF0/1/2/3 */
> +	GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
> +	     CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost",
> +	     CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
> +
> +	/* MISC */
> +	GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
> +	GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
> +	     CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
> +
> +	/* PERI0 */
> +	GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
> +	GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
> +	     CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
> +
> +	/* PERI1 */
> +	GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
> +	GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
> +	     CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
> +
> +	/* TPU */
> +	GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
> +	     CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
> +	GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
> +	     CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
> +	GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
> +	GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
> +	     CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
> +
> +	/* BO */
> +	GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
> +
> +};
> +
> +static const struct samsung_cmu_info top_cmu_info __initconst = {
> +	.pll_clks		= cmu_top_pll_clks,
> +	.nr_pll_clks		= ARRAY_SIZE(cmu_top_pll_clks),
> +	.mux_clks		= cmu_top_mux_clks,
> +	.nr_mux_clks		= ARRAY_SIZE(cmu_top_mux_clks),
> +	.div_clks		= cmu_top_div_clks,
> +	.nr_div_clks		= ARRAY_SIZE(cmu_top_div_clks),
> +	.gate_clks		= cmu_top_gate_clks,
> +	.nr_gate_clks		= ARRAY_SIZE(cmu_top_gate_clks),
> +	.nr_clk_ids		= TOP_NR_CLK,
> +	.clk_regs		= cmu_top_clk_regs,
> +	.nr_clk_regs		= ARRAY_SIZE(cmu_top_clk_regs),
> +};
> +
> +static void __init gs101_cmu_top_init(struct device_node *np)
> +{
> +	exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
> +}
> +
> +/* Register CMU_TOP early, as it's a dependency for other early domains */
> +CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
> +	       gs101_cmu_top_init);
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 11/20] clk: samsung: clk-gs101: add CMU_APM support

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> This patch adds all the registers for the APM clock controller unit.
> 
> We register all the muxes and dividers, but only a few of the
> gates currently for PMU and GPIO.
> 
> One clock is marked CLK_IS_CRITICAL because the system
> hangs if this clock is disabled.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  drivers/clk/samsung/clk-gs101.c | 301 ++++++++++++++++++++++++++++++++
>  1 file changed, 301 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index e2c62754b1eb..525f95e60665 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -19,6 +19,7 @@
>  
>  /* NOTE: Must be equal to the last clock ID increased by one */
>  #define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
> +#define APM_NR_CLK                     (CLK_APM_PLL_DIV16_APM + 1)
>  
>  /* ---- CMU_TOP ------------------------------------------------------------- */
>  
> @@ -1549,3 +1550,303 @@ static void __init gs101_cmu_top_init(struct device_node *np)
>  /* Register CMU_TOP early, as it's a dependency for other early domains */
>  CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
>  	       gs101_cmu_top_init);
> +
> +/* ---- CMU_APM ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_APM (0x17400000) */
> +#define APM_CMU_APM_CONTROLLER_OPTION							0x0800
> +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0						0x0810
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC							0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC						0x1004
> +#define CLK_CON_DIV_DIV_CLK_APM_BOOST							0x1800
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART						0x1804
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI						0x1808
> +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART						0x180c
> +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK				0x2000
> +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1						0x2004
> +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1						0x2008
> +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1						0x200c
> +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC						0x2010
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK			0x2014
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK		0x2018
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK			0x201c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK				0x2020
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK				0x2024
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK			0x2028
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK			0x202c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK			0x2030
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK			0x2034
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK			0x2038
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK			0x203c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK				0x2040
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK				0x2044
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK			0x2048
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK				0x204c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK				0x2050
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK			0x2054
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK			0x2058
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK			0x205c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK			0x2060
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK			0x2064
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK		0x2068
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK			0x206c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK			0x2070
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK			0x2074
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK			0x207c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK			0x2080
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK			0x2084
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK			0x2088
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK			0x208c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK			0x2090
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK			0x2094
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK			0x2098
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK		0x209c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK		0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK		0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK				0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK			0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK				0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK				0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK			0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK			0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK	0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2			0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK				0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK				0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK				0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK			0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK			0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK				0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK				0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK			0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK			0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK				0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK				0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK				0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK				0x20fc
> +#define PCH_CON_LHM_AXI_G_SWD_PCH			0x3000
> +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH			0x3004
> +#define PCH_CON_LHM_AXI_P_APM_PCH			0x3008
> +#define PCH_CON_LHS_AXI_D_APM_PCH			0x300c
> +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH			0x3010
> +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH			0x3014
> +#define QCH_CON_APBIF_GPIO_ALIVE_QCH			0x3018
> +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH		0x301c
> +#define QCH_CON_APBIF_PMU_ALIVE_QCH			0x3020
> +#define QCH_CON_APBIF_RTC_QCH				0x3024
> +#define QCH_CON_APBIF_TRTC_QCH				0x3028
> +#define QCH_CON_APM_CMU_APM_QCH				0x302c
> +#define QCH_CON_APM_USI0_UART_QCH			0x3030
> +#define QCH_CON_APM_USI0_USI_QCH			0x3034
> +#define QCH_CON_APM_USI1_UART_QCH			0x3038
> +#define QCH_CON_D_TZPC_APM_QCH				0x303c
> +#define QCH_CON_GPC_APM_QCH				0x3040
> +#define QCH_CON_GREBEINTEGRATION_QCH_DBG		0x3044
> +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE		0x3048
> +#define QCH_CON_INTMEM_QCH				0x304c
> +#define QCH_CON_LHM_AXI_G_SWD_QCH			0x3050
> +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH			0x3054
> +#define QCH_CON_LHM_AXI_P_APM_QCH			0x3058
> +#define QCH_CON_LHS_AXI_D_APM_QCH			0x305c
> +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH			0x3060
> +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH			0x3064
> +#define QCH_CON_MAILBOX_APM_AOC_QCH			0x3068
> +#define QCH_CON_MAILBOX_APM_AP_QCH			0x306c
> +#define QCH_CON_MAILBOX_APM_GSA_QCH			0x3070
> +#define QCH_CON_MAILBOX_APM_SWD_QCH			0x3078
> +#define QCH_CON_MAILBOX_APM_TPU_QCH			0x307c
> +#define QCH_CON_MAILBOX_AP_AOC_QCH			0x3080
> +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH			0x3084
> +#define QCH_CON_PMU_INTR_GEN_QCH			0x3088
> +#define QCH_CON_ROM_CRC32_HOST_QCH			0x308c
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE		0x3090
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG	0x3094
> +#define QCH_CON_SPEEDY_APM_QCH				0x3098
> +#define QCH_CON_SPEEDY_SUB_APM_QCH			0x309c
> +#define QCH_CON_SSMT_D_APM_QCH				0x30a0
> +#define QCH_CON_SSMT_G_DBGCORE_QCH			0x30a4
> +#define QCH_CON_SS_DBGCORE_QCH_DBG			0x30a8
> +#define QCH_CON_SS_DBGCORE_QCH_GREBE			0x30ac
> +#define QCH_CON_SYSMMU_D_APM_QCH			0x30b0
> +#define QCH_CON_SYSREG_APM_QCH				0x30b8
> +#define QCH_CON_UASC_APM_QCH				0x30bc
> +#define QCH_CON_UASC_DBGCORE_QCH			0x30c0
> +#define QCH_CON_UASC_G_SWD_QCH				0x30c4
> +#define QCH_CON_UASC_P_AOCAPM_QCH			0x30c8
> +#define QCH_CON_UASC_P_APM_QCH				0x30cc
> +#define QCH_CON_WDT_APM_QCH				0x30d0
> +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM			0x3c00
> +
> +static const unsigned long apm_clk_regs[] __initconst = {
> +	APM_CMU_APM_CONTROLLER_OPTION,
> +	CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
> +	CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
> +	CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
> +	CLK_CON_DIV_DIV_CLK_APM_BOOST,
> +	CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
> +	CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
> +	CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
> +	CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
> +	CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
> +	CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
> +	CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
> +};
> +
> +PNAME(mout_apm_func_p)	= { "oscclk_apmgsa", "mout_apm_funcsrc", "pad_clk_apm" };
> +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
> +
> +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
> +	FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
> +	FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
> +	FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
> +};
> +
> +static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
> +	MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
> +	MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
> +};
> +
> +static const struct samsung_div_clock apm_div_clks[] __initconst = {
> +	DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
> +	    CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
> +	DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
> +	    CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
> +	DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
> +	    CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
> +	DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
> +	    CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
> +};
> +
> +static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
> +	GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
> +	     CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> +	     "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
> +	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +	GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> +	     "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
> +	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +	GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> +	     "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
> +	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> +	     21, CLK_IS_CRITICAL, 0),
> +
> +	GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> +	     "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
> +	     CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info apm_cmu_info __initconst = {
> +	.mux_clks		= apm_mux_clks,
> +	.nr_mux_clks		= ARRAY_SIZE(apm_mux_clks),
> +	.div_clks		= apm_div_clks,
> +	.nr_div_clks		= ARRAY_SIZE(apm_div_clks),
> +	.gate_clks		= apm_gate_clks,
> +	.nr_gate_clks		= ARRAY_SIZE(apm_gate_clks),
> +	.fixed_clks		= apm_fixed_clks,
> +	.nr_fixed_clks		= ARRAY_SIZE(apm_fixed_clks),
> +	.nr_clk_ids		= APM_NR_CLK,
> +	.clk_regs		= apm_clk_regs,
> +	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
> +};
> +
> +/* ---- platform_driver ----------------------------------------------------- */
> +
> +static int __init gs101_cmu_probe(struct platform_device *pdev)
> +{
> +	const struct samsung_cmu_info *info;
> +	struct device *dev = &pdev->dev;
> +
> +	info = of_device_get_match_data(dev);
> +	exynos_arm64_register_cmu(dev, dev->of_node, info);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id gs101_cmu_of_match[] = {
> +	{
> +		.compatible = "google,gs101-cmu-apm",
> +		.data = &apm_cmu_info,
> +	}, {
> +	},
> +};
> +
> +static struct platform_driver gs101_cmu_driver __refdata = {
> +	.driver	= {
> +		.name = "gs101-cmu",
> +		.of_match_table = gs101_cmu_of_match,
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe = gs101_cmu_probe,
> +};
> +
> +static int __init gs101_cmu_init(void)
> +{
> +	return platform_driver_register(&gs101_cmu_driver);
> +}
> +core_initcall(gs101_cmu_init);
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 12/20] clk: samsung: clk-gs101: Add support for CMU_MISC clock unit

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> CMU Misc clocks IPs such as Watchdog. Add support for the
> muxes, dividers and gates in this CMU.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  drivers/clk/samsung/clk-gs101.c | 312 ++++++++++++++++++++++++++++++++
>  1 file changed, 312 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 525f95e60665..bf2bd8cd39d0 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -20,6 +20,7 @@
>  /* NOTE: Must be equal to the last clock ID increased by one */
>  #define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
>  #define APM_NR_CLK                     (CLK_APM_PLL_DIV16_APM + 1)
> +#define MISC_NR_CLK                    (CLK_GOUT_MISC_WDT_CLUSTER1 + 1)
>  
>  /* ---- CMU_TOP ------------------------------------------------------------- */
>  
> @@ -1815,6 +1816,314 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
>  	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
>  };
>  
> +/* ---- CMU_MISC ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_MISC (0x10010000) */
> +#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER	0x0600
> +#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER	0x0604
> +#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER	0x0610
> +#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER	0x0614
> +#define MISC_CMU_MISC_CONTROLLER_OPTION		0x0800
> +#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0	0x0810
> +#define CLK_CON_MUX_MUX_CLK_MISC_GIC		0x1000
> +#define CLK_CON_DIV_DIV_CLK_MISC_BUSP		0x1800
> +#define CLK_CON_DIV_DIV_CLK_MISC_GIC		0x1804
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK		0x2000
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK		0x2004
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK		0x2008
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK		0x200c
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK	0x2010
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM		0x2014
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM		0x2018
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM		0x201c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A			0x2020
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK		0x2024
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK			0x2028
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK			0x202c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK	0x2030
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK		0x2034
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK		0x2038
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK		0x203c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK		0x2040
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK	0x2044
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK		0x2048
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK			0x204c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK		0x2050
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK		0x2054
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK		0x2058
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK			0x205c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK			0x2060
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK			0x2064
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK			0x2068
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK			0x206c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK			0x2070
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK			0x2074
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK			0x2078
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK			0x207c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK		0x2080
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK		0x2084
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK			0x2088
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK			0x208c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK			0x2090
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK			0x2094
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK			0x2098
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK			0x209c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK	0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK	0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK	0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK	0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK			0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK			0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK			0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK			0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK			0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK			0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK			0x20c8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK		0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK		0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK			0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK			0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK			0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK			0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK			0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK			0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK			0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK			0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2		0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1		0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK		0x20fc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK			0x2100
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK			0x2104
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK		0x2108
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK		0x210c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK			0x2110
> +#define DMYQCH_CON_PPMU_DMA_QCH			0x3000
> +#define DMYQCH_CON_PUF_QCH			0x3004
> +#define PCH_CON_LHM_AXI_D_SSS_PCH		0x300c
> +#define PCH_CON_LHM_AXI_P_GIC_PCH		0x3010
> +#define PCH_CON_LHM_AXI_P_MISC_PCH		0x3014
> +#define PCH_CON_LHS_ACEL_D_MISC_PCH		0x3018
> +#define PCH_CON_LHS_AST_IRI_GICCPU_PCH		0x301c
> +#define PCH_CON_LHS_AXI_D_SSS_PCH		0x3020
> +#define QCH_CON_ADM_AHB_SSS_QCH			0x3024
> +#define QCH_CON_DIT_QCH				0x3028
> +#define QCH_CON_GIC_QCH				0x3030
> +#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH		0x3038
> +#define QCH_CON_LHM_AXI_D_SSS_QCH		0x303c
> +#define QCH_CON_LHM_AXI_P_GIC_QCH		0x3040
> +#define QCH_CON_LHM_AXI_P_MISC_QCH		0x3044
> +#define QCH_CON_LHS_ACEL_D_MISC_QCH		0x3048
> +#define QCH_CON_LHS_AST_IRI_GICCPU_QCH		0x304c
> +#define QCH_CON_LHS_AXI_D_SSS_QCH		0x3050
> +#define QCH_CON_MCT_QCH				0x3054
> +#define QCH_CON_MISC_CMU_MISC_QCH		0x3058
> +#define QCH_CON_OTP_CON_BIRA_QCH		0x305c
> +#define QCH_CON_OTP_CON_BISR_QCH		0x3060
> +#define QCH_CON_OTP_CON_TOP_QCH			0x3064
> +#define QCH_CON_PDMA_QCH			0x3068
> +#define QCH_CON_PPMU_MISC_QCH			0x306c
> +#define QCH_CON_QE_DIT_QCH			0x3070
> +#define QCH_CON_QE_PDMA_QCH			0x3074
> +#define QCH_CON_QE_PPMU_DMA_QCH			0x3078
> +#define QCH_CON_QE_RTIC_QCH			0x307c
> +#define QCH_CON_QE_SPDMA_QCH			0x3080
> +#define QCH_CON_QE_SSS_QCH			0x3084
> +#define QCH_CON_RTIC_QCH			0x3088
> +#define QCH_CON_SPDMA_QCH			0x308c
> +#define QCH_CON_SSMT_DIT_QCH			0x3090
> +#define QCH_CON_SSMT_PDMA_QCH			0x3094
> +#define QCH_CON_SSMT_PPMU_DMA_QCH		0x3098
> +#define QCH_CON_SSMT_RTIC_QCH			0x309c
> +#define QCH_CON_SSMT_SPDMA_QCH			0x30a0
> +#define QCH_CON_SSMT_SSS_QCH			0x30a4
> +#define QCH_CON_SSS_QCH				0x30a8
> +#define QCH_CON_SYSMMU_MISC_QCH			0x30ac
> +#define QCH_CON_SYSMMU_SSS_QCH			0x30b0
> +#define QCH_CON_SYSREG_MISC_QCH			0x30b4
> +#define QCH_CON_TMU_SUB_QCH			0x30b8
> +#define QCH_CON_TMU_TOP_QCH			0x30bc
> +#define QCH_CON_WDT_CLUSTER0_QCH		0x30c0
> +#define QCH_CON_WDT_CLUSTER1_QCH		0x30c4
> +#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC	0x3c00
> +
> +static const unsigned long misc_clk_regs[] __initconst = {
> +	PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
> +	PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
> +	PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
> +	PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
> +	MISC_CMU_MISC_CONTROLLER_OPTION,
> +	CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
> +	CLK_CON_MUX_MUX_CLK_MISC_GIC,
> +	CLK_CON_DIV_DIV_CLK_MISC_BUSP,
> +	CLK_CON_DIV_DIV_CLK_MISC_GIC,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
> +	DMYQCH_CON_PPMU_DMA_QCH,
> +	DMYQCH_CON_PUF_QCH,
> +	PCH_CON_LHM_AXI_D_SSS_PCH,
> +	PCH_CON_LHM_AXI_P_GIC_PCH,
> +	PCH_CON_LHM_AXI_P_MISC_PCH,
> +	PCH_CON_LHS_ACEL_D_MISC_PCH,
> +	PCH_CON_LHS_AST_IRI_GICCPU_PCH,
> +	PCH_CON_LHS_AXI_D_SSS_PCH,
> +	QCH_CON_ADM_AHB_SSS_QCH,
> +	QCH_CON_DIT_QCH,
> +	QCH_CON_GIC_QCH,
> +	QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
> +	QCH_CON_LHM_AXI_D_SSS_QCH,
> +	QCH_CON_LHM_AXI_P_GIC_QCH,
> +	QCH_CON_LHM_AXI_P_MISC_QCH,
> +	QCH_CON_LHS_ACEL_D_MISC_QCH,
> +	QCH_CON_LHS_AST_IRI_GICCPU_QCH,
> +	QCH_CON_LHS_AXI_D_SSS_QCH,
> +	QCH_CON_MCT_QCH,
> +	QCH_CON_MISC_CMU_MISC_QCH,
> +	QCH_CON_OTP_CON_BIRA_QCH,
> +	QCH_CON_OTP_CON_BISR_QCH,
> +	QCH_CON_OTP_CON_TOP_QCH,
> +	QCH_CON_PDMA_QCH,
> +	QCH_CON_PPMU_MISC_QCH,
> +	QCH_CON_QE_DIT_QCH,
> +	QCH_CON_QE_PDMA_QCH,
> +	QCH_CON_QE_PPMU_DMA_QCH,
> +	QCH_CON_QE_RTIC_QCH,
> +	QCH_CON_QE_SPDMA_QCH,
> +	QCH_CON_QE_SSS_QCH,
> +	QCH_CON_RTIC_QCH,
> +	QCH_CON_SPDMA_QCH,
> +	QCH_CON_SSMT_DIT_QCH,
> +	QCH_CON_SSMT_PDMA_QCH,
> +	QCH_CON_SSMT_PPMU_DMA_QCH,
> +	QCH_CON_SSMT_RTIC_QCH,
> +	QCH_CON_SSMT_SPDMA_QCH,
> +	QCH_CON_SSMT_SSS_QCH,
> +	QCH_CON_SSS_QCH,
> +	QCH_CON_SYSMMU_MISC_QCH,
> +	QCH_CON_SYSMMU_SSS_QCH,
> +	QCH_CON_SYSREG_MISC_QCH,
> +	QCH_CON_TMU_SUB_QCH,
> +	QCH_CON_TMU_TOP_QCH,
> +	QCH_CON_WDT_CLUSTER0_QCH,
> +	QCH_CON_WDT_CLUSTER1_QCH,
> +	QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_MISC */
> +PNAME(mout_misc_bus_user_p)		= { "oscclk", "dout_cmu_misc_bus" };
> +PNAME(mout_misc_sss_user_p)		= { "oscclk", "dout_cmu_misc_sss" };
> +
> +static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
> +	MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
> +	    PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
> +	MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
> +	    PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
> +};
> +
> +static const struct samsung_div_clock misc_div_clks[] __initconst = {
> +	DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
> +	    CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
> +	DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
> +	    CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
> +};
> +
> +static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
> +	GATE(CLK_GOUT_MISC_PCLK, "gout_misc_pclk", "dout_misc_busp",
> +	     CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +	GATE(CLK_GOUT_MISC_SYSREG_PCLK, "gout_misc_sysreg_pclk", "dout_misc_busp",
> +	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +	GATE(CLK_GOUT_MISC_WDT_CLUSTER0, "gout_misc_wdt_cluster0", "dout_misc_busp",
> +	     CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +	GATE(CLK_GOUT_MISC_WDT_CLUSTER1, "gout_misc_wdt_cluster1", "dout_misc_busp",
> +	     CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +};
> +
> +static const struct samsung_cmu_info misc_cmu_info __initconst = {
> +	.mux_clks		= misc_mux_clks,
> +	.nr_mux_clks		= ARRAY_SIZE(misc_mux_clks),
> +	.div_clks		= misc_div_clks,
> +	.nr_div_clks		= ARRAY_SIZE(misc_div_clks),
> +	.gate_clks		= misc_gate_clks,
> +	.nr_gate_clks		= ARRAY_SIZE(misc_gate_clks),
> +	.nr_clk_ids		= MISC_NR_CLK,
> +	.clk_regs		= misc_clk_regs,
> +	.nr_clk_regs		= ARRAY_SIZE(misc_clk_regs),
> +	.clk_name		= "dout_misc_bus",
> +};
> +
>  /* ---- platform_driver ----------------------------------------------------- */
>  
>  static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -1832,6 +2141,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
>  	{
>  		.compatible = "google,gs101-cmu-apm",
>  		.data = &apm_cmu_info,
> +	}, {
> +		.compatible = "google,gs101-cmu-misc",
> +		.data = &misc_cmu_info,
>  	}, {
>  	},
>  };
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 13/20] pinctrl: samsung: Add filter selection support for alive banks

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Newer Exynos SoCs have a filter selection register on alive bank pins.
> This allows the selection of a digital or delay filter for each pin. If
> the filter selection register is not available then the default filter
> (digital) is applied.
> 
> On suspend we apply the analog filter to all pins in the bank, and on
> resume the digital filter is reapplied to all pins in the bank.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c  | 82 ++++++++++++++++++++++-
>  drivers/pinctrl/samsung/pinctrl-exynos.h  |  7 ++
>  drivers/pinctrl/samsung/pinctrl-samsung.c |  2 +
>  drivers/pinctrl/samsung/pinctrl-samsung.h | 23 +++++++
>  4 files changed, 113 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index a8212fc126bf..800831aa8357 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -269,6 +269,68 @@ struct exynos_eint_gpio_save {
>  	u32 eint_mask;
>  };
>  
> +static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d,
> +				   struct samsung_pin_bank *bank, int filter)
> +{
> +	unsigned int flt_reg, flt_con = 0;
> +	unsigned int val, shift;
> +	int i;
> +	int loop_cnt;
> +
> +	/*
> +	 * This function sets the desired filter (digital or delay) to
> +	 * every pin in the bank. Note the filter selection bitfield is
> +	 * only found on alive banks. The FLTCON register has the
> +	 * following layout
> +	 *
> +	 * BitfieldName[PinNum][Bit:Bit]
> +	 *
> +	 * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
> +	 * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
> +	 * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
> +	 * FLT_EN[0][7]  FLT_SEL[0][6]  FLT_WIDTH[0][5:0]
> +	 */
> +
> +	flt_con |= EXYNOS9_FLTCON_EN;
> +
> +	if (filter)
> +		flt_con |= EXYNOS9_FLTCON_SEL_DIGITAL;
> +
> +	flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
> +
> +	if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN)
> +		/*
> +		 * if nr_pins > 4, we should set FLTCON0 register fully.
> +		 * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
> +		 */
> +		loop_cnt = EXYNOS9_FLTCON_NR_PIN;
> +	else
> +		loop_cnt = bank->nr_pins;
> +
> +	val = readl(d->virt_base + flt_reg);
> +
> +	for (i = 0; i < loop_cnt; i++) {
> +		shift = i * EXYNOS9_FLTCON_LEN;
> +		val &= ~(EXYNOS9_FLTCON_MASK << shift);
> +		val |= (flt_con << shift);
> +	}
> +
> +	writel(val, d->virt_base + flt_reg);
> +
> +	/* loop for FLTCON1 pin 4 ~ 7 */
> +	if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) {
> +		val = readl(d->virt_base + flt_reg + 0x4);
> +		loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN);
> +
> +		for (i = 0; i < loop_cnt; i++) {
> +			shift = i * EXYNOS9_FLTCON_LEN;
> +			val &= ~(EXYNOS9_FLTCON_MASK << shift);
> +			val |= (flt_con << shift);
> +		}
> +		writel(val, d->virt_base + flt_reg + 0x4);
> +	}
> +}
> +
>  /*
>   * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
>   * @d: driver data of samsung pinctrl driver.
> @@ -321,6 +383,9 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
>  			goto err_domains;
>  		}
>  
> +		/* Set Delay Analog Filter */
> +		if (bank->fltcon_type != FLT_DEFAULT)
> +			exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DELAY);
>  	}
>  
>  	return 0;
> @@ -555,6 +620,10 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
>  		if (bank->eint_type != EINT_TYPE_WKUP)
>  			continue;
>  
> +		/* Set Digital Filter */
> +		if (bank->fltcon_type != FLT_DEFAULT)
> +			exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DIGITAL);
> +
>  		bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
>  					      GFP_KERNEL);
>  		if (!bank->irq_chip) {
> @@ -658,6 +727,7 @@ static void exynos_pinctrl_suspend_bank(
>  void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
>  {
>  	struct samsung_pin_bank *bank = drvdata->pin_banks;
> +	struct samsung_pinctrl_drv_data *d = bank->drvdata;
>  	struct exynos_irq_chip *irq_chip = NULL;
>  	int i;
>  
> @@ -665,6 +735,9 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
>  		if (bank->eint_type == EINT_TYPE_GPIO)
>  			exynos_pinctrl_suspend_bank(drvdata, bank);
>  		else if (bank->eint_type == EINT_TYPE_WKUP) {
> +			/* Setting Delay (Analog) Filter */
> +			if (bank->fltcon_type != FLT_DEFAULT)
> +				exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DELAY);
>  			if (!irq_chip) {
>  				irq_chip = bank->irq_chip;
>  				irq_chip->set_eint_wakeup_mask(drvdata,
> @@ -707,11 +780,18 @@ static void exynos_pinctrl_resume_bank(
>  void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
>  {
>  	struct samsung_pin_bank *bank = drvdata->pin_banks;
> +	struct samsung_pinctrl_drv_data *d = bank->drvdata;
>  	int i;
>  
>  	for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
> -		if (bank->eint_type == EINT_TYPE_GPIO)
> +		if (bank->eint_type == EINT_TYPE_GPIO) {
>  			exynos_pinctrl_resume_bank(drvdata, bank);
> +		} else if (bank->eint_type == EINT_TYPE_WKUP ||
> +			bank->eint_type == EINT_TYPE_WKUP_MUX) {
> +			/* Set Digital Filter */
> +			if (bank->fltcon_type != FLT_DEFAULT)
> +				exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DIGITAL);
> +		}
>  }
>  
>  static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 7bd6d82c9f36..63b2426ad5d6 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -50,6 +50,13 @@
>  
>  #define EXYNOS_EINT_MAX_PER_BANK	8
>  #define EXYNOS_EINT_NR_WKUP_EINT
> +/* EINT filter configuration */
> +#define EXYNOS9_FLTCON_EN		BIT(7)
> +#define EXYNOS9_FLTCON_SEL_DIGITAL	BIT(6)
> +#define EXYNOS9_FLTCON_SEL_DELAY	0
> +#define EXYNOS9_FLTCON_MASK		0xff
> +#define EXYNOS9_FLTCON_LEN		8
> +#define EXYNOS9_FLTCON_NR_PIN		4
>  
>  #define EXYNOS_PIN_BANK_EINTN(pins, reg, id)		\
>  	{						\
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index e54847040b4a..449f8109d8b5 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1104,6 +1104,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
>  		bank->eint_func = bdata->eint_func;
>  		bank->eint_type = bdata->eint_type;
>  		bank->eint_mask = bdata->eint_mask;
> +		bank->fltcon_type = bdata->fltcon_type;
> +		bank->fltcon_offset = bdata->fltcon_offset;
>  		bank->eint_offset = bdata->eint_offset;
>  		bank->name = bdata->name;
>  
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index 9af93e3d8d9f..de2ca8e8b378 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -82,6 +82,21 @@ enum eint_type {
>  	EINT_TYPE_WKUP_MUX,
>  };
>  
> +/**
> + * enum fltcon_type - filter selection
> + * @FLT_DEFAULT: filter not selectable, default digital filter
> + * @FLT_SELECT: filter selectable (digital or delay)
> + *
> + * Some banks on some SoCs (gs101 and possibly others) have a selectable
> + * filter on alive banks of 'delay/analog' or 'digital'. If the filter
> + * selection is not available then the default filter is used (digital).
> + */
> +
> +enum fltcon_type {
> +	FLT_DEFAULT,
> +	FLT_SELECTABLE,
> +};
> +
>  /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
>  #define PIN_NAME_LENGTH	10
>  
> @@ -122,6 +137,8 @@ struct samsung_pin_bank_type {
>   * @eint_type: type of the external interrupt supported by the bank.
>   * @eint_mask: bit mask of pins which support EINT function.
>   * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
> + * @fltcon_type: whether the filter (delay/digital) is selectable
> + * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
>   * @name: name to be prefixed for each pin in this pin bank.
>   */
>  struct samsung_pin_bank_data {
> @@ -133,6 +150,8 @@ struct samsung_pin_bank_data {
>  	enum eint_type	eint_type;
>  	u32		eint_mask;
>  	u32		eint_offset;
> +	enum fltcon_type fltcon_type;
> +	u32		fltcon_offset;
>  	const char	*name;
>  };
>  
> @@ -147,6 +166,8 @@ struct samsung_pin_bank_data {
>   * @eint_type: type of the external interrupt supported by the bank.
>   * @eint_mask: bit mask of pins which support EINT function.
>   * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
> + * @fltcon_type: whether the filter (delay/digital) is selectable
> + * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
>   * @name: name to be prefixed for each pin in this pin bank.
>   * @pin_base: starting pin number of the bank.
>   * @soc_priv: per-bank private data for SoC-specific code.
> @@ -169,6 +190,8 @@ struct samsung_pin_bank {
>  	enum eint_type	eint_type;
>  	u32		eint_mask;
>  	u32		eint_offset;
> +	enum fltcon_type fltcon_type;
> +	u32		fltcon_offset;
>  	const char	*name;
>  
>  	u32		pin_base;
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 14/20] pinctrl: samsung: Add gs101 SoC pinctrl configuration

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Add support for the pin-controller found on the gs101 SoC used in
> Pixel 6 phones.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 163 ++++++++++++++++++
>  drivers/pinctrl/samsung/pinctrl-exynos.c      |   2 +
>  drivers/pinctrl/samsung/pinctrl-exynos.h      |  34 ++++
>  drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
>  drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
>  5 files changed, 202 insertions(+)
> 
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index cb965cf93705..db47001d1b35 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
>  	.ctrl		= fsd_pin_ctrl,
>  	.num_ctrl	= ARRAY_SIZE(fsd_pin_ctrl),
>  };
> +
> +/*
> + * bank type for non-alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> + */
> +static struct samsung_pin_bank_type gs101_bank_type_off  = {
> +	.fld_width = { 4, 1, 4, 4, 2, 4, },
> +	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> +};
> +
> +/*
> + * bank type for alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + */
> +static const struct samsung_pin_bank_type gs101_bank_type_alive = {
> +	.fld_width = { 4, 1, 4, 4, },
> +	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> +};
> +
> +/* pin banks of gs101 pin-controller (ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACORE) */
> +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACTRL) */
> +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC0) */
> +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC1) */
> +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI1) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI2) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> +	{
> +		/* pin banks of gs101 pin-controller (ALIVE) */
> +		.pin_banks	= gs101_pin_alive,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_alive),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.eint_wkup_init = exynos_eint_wkup_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +		.pin_banks	= gs101_pin_far_alive,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_far_alive),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.eint_wkup_init = exynos_eint_wkup_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (GSACORE) */
> +		.pin_banks	= gs101_pin_gsacore,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_gsacore),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +	}, {
> +		/* pin banks of gs101 pin-controller (GSACTRL) */
> +		.pin_banks	= gs101_pin_gsactrl,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_gsactrl),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +	}, {
> +		/* pin banks of gs101 pin-controller (PERIC0) */
> +		.pin_banks	= gs101_pin_peric0,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_peric0),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (PERIC1) */
> +		.pin_banks	= gs101_pin_peric1,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_peric1),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume	= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (HSI1) */
> +		.pin_banks	= gs101_pin_hsi1,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_hsi1),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (HSI2) */
> +		.pin_banks	= gs101_pin_hsi2,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_hsi2),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	},
> +};
> +
> +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> +	.ctrl		= gs101_pin_ctrl,
> +	.num_ctrl	= ARRAY_SIZE(gs101_pin_ctrl),
> +};
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index 800831aa8357..014f0c37f97f 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -533,6 +533,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
>  			.data = &exynos7_wkup_irq_chip },
>  	{ .compatible = "samsung,exynosautov9-wakeup-eint",
>  			.data = &exynos7_wkup_irq_chip },
> +	{ .compatible = "google,gs101-wakeup-eint",
> +			.data = &exynos7_wkup_irq_chip },
>  	{ }
>  };
>  
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 63b2426ad5d6..0dd013654bd2 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -147,6 +147,40 @@
>  		.name		= id				\
>  	}
>  
> +#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id)	\
> +	{						\
> +		.type		= &types,		\
> +		.pctl_offset	= reg,			\
> +		.nr_pins	= pins,			\
> +		.eint_type	= EINT_TYPE_NONE,	\
> +		.fltcon_type	= FLT_DEFAULT		\
> +		.name		= id			\
> +	}
> +
> +#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> +	{						\
> +		.type		= &types,		\
> +		.pctl_offset	= reg,			\
> +		.nr_pins	= pins,			\
> +		.eint_type	= EINT_TYPE_GPIO,	\
> +		.eint_offset	= offs,			\
> +		.fltcon_type    = fltcontype,		\
> +		.fltcon_offset	= fltcon_offs,		\
> +		.name		= id			\
> +	}
> +
> +#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> +	{						\
> +		.type		= &types,		\
> +		.pctl_offset	= reg,			\
> +		.nr_pins	= pins,			\
> +		.eint_type	= EINT_TYPE_WKUP,	\
> +		.eint_offset	= offs,			\
> +		.fltcon_type    = fltcontype,		\
> +		.fltcon_offset	= fltcon_offs,		\
> +		.name		= id			\
> +	}
> +
>  /**
>   * struct exynos_weint_data: irq specific data for all the wakeup interrupts
>   * generated by the external wakeup interrupt controller.
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 449f8109d8b5..12176f98440d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
>  		.data = &exynosautov9_of_data },
>  	{ .compatible = "tesla,fsd-pinctrl",
>  		.data = &fsd_of_data },
> +	{ .compatible = "google,gs101-pinctrl",
> +		.data = &gs101_of_data },
>  #endif
>  #ifdef CONFIG_PINCTRL_S3C64XX
>  	{ .compatible = "samsung,s3c64xx-pinctrl",
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index de2ca8e8b378..e62e909fb10d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -374,6 +374,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
>  extern const struct samsung_pinctrl_of_match_data fsd_of_data;
> +extern const struct samsung_pinctrl_of_match_data gs101_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 14/20] pinctrl: samsung: Add gs101 SoC pinctrl configuration

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Add support for the pin-controller found on the gs101 SoC used in
> Pixel 6 phones.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 163 ++++++++++++++++++
>  drivers/pinctrl/samsung/pinctrl-exynos.c      |   2 +
>  drivers/pinctrl/samsung/pinctrl-exynos.h      |  34 ++++
>  drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
>  drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
>  5 files changed, 202 insertions(+)
> 
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index cb965cf93705..db47001d1b35 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
>  	.ctrl		= fsd_pin_ctrl,
>  	.num_ctrl	= ARRAY_SIZE(fsd_pin_ctrl),
>  };
> +
> +/*
> + * bank type for non-alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> + */
> +static struct samsung_pin_bank_type gs101_bank_type_off  = {
> +	.fld_width = { 4, 1, 4, 4, 2, 4, },
> +	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> +};
> +
> +/*
> + * bank type for alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + */
> +static const struct samsung_pin_bank_type gs101_bank_type_alive = {
> +	.fld_width = { 4, 1, 4, 4, },
> +	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> +};
> +
> +/* pin banks of gs101 pin-controller (ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACORE) */
> +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACTRL) */
> +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> +	EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC0) */
> +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC1) */
> +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI1) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI2) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> +	EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> +	{
> +		/* pin banks of gs101 pin-controller (ALIVE) */
> +		.pin_banks	= gs101_pin_alive,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_alive),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.eint_wkup_init = exynos_eint_wkup_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +		.pin_banks	= gs101_pin_far_alive,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_far_alive),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.eint_wkup_init = exynos_eint_wkup_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (GSACORE) */
> +		.pin_banks	= gs101_pin_gsacore,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_gsacore),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +	}, {
> +		/* pin banks of gs101 pin-controller (GSACTRL) */
> +		.pin_banks	= gs101_pin_gsactrl,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_gsactrl),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +	}, {
> +		/* pin banks of gs101 pin-controller (PERIC0) */
> +		.pin_banks	= gs101_pin_peric0,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_peric0),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (PERIC1) */
> +		.pin_banks	= gs101_pin_peric1,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_peric1),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume	= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (HSI1) */
> +		.pin_banks	= gs101_pin_hsi1,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_hsi1),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	}, {
> +		/* pin banks of gs101 pin-controller (HSI2) */
> +		.pin_banks	= gs101_pin_hsi2,
> +		.nr_banks	= ARRAY_SIZE(gs101_pin_hsi2),
> +		.eint_gpio_init = exynos_eint_gpio_init,
> +		.suspend	= exynos_pinctrl_suspend,
> +		.resume		= exynos_pinctrl_resume,
> +	},
> +};
> +
> +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> +	.ctrl		= gs101_pin_ctrl,
> +	.num_ctrl	= ARRAY_SIZE(gs101_pin_ctrl),
> +};
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index 800831aa8357..014f0c37f97f 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -533,6 +533,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
>  			.data = &exynos7_wkup_irq_chip },
>  	{ .compatible = "samsung,exynosautov9-wakeup-eint",
>  			.data = &exynos7_wkup_irq_chip },
> +	{ .compatible = "google,gs101-wakeup-eint",
> +			.data = &exynos7_wkup_irq_chip },
>  	{ }
>  };
>  
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 63b2426ad5d6..0dd013654bd2 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -147,6 +147,40 @@
>  		.name		= id				\
>  	}
>  
> +#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id)	\
> +	{						\
> +		.type		= &types,		\
> +		.pctl_offset	= reg,			\
> +		.nr_pins	= pins,			\
> +		.eint_type	= EINT_TYPE_NONE,	\
> +		.fltcon_type	= FLT_DEFAULT		\
> +		.name		= id			\
> +	}
> +
> +#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> +	{						\
> +		.type		= &types,		\
> +		.pctl_offset	= reg,			\
> +		.nr_pins	= pins,			\
> +		.eint_type	= EINT_TYPE_GPIO,	\
> +		.eint_offset	= offs,			\
> +		.fltcon_type    = fltcontype,		\
> +		.fltcon_offset	= fltcon_offs,		\
> +		.name		= id			\
> +	}
> +
> +#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> +	{						\
> +		.type		= &types,		\
> +		.pctl_offset	= reg,			\
> +		.nr_pins	= pins,			\
> +		.eint_type	= EINT_TYPE_WKUP,	\
> +		.eint_offset	= offs,			\
> +		.fltcon_type    = fltcontype,		\
> +		.fltcon_offset	= fltcon_offs,		\
> +		.name		= id			\
> +	}
> +
>  /**
>   * struct exynos_weint_data: irq specific data for all the wakeup interrupts
>   * generated by the external wakeup interrupt controller.
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 449f8109d8b5..12176f98440d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
>  		.data = &exynosautov9_of_data },
>  	{ .compatible = "tesla,fsd-pinctrl",
>  		.data = &fsd_of_data },
> +	{ .compatible = "google,gs101-pinctrl",
> +		.data = &gs101_of_data },
>  #endif
>  #ifdef CONFIG_PINCTRL_S3C64XX
>  	{ .compatible = "samsung,s3c64xx-pinctrl",
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index de2ca8e8b378..e62e909fb10d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -374,6 +374,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
>  extern const struct samsung_pinctrl_of_match_data fsd_of_data;
> +extern const struct samsung_pinctrl_of_match_data gs101_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Add serial driver data for Google Tensor gs101 SoC.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  drivers/tty/serial/samsung_tty.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index 07fb8a9dac63..26bc52e681a4 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -2597,14 +2597,22 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
>  	.fifosize = { 256, 64, 64, 64 },
>  };
>  
> +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> +	EXYNOS_COMMON_SERIAL_DRV_DATA(),
> +	/* rely on samsung,uart-fifosize DT property for fifosize */
> +	.fifosize = { 0 },
> +};
> +
>  #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
>  #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
>  #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
> +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
>  
>  #else
>  #define EXYNOS4210_SERIAL_DRV_DATA NULL
>  #define EXYNOS5433_SERIAL_DRV_DATA NULL
>  #define EXYNOS850_SERIAL_DRV_DATA NULL
> +#define GS101_SERIAL_DRV_DATA NULL
>  #endif
>  
>  #ifdef CONFIG_ARCH_APPLE
> @@ -2688,6 +2696,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
>  	}, {
>  		.name		= "artpec8-uart",
>  		.driver_data	= (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
> +	}, {
> +		.name		= "gs101-uart",
> +		.driver_data	= (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
>  	},
>  	{ },
>  };
> @@ -2709,6 +2720,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
>  		.data = EXYNOS850_SERIAL_DRV_DATA },
>  	{ .compatible = "axis,artpec8-uart",
>  		.data = ARTPEC8_SERIAL_DRV_DATA },
> +	{ .compatible = "google,gs101-uart",
> +		.data =  GS101_SERIAL_DRV_DATA },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> phones. It features:
> * 4xA55 little cluster
> * 2xA76 Mid cluster
> * 2xX1 Big cluster
> 
> This commit adds the basic device tree for gs101 (SoC).
> Further platform support will be added over time.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  arch/arm64/Kconfig.platforms                  |    6 +
>  arch/arm64/boot/dts/Makefile                  |    1 +
>  arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 +++++++++++++++++
>  arch/arm64/boot/dts/google/gs101-pinctrl.h    |   32 +
>  arch/arm64/boot/dts/google/gs101.dtsi         |  504 +++++++
>  5 files changed, 1818 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
>  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
>  create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
> 
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 6069120199bb..a5ed1b719488 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
>  	help
>  	  This enables support for ARMv8 based Samsung Exynos SoC family.
>  
> +config ARCH_GOOGLE_TENSOR
> +	bool "Google Tensor SoC fmaily"
> +	depends on ARCH_EXYNOS
> +	help
> +	  Support for ARMv8 based Google Tensor platforms.
> +
>  config ARCH_SPARX5
>  	bool "Microchip Sparx5 SoC family"
>  	select PINCTRL
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..a4ee7b628114 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -13,6 +13,7 @@ subdir-y += broadcom
>  subdir-y += cavium
>  subdir-y += exynos
>  subdir-y += freescale
> +subdir-y += google
>  subdir-y += hisilicon
>  subdir-y += intel
>  subdir-y += lg
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> new file mode 100644
> index 000000000000..ba88000c3ed8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> @@ -0,0 +1,1275 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include "gs101-pinctrl.h"
> +
> +/* GPIO_ALIVE */
> +&pinctrl_0 {
> +	gpa0: gpa0-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa1: gpa1-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa2: gpa2-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa3: gpa3-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa4: gpa4-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa5: gpa5-gpio-bank  {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa9: gpa9-gpio-bank  {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa10: gpa10-gpio-bank  {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	uart15_bus: uart15-bus-pins {
> +	       samsung,pins = "gpa2-3", "gpa2-4";
> +	       samsung,pin-function = <2>;
> +	       samsung,pin-pud = <0>;
> +	};
> +
> +	uart16_bus: uart16-bus-pins {
> +	       samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> +	       samsung,pin-function = <GS101_PIN_FUNC_2>;
> +	       samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +	};
> +
> +	uart16_bus_rts: uart1-bus-rts-pins {
> +		samsung,pins = "gpa3-2";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-val = <1>;
> +	};
> +
> +	uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
> +		samsung,pins = "gpa3-1";
> +		samsung,pin-val = <1>;
> +	};
> +
> +	uart16_bus_tx_con: uart1-bus-tx-con-pins {
> +		samsung,pins = "gpa3-1";
> +		samsung,pin-function = <1>;
> +	};
> +
> +	uart17_bus: uart17-bus-pins {
> +	       samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
> +	       samsung,pin-function = <2>;
> +	       samsung,pin-pud = <0>;
> +	};
> +
> +	spi15_bus: spi15-bus-pins {
> +		samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi15_cs: spi15-cs-pins {
> +		samsung,pins = "gpa4-3";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +};
> +
> +/* GPIO_FAR_ALIVE */
> +&pinctrl_1 {
> +	gpa6: gpa6-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa7: gpa7-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa8: gpa8-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	gpa11: gpa11-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +};
> +
> +/* GPIO_GSACORE */
> +&pinctrl_2 {
> +	gps0: gps0-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gps1: gps1-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gps2: gps2-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +};
> +
> +/* GPIO_GSACTRL */
> +&pinctrl_3 {
> +	gps3: gps3-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +};
> +
> +/* GPIO_HSI1 */
> +&pinctrl_6 {
> +	gph0: gph0-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gph1: gph1-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	pcie0_clkreq: pcie0-clkreq-pins{
> +		samsung,pins = "gph0-1";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <3>;
> +		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +		samsung,pin-con-pdn = <3>;
> +		samsung,pin-pud-pdn = <3>;
> +	};
> +
> +	pcie0_perst: pcie0-perst-pins {
> +		samsung,pins = "gph0-0";
> +		samsung,pin-function = <1>;
> +		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +		samsung,pin-con-pdn = <3>;
> +	};
> +};
> +
> +/* GPIO_HSI2 */
> +&pinctrl_7 {
> +	gph2: gph2-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gph3: gph3-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gph4: gph4-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	sd2_clk: sd2-clk-pins {
> +		samsung,pins = "gph4-0";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +	};
> +
> +	sd2_cmd: sd2-cmd-pins {
> +		samsung,pins = "gph4-1";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <3>;
> +		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +	};
> +
> +	sd2_bus1: sd2-bus-width1-pins {
> +		samsung,pins = "gph4-2";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <3>;
> +		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +	};
> +
> +	sd2_bus4: sd2-bus-width4-pins {
> +		samsung,pins = "gph4-3", "gph4-4", "gph4-5";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <3>;
> +		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
> +		samsung,pins = "gph4-0";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
> +		samsung,pins = "gph4-0";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
> +		samsung,pins = "gph4-0";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +	};
> +
> +	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
> +		samsung,pins = "gph4-0";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +	};
> +
> +	ufs_rst_n: ufs-rst-n-pins {
> +		samsung,pins = "gph3-1";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-con-pdn = <3>;
> +		samsung,pin-pud-pdn = <0>;
> +	};
> +
> +	ufs_refclk_out: ufs-refclk-out-pins {
> +		samsung,pins = "gph3-0";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-con-pdn = <3>;
> +		samsung,pin-pud-pdn = <0>;
> +	};
> +
> +	pcie1_clkreq: pcie1-clkreq-pins {
> +		samsung,pins = "gph2-1";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <3>;
> +		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +		samsung,pin-con-pdn = <3>;
> +		samsung,pin-pud-pdn = <3>;
> +	};
> +
> +	pcie1_perst: pcie1-perst-pins {
> +		samsung,pins = "gph2-0";
> +		samsung,pin-function = <1>;
> +		samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +		samsung,pin-con-pdn = <3>;
> +	};
> +};
> +
> +/* GPIO_PERIC0 */
> +&pinctrl_4 {
> +	gpp0: gpp0-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp1: gpp1-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp2: gpp2-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp3: gpp3-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp4: gpp4-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp5: gpp5-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp6: gpp6-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp7: gpp7-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp8: gpp8-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp9: gpp9-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp10: gpp10-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp11: gpp11-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp12: gpp12-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp13: gpp13-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp14: gpp14-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp15: gpp15-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp16: gpp16-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp17: gpp17-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp18: gpp18-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp19: gpp19-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	/* USI_PERIC0_UART_DBG */
> +	uart0_bus: uart0-bus-pins {
> +		samsung,pins = "gpp1-2", "gpp1-3";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	disp_te_pri_on: disp-te-pri-on-pins {
> +		samsung,pins = "gpp0-3";
> +		samsung,pin-function = <0xf>;
> +	};
> +
> +	disp_te_pri_off: disp-te-pri-off-pins {
> +		samsung,pins = "gpp0-3";
> +		samsung,pin-function = <0>;
> +	};
> +
> +	disp_te_sec_on: disp-te-sec-on-pins {
> +		samsung,pins = "gpp0-4";
> +		samsung,pin-function = <0xf>;
> +	};
> +
> +	disp_te_sec_off: disp-te-sec-off-pins {
> +		samsung,pins = "gpp0-4";
> +		samsung,pin-function = <0>;
> +	};
> +
> +	sensor_mclk1_out: sensor-mclk1-out-pins {
> +		samsung,pins = "gpp3-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk1_fn: sensor-mclk1-fn-pins {
> +		samsung,pins = "gpp3-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk2_out: sensor-mclk2-out-pins {
> +		samsung,pins = "gpp5-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk2_fn: sensor-mclk2-fn-pins {
> +		samsung,pins = "gpp5-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk3_out: sensor-mclk3-out-pins {
> +		samsung,pins = "gpp7-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk3_fn: sensor-mclk3-fn-pins {
> +		samsung,pins = "gpp7-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk4_out: sensor-mclk4-out-pins {
> +		samsung,pins = "gpp9-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk4_fn: sensor-mclk4-fn-pins {
> +		samsung,pins = "gpp9-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk5_out: sensor-mclk5-out-pins {
> +		samsung,pins = "gpp11-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk5_fn: sensor-mclk5-fn-pins {
> +		samsung,pins = "gpp11-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk6_out: sensor-mclk6-out-pins {
> +		samsung,pins = "gpp13-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk6_fn: sensor-mclk6-fn-pins {
> +		samsung,pins = "gpp13-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk7_out: sensor-mclk7-out-pins {
> +		samsung,pins = "gpp15-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk7_fn: sensor-mclk7-fn-pins {
> +		samsung,pins = "gpp15-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk8_out: sensor-mclk8-out-pins {
> +		samsung,pins = "gpp17-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	sensor_mclk8_fn: sensor-mclk8-fn-pins {
> +		samsung,pins = "gpp17-0";
> +		samsung,pin-function = <GS101_PIN_FUNC_2>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +	};
> +
> +	hsi2c14_bus: hsi2c14-bus-pins {
> +		samsung,pins = "gpp18-0", "gpp18-1";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart14_bus_single: uart14-bus-pins {
> +		samsung,pins = "gpp18-0", "gpp18-1",
> +			       "gpp18-2", "gpp18-3";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi14_bus: spi14-bus-pins {
> +		samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi14_cs: spi14-cs-pins {
> +		samsung,pins = "gpp18-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi14_cs_func: spi14-cs-func-pins {
> +		samsung,pins = "gpp18-3";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c8_bus: hsi2c8-bus-pins {
> +		samsung,pins = "gpp16-0", "gpp16-1";
> +		samsung,pin-function = <GS101_PIN_FUNC_3>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +		samsung,pin-pud-pdn = <GS101_PIN_PDN_OUT0>;
> +	};
> +
> +	uart8_bus_single: uart8-bus-pins {
> +		samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
> +			       "gpp16-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi8_bus: spi8-bus-pins {
> +		samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi8_cs: spi8-cs-pins {
> +		samsung,pins = "gpp16-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi8_cs_func: spi8-cs-func-pins {
> +		samsung,pins = "gpp16-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c7_bus: hsi2c7-bus-pins {
> +		samsung,pins = "gpp14-0", "gpp14-1";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart7_bus_single: uart7-bus-pins {
> +		samsung,pins = "gpp14-0", "gpp14-1",
> +			       "gpp14-2", "gpp14-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi7_bus: spi7-bus-pins {
> +		samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi7_cs: spi7-cs-pins {
> +		samsung,pins = "gpp14-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi7_cs_func: spi7-cs-func-pins {
> +		samsung,pins = "gpp14-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c6_bus: hsi2c6-bus-pins {
> +		samsung,pins = "gpp12-0", "gpp12-1";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart6_bus_single: uart6-bus-pins {
> +		samsung,pins = "gpp12-0", "gpp12-1",
> +			       "gpp12-2", "gpp12-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi6_bus: spi6-bus-pins {
> +		samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi6_cs: spi6-cs-pins {
> +		samsung,pins = "gpp12-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi6_cs_func: spi6-cs-func-pins {
> +		samsung,pins = "gpp12-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c5_bus: hsi2c5-bus-pins {
> +		samsung,pins = "gpp10-0", "gpp10-1";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart5_bus_single: uart5-bus-pins {
> +		samsung,pins = "gpp10-0", "gpp10-1",
> +			       "gpp10-2", "gpp10-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi5_bus: spi5-bus-pins {
> +		samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +		samsung,pin-function = <GS101_PIN_FUNC_3>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
> +		samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
> +	};
> +
> +	spi5_cs_func: spi5-cs-func-pins {
> +		samsung,pins = "gpp10-3";
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +		samsung,pin-function = <GS101_PIN_FUNC_3>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
> +		samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
> +	};
> +
> +	hsi2c4_bus: hsi2c4-bus-pins {
> +		samsung,pins = "gpp8-0", "gpp8-1";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart4_bus_single: uart4-bus-pins {
> +		samsung,pins = "gpp8-0", "gpp8-1",
> +			       "gpp8-2", "gpp8-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi4_bus: spi4-bus-pins {
> +		samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi4_cs: spi4-cs-pins {
> +		samsung,pins = "gpp8-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi4_cs_func: spi4-cs-func-pins {
> +		samsung,pins = "gpp8-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c3_bus: hsi2c3-bus-pins {
> +		samsung,pins = "gpp6-0", "gpp6-1";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart3_bus_single: uart3-bus-pins {
> +		samsung,pins = "gpp6-0", "gpp6-1",
> +			       "gpp6-2", "gpp6-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi3_bus: spi3-bus-pins {
> +		samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi3_cs: spi3-cs-pins {
> +		samsung,pins = "gpp6-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi3_cs_func: spi3-cs-func-pins {
> +		samsung,pins = "gpp6-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c2_bus: hsi2c2-bus-pins {
> +		samsung,pins = "gpp4-0", "gpp4-1";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart2_bus_single: uart2-bus-pins {
> +		samsung,pins = "gpp4-0", "gpp4-1",
> +			       "gpp4-2", "gpp4-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi2_bus: spi2-bus-pins {
> +		samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi2_cs: spi2-cs-pins {
> +		samsung,pins = "gpp4-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi2_cs_func: spi2-cs-func-pins {
> +		samsung,pins = "gpp4-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c1_bus: hsi2c1-bus-pins {
> +		samsung,pins = "gpp2-0", "gpp2-1";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart1_bus_single: uart1-bus-pins {
> +		samsung,pins = "gpp2-0", "gpp2-1",
> +			       "gpp2-2", "gpp2-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi1_bus: spi1-bus-pins {
> +		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi1_cs: spi1-cs-pins {
> +		samsung,pins = "gpp2-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi1_cs_func: spi1-cs-func-pins {
> +		samsung,pins = "gpp2-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +};
> +
> +/* GPIO_PERIC1 */
> +&pinctrl_5 {
> +	gpp20: gpp20-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp21: gpp21-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp22: gpp22-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp23: gpp23-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp24: gpp24-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp25: gpp25-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp26: gpp26-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	gpp27: gpp27-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +	};
> +
> +	hsi2c13_bus: hsi2c13-bus-pins  {
> +		samsung,pins = "gpp25-0", "gpp25-1";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart13_bus_single: uart13-bus-pins {
> +	       samsung,pins = "gpp25-0", "gpp25-1",
> +			      "gpp25-2", "gpp25-3";
> +	       samsung,pin-function = <2>;
> +	       samsung,pin-pud = <0>;
> +	};
> +
> +	spi13_bus: spi13-bus-pins {
> +		samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi13_cs: spi13-cs-pins {
> +		samsung,pins = "gpp25-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi13_cs_func: spi13-cs-func-pins {
> +		samsung,pins = "gpp25-3";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c12_bus: hsi2c12-bus-pins {
> +		samsung,pins = "gpp23-4", "gpp23-5";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart12_bus_single: uart12-bus-pins {
> +		samsung,pins = "gpp23-4", "gpp23-5",
> +			       "gpp23-6", "gpp23-7";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi12_bus: spi12-bus-pins {
> +		samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi14_cs2: spi14-cs2-pins {
> +		samsung,pins = "gpp23-6";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi12_cs: spi12-cs-pins {
> +		samsung,pins = "gpp23-7";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi12_cs_func: spi12-cs-func-pins {
> +		samsung,pins = "gpp23-7";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c11_bus: hsi2c11-bus-pins {
> +		samsung,pins = "gpp23-0", "gpp23-1";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart11_bus_single: uart11-bus-pins {
> +		samsung,pins = "gpp23-0", "gpp23-1",
> +			       "gpp23-2", "gpp23-3";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi11_bus: spi11-bus-pins {
> +		samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi11_cs: spi11-cs-pins {
> +		samsung,pins = "gpp23-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi11_cs_func: spi11-cs-func-pins {
> +		samsung,pins = "gpp23-3";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c10_bus: hsi2c10-bus-pins {
> +		samsung,pins = "gpp21-0", "gpp21-1";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart10_bus_single: uart10-bus-pins {
> +		samsung,pins = "gpp21-0", "gpp21-1",
> +			       "gpp21-2", "gpp21-3";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi10_bus: spi10-bus-pins {
> +		samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi10_cs: spi10-cs-pins {
> +		samsung,pins = "gpp21-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi10_cs_func: spi10-cs-func-pins {
> +		samsung,pins = "gpp21-3";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c9_bus: hsi2c9-bus-pins {
> +		samsung,pins = "gpp20-4", "gpp20-5";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart9_bus_single: uart9-bus-pins {
> +		samsung,pins = "gpp20-4", "gpp20-5",
> +			       "gpp20-6", "gpp20-7";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi9_bus: spi9-bus-pins {
> +		samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi9_cs: spi9-cs-pins {
> +		samsung,pins = "gpp20-7";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi9_cs_func: spi9-cs-func-pins {
> +		samsung,pins = "gpp20-7";
> +		samsung,pin-function = <2>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	hsi2c0_bus: hsi2c0-bus-pins {
> +		samsung,pins = "gpp20-0", "gpp20-1";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	uart0_bus_single: uart0-bus-pins {
> +		samsung,pins = "gpp20-0", "gpp20-1",
> +			       "gpp20-2", "gpp20-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +	};
> +
> +	spi0_bus: spi0-bus-pins {
> +		samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi0_cs: spi0-cs-pins {
> +		samsung,pins = "gpp20-3";
> +		samsung,pin-function = <1>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	spi0_cs_func: spi0-cs-func-pins {
> +		samsung,pins = "gpp20-3";
> +		samsung,pin-function = <3>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +};
> +
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> new file mode 100644
> index 000000000000..16c54888f4bb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Pinctrl binding constants for GS101
> + *
> + * Copyright (c) 2020-2023 Google, LLC.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
> +#define __DT_BINDINGS_PINCTRL_GS101_H__
> +
> +#define GS101_PIN_PULL_NONE		0
> +#define GS101_PIN_PULL_DOWN		1
> +#define GS101_PIN_PULL_UP		3
> +
> +/* Pin function in power down mode */
> +#define GS101_PIN_PDN_OUT0		0
> +#define GS101_PIN_PDN_OUT1		1
> +#define GS101_PIN_PDN_INPUT		2
> +#define GS101_PIN_PDN_PREV		3
> +
> +/* GS101 drive strengths */
> +#define GS101_PIN_DRV_2_5_MA		0
> +#define GS101_PIN_DRV_5_MA		1
> +#define GS101_PIN_DRV_7_5_MA		2
> +#define GS101_PIN_DRV_10_MA		3
> +
> +#define GS101_PIN_FUNC_INPUT		0
> +#define GS101_PIN_FUNC_OUTPUT		1
> +#define GS101_PIN_FUNC_2		2
> +#define GS101_PIN_FUNC_3		3
> +
> +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
> diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> new file mode 100644
> index 000000000000..37fb0a4dc8d3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> @@ -0,0 +1,504 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/clock/google,gs101.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "google,gs101";
> +	#address-cells = <2>;
> +	#size-cells = <1>;
> +
> +	interrupt-parent = <&gic>;
> +
> +	aliases {
> +		pinctrl0 = &pinctrl_0;
> +		pinctrl1 = &pinctrl_1;
> +		pinctrl2 = &pinctrl_2;
> +		pinctrl3 = &pinctrl_3;
> +		pinctrl4 = &pinctrl_4;
> +		pinctrl5 = &pinctrl_5;
> +		pinctrl6 = &pinctrl_6;
> +		pinctrl7 = &pinctrl_7;
> +		serial0 = &serial_0;
> +	};
> +
> +	arm-pmu {
> +		compatible = "arm,armv8-pmuv3";
> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	dsu-pmu-0 {
> +		compatible = "arm,dsu-pmu";
> +		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
> +		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
> +		       <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> +	};
> +
> +	/* TODO replace with CCF clock */
> +	dummy_clk: oscillator {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <12345>;
> +		clock-output-names = "pclk";
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu4>;
> +				};
> +				core1 {
> +					cpu = <&cpu5>;
> +				};
> +			};
> +
> +			cluster2 {
> +				core0 {
> +					cpu = <&cpu6>;
> +				};
> +				core1 {
> +					cpu = <&cpu7>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0000>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +			capacity-dmips-mhz = <250>;
> +			dynamic-power-coefficient = <70>;
> +		};
> +
> +		cpu1: cpu@100 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0100>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +			capacity-dmips-mhz = <250>;
> +			dynamic-power-coefficient = <70>;
> +		};
> +
> +		cpu2: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0200>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +			capacity-dmips-mhz = <250>;
> +			dynamic-power-coefficient = <70>;
> +		};
> +
> +		cpu3: cpu@300 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0300>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +			capacity-dmips-mhz = <250>;
> +			dynamic-power-coefficient = <70>;
> +		};
> +
> +		cpu4: cpu@400 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0400>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> +			capacity-dmips-mhz = <620>;
> +			dynamic-power-coefficient = <284>;
> +		};
> +
> +		cpu5: cpu@500 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0500>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> +			capacity-dmips-mhz = <620>;
> +			dynamic-power-coefficient = <284>;
> +		};
> +
> +		cpu6: cpu@600 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0600>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&HERA_CPU_SLEEP>;
> +			capacity-dmips-mhz = <1024>;
> +			dynamic-power-coefficient = <650>;
> +		};
> +
> +		cpu7: cpu@700 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0700>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&HERA_CPU_SLEEP>;
> +			capacity-dmips-mhz = <1024>;
> +			dynamic-power-coefficient = <650>;
> +		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> +				idle-state-name = "c2";
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010000>;
> +				entry-latency-us = <70>;
> +				exit-latency-us = <160>;
> +				min-residency-us = <2000>;
> +			};
> +
> +			ENYO_CPU_SLEEP: cpu-enyo-sleep {
> +				idle-state-name = "c2";
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010000>;
> +				entry-latency-us = <150>;
> +				exit-latency-us = <190>;
> +				min-residency-us = <2500>;
> +			};
> +
> +			HERA_CPU_SLEEP: cpu-hera-sleep {
> +				idle-state-name = "c2";
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010000>;
> +				entry-latency-us = <235>;
> +				exit-latency-us = <220>;
> +				min-residency-us = <3500>;
> +			};
> +		};
> +	};
> +
> +	/* bootloader requires ect node */
> +	ect {
> +		parameter_address = <0x90000000>;
> +		parameter_size = <0x53000>;
> +	};
> +
> +	ext_24_5m: clock-1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <24576000>;
> +		clock-output-names = "oscclk";
> +	};
> +
> +	ext_200m: clock-2 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <200000000>;
> +		clock-output-names = "ext-200m";
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	reserved_memory: reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		gsa_reserved_protected: gsa@90200000 {
> +			reg = <0x0 0x90200000 0x400000>;
> +			no-map;
> +		};
> +
> +		tpu_fw_reserved: tpu-fw@93000000 {
> +			reg = <0x0 0x93000000 0x1000000>;
> +			no-map;
> +		};
> +
> +		aoc_reserve: aoc@94000000 {
> +			reg = <0x0 0x94000000 0x03000000>;
> +			no-map;
> +		};
> +
> +		abl_reserved: abl@f8800000 {
> +			reg = <0x0 0xf8800000 0x02000000>;
> +			no-map;
> +		};
> +
> +		dss_log_reserved: dss-log-reserved@fd3f0000 {
> +			reg = <0 0xfd3f0000 0x0000e000>;
> +			no-map;
> +		};
> +
> +		debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
> +			reg = <0 0xfd3fe000 0x00001000>;
> +			no-map;
> +		};
> +
> +		bldr_log_reserved: bldr-log-reserved@fd800000 {
> +			reg = <0 0xfd800000 0x00100000>;
> +			no-map;
> +		};
> +
> +		bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
> +			reg = <0 0xfd900000 0x00002000>;
> +			no-map;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <24576000>;
> +	};
> +
> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		cmu_misc: clock-controller@10010000 {
> +			compatible = "google,gs101-cmu-misc";
> +			reg = <0x0 0x10010000 0x8000>;
> +			#clock-cells = <1>;
> +			clocks =  <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
> +			clock-names = "oscclk", "dout_cmu_misc_bus";
> +		};
> +
> +		watchdog_cl0: watchdog@10060000 {
> +			compatible = "google,gs101-wdt";
> +			reg = <0x0 0x10060000 0x100>;
> +			interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
> +			clock-names = "watchdog", "watchdog_src";
> +			samsung,syscon-phandle = <&pmu_system_controller>;
> +			samsung,cluster-index = <0>;
> +		};
> +
> +		watchdog_cl1: watchdog@10070000 {
> +			compatible = "google,gs101-wdt";
> +			reg = <0x0 0x10070000 0x100>;
> +			interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
> +			clock-names = "watchdog", "watchdog_src";
> +			samsung,syscon-phandle = <&pmu_system_controller>;
> +			samsung,cluster-index = <1>;
> +			status = "disabled";
> +		};
> +
> +		gic: interrupt-controller@10400000 {
> +		     compatible = "arm,gic-v3";
> +		     #interrupt-cells = <3>;
> +		     interrupt-controller;
> +		     reg = <0x0 0x10400000 0x10000>,	/* GICD */
> +			   <0x0 0x10440000 0x100000>;	/* GICR * 8 */
> +		     interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		sysreg_peric0: syscon@10821000 {
> +			compatible = "google,gs101-peric0-sysreg", "syscon";
> +			reg = <0x0 0x10821000 0x40000>;
> +		};
> +
> +		/* GPIO_PERIC0 */
> +		pinctrl_4: pinctrl@10840000 {
> +			compatible = "google,gs101-pinctrl";
> +			reg = <0x0 0x10840000 0x00001000>;
> +			interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		serial_0: serial@10a00000 {
> +			compatible = "google,gs101-uart";
> +			reg = <0x0 0x10a00000 0xc0>;
> +			reg-io-width = <4>;
> +			samsung,uart-fifosize = <256>;
> +			interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> +			clock-names = "uart", "clk_uart_baud0";
> +		};
> +
> +		/* GPIO_PERIC1 */
> +		pinctrl_5: pinctrl@10c40000 {
> +			compatible = "google,gs101-pinctrl";
> +			reg = <0x0 0x10C40000 0x00001000>;
> +			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		sysreg_peric1: syscon@10c21000 {
> +			compatible = "google,gs101-peric1-sysreg", "syscon";
> +			reg = <0x0 0x10C21000 0x40000>;
> +		};
> +
> +		/* GPIO_HSI1 */
> +		pinctrl_6: pinctrl@11840000 {
> +			compatible = "google,gs101-pinctrl";
> +			reg = <0x0 0x11840000 0x00001000>;
> +			interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		/* GPIO_HSI2 */
> +		pinctrl_7: pinctrl@14440000 {
> +			compatible = "google,gs101-pinctrl";
> +			reg = <0x0 0x14440000 0x00001000>;
> +			interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		cmu_apm: clock-controller@17400000 {
> +			compatible = "google,gs101-cmu-apm";
> +			reg = <0x0 0x17400000 0x8000>;
> +			#clock-cells = <1>;
> +
> +			clocks = <&ext_24_5m>;
> +			clock-names = "oscclk";
> +		};
> +
> +		sysreg_apm: syscon@174204e0 {
> +			compatible = "google,gs101-apm-sysreg", "syscon";
> +			reg = <0x0 0x174204e0 0x1000>;
> +		};
> +
> +		pmu_system_controller: system-controller@17460000 {
> +			compatible = "google,gs101-pmu", "syscon";
> +			reg = <0x0 0x17460000 0x10000>;
> +		};
> +
> +		/* GPIO_ALIVE */
> +		pinctrl_0: pinctrl@174d0000 {
> +			compatible = "google,gs101-pinctrl";
> +			reg = <0x0 0x174d0000 0x00001000>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			wakeup-interrupt-controller {
> +				compatible = "google,gs101-wakeup-eint";
> +			};
> +		};
> +
> +		/* GPIO_FAR_ALIVE */
> +		pinctrl_1: pinctrl@174e0000 {
> +			compatible = "google,gs101-pinctrl";
> +			reg = <0x0 0x174e0000 0x00001000>;
> +			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			wakeup-interrupt-controller {
> +				compatible = "google,gs101-wakeup-eint";
> +			};
> +		};
> +
> +		/* GPIO_GSACTRL */
> +		pinctrl_3: pinctrl@17940000 {
> +			compatible = "google,gs101-pinctrl";
> +			reg = <0x0 0x17940000 0x00001000>;
> +		};
> +
> +		/* GPIO_GSACORE */
> +		pinctrl_2: pinctrl@17a80000 {
> +			compatible = "google,gs101-pinctrl";
> +			reg = <0x0 0x17a80000 0x00001000>;
> +		};
> +
> +		cmu_top: clock-controller@1e080000 {
> +			compatible = "google,gs101-cmu-top";
> +			reg = <0x0 0x1e080000 0x8000>;
> +			#clock-cells = <1>;
> +
> +			clocks = <&ext_24_5m>;
> +			clock-names = "oscclk";
> +		};
> +	};
> +};
> +
> +#include "gs101-pinctrl.dtsi"
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 18/20] arm64: dts: google: Add initial Oriole/pixel 6 board support

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Add initial board support for the Pixel 6 phone code named Oriole. This
> has been tested with a minimal busybox initramfs and boots to a shell.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  arch/arm64/boot/dts/google/Makefile         |  4 ++
>  arch/arm64/boot/dts/google/gs101-oriole.dts | 79 +++++++++++++++++++++
>  2 files changed, 83 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/google/Makefile
>  create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
> 
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> new file mode 100644
> index 000000000000..5cea8ff27141
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> +	gs101-oriole.dtb \
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
> new file mode 100644
> index 000000000000..3bebca989d34
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "gs101-pinctrl.h"
> +#include "gs101.dtsi"
> +
> +/ {
> +	model = "Oriole";
> +	compatible = "google,gs101-oriole", "google,gs101";
> +
> +	chosen {
> +		bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0";
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&key_voldown &key_volup &key_power>;
> +
> +		button-vol-down {
> +			label = "KEY_VOLUMEDOWN";
> +			linux,code = <KEY_VOLUMEDOWN>;
> +			gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +
> +		button-vol-up {
> +			label = "KEY_VOLUMEUP";
> +			linux,code = <KEY_VOLUMEUP>;
> +			gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +
> +		button-power {
> +			label = "KEY_POWER";
> +			linux,code = <KEY_POWER>;
> +			gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +	};
> +};
> +
> +&pinctrl_1 {
> +	key_voldown: key-voldown-pins {
> +		samsung,pins = "gpa7-3";
> +		samsung,pin-function = <0xf>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	key_volup: key-volup-pins {
> +		samsung,pins = "gpa8-1";
> +		samsung,pin-function = <0xf>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +};
> +
> +&pinctrl_0 {
> +	key_power: key-power-pins {
> +		samsung,pins = "gpa10-1";
> +		samsung,pin-function = <0xf>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +};
> +
> +&watchdog_cl0 {
> +	timeout-sec = <30>;
> +};
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 19/20] arm64: defconfig: Enable Google Tensor SoC

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Add the Google Tensor SoC to the arm64 defconfig
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

Thanks,
Will

> ---
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 5315789f4868..8a34603b1822 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -41,6 +41,7 @@ CONFIG_ARCH_BCMBCA=y
>  CONFIG_ARCH_BRCMSTB=y
>  CONFIG_ARCH_BERLIN=y
>  CONFIG_ARCH_EXYNOS=y
> +CONFIG_ARCH_GOOGLE_TENSOR=y
>  CONFIG_ARCH_SPARX5=y
>  CONFIG_ARCH_K3=y
>  CONFIG_ARCH_LG1K=y
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 00/20] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board

[William McVicker]

On 10/11/2023, Peter Griffin wrote:
> Hi folks,
> 
> Firstly, thanks to everyone who reviewed the v2/V1 series! V3 incorporates
> all the review feedback received so far.
> 
> As this series spans multiple subsytems the expectation is that Krzysztof
> will apply the whole series through the Samsung SoC tree. If the relevant
> subsystem maintainers can give a acked-by or reviewed-by on the relevant
> patches that would be most appreciated!
> 
> This series adds initial SoC support for the GS101 SoC and also initial board
> support for Pixel 6 phone (Oriole).
> 
> The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro
> (raven) phones. Currently DT is added for the gs101 SoC and Oriole.
> As you can see from the patches the SoC is based on a Samsung Exynos SoC,
> and therefore lots of the low level Exynos drivers and bindings can be
> re-used.
> 
> The support added in this series consists of:
> * cpus
> * pinctrl
> * some CCF implementation
> * watchdog
> * uart
> * gpio
> 
> This is enough to boot through to a busybox initramfs and shell using an
> upstream kernel though :) More platform support will be added over the
> following weeks and months.
> 
> For further information on how to build and flash the upstream kernel on your
> Pixel 6, with a prebuilt busybox initramfs please refer to the script and
> README.md here:
> 
> https://git.codelinaro.org/linaro/googlelt/pixelscripts
> 
> Note 1: I've removed the dtbo overlay from v2 and later submissions and
> will re-submit once I have appropriate documentation for it.
> 
> Note 2: I've left the bootargs in dts with earlycon for now, for two reasons.
> 1) The bootloader hangs if bootargs isn't present in the dtb as it tries to
> re-write this with additional bootargs.
> 2) there is a issue whereby the full serial console doesn't come up properly
> if earlycon isn't also specified. This issue needs further investigation.
> 
> kind regards,
> 
> Peter.

Thanks Peter for sending the series out and for the quick turn around in
addressing the feedback! I've tested the v3 patch series on my oriole device by
following your README. I was able to successfully boot to the busybox console.

Thanks,
Will

> 
> Changes since v2:
>  - Fixup pinctrl@174d0000: interrupts: [..] is too long DTC warning (Tudor)
>  - Add missing windowed watchdog code (Guenter)
>  - Fixup UART YAML bindings error (Krzysztof)
>  - gs101.dtsi add missing serial_0 alias (me)
>  - samsung_tty.c: fixup gs101_serial_drv_data so fifosize os obtained from DT
>  
> Changes since v1:
>  - Remove irq/gs101.h and replace macros with irq numbers globally
>  - exynos-pmu - keep alphabetical order
>  - add cmu_apm to clock bindings documentation
>  - sysreg bindings - remove superfluous `google,gs101-sysreg`
>  - watchdog bindings - Alphanumerical order, update gs201 comment
>  - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC
>  - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order
>  - samsung,pinctrl- add google,gs101-wakeup-eint compatible
>  - clk-pll: fixup typos
>  - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate)
>  - clk-gs101: fix alphabetical order
>  - clk-gs101: cmu_apm: fixup typo and missing empty entry
>  - clk-gs101: cmu_misc: remove clocks that were being registerred twice
>  - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield
>  - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well
>  - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter
>  - watchdog: s3c2410_wdt: remove dev_info prints
>  - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines
>    add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix
>  - gs101-oriole.dtso: Remove overlay until board_id is documented properly
>  - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones
>  - gpio-keys: update linux,code to use input-event-code macros
>  - add dedicated gs101-uart compatible
> 
> Peter Griffin (20):
>   dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
>   dt-bindings: clock: Add Google gs101 clock management unit bindings
>   dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG
>     compatibles to GS101
>   dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
>   dt-bindings: arm: google: Add bindings for Google ARM platforms
>   dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
>   dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
>   dt-bindings: serial: samsung: Add google-gs101-uart compatible
>   clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
>   clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
>   clk: samsung: clk-gs101: add CMU_APM support
>   clk: samsung: clk-gs101: Add support for CMU_MISC clock unit
>   pinctrl: samsung: Add filter selection support for alive banks
>   pinctrl: samsung: Add gs101 SoC pinctrl configuration
>   watchdog: s3c2410_wdt: Add support for Google tensor SoCs
>   tty: serial: samsung: Add gs101 compatible and SoC data
>   arm64: dts: google: Add initial Google gs101 SoC support
>   arm64: dts: google: Add initial Oriole/pixel 6 board support
>   arm64: defconfig: Enable Google Tensor SoC
>   MAINTAINERS: add entry for Google Tensor SoC
> 
>  .../devicetree/bindings/arm/google.yaml       |   46 +
>  .../bindings/clock/google,gs101-clock.yaml    |  125 +
>  .../samsung,pinctrl-wakeup-interrupt.yaml     |    2 +
>  .../bindings/pinctrl/samsung,pinctrl.yaml     |   22 +-
>  .../bindings/serial/samsung_uart.yaml         |    1 +
>  .../bindings/soc/samsung/exynos-pmu.yaml      |    2 +
>  .../soc/samsung/samsung,exynos-sysreg.yaml    |    6 +
>  .../bindings/watchdog/samsung-wdt.yaml        |   10 +-
>  MAINTAINERS                                   |   10 +
>  arch/arm64/Kconfig.platforms                  |    6 +
>  arch/arm64/boot/dts/Makefile                  |    1 +
>  arch/arm64/boot/dts/google/Makefile           |    4 +
>  arch/arm64/boot/dts/google/gs101-oriole.dts   |   79 +
>  arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 ++++++++++
>  arch/arm64/boot/dts/google/gs101-pinctrl.h    |   32 +
>  arch/arm64/boot/dts/google/gs101.dtsi         |  504 ++++
>  arch/arm64/configs/defconfig                  |    1 +
>  drivers/clk/samsung/Kconfig                   |    9 +
>  drivers/clk/samsung/Makefile                  |    2 +
>  drivers/clk/samsung/clk-gs101.c               | 2164 +++++++++++++++++
>  drivers/clk/samsung/clk-pll.c                 |    9 +-
>  drivers/clk/samsung/clk-pll.h                 |    3 +
>  .../pinctrl/samsung/pinctrl-exynos-arm64.c    |  163 ++
>  drivers/pinctrl/samsung/pinctrl-exynos.c      |   84 +-
>  drivers/pinctrl/samsung/pinctrl-exynos.h      |   41 +
>  drivers/pinctrl/samsung/pinctrl-samsung.c     |    4 +
>  drivers/pinctrl/samsung/pinctrl-samsung.h     |   24 +
>  drivers/tty/serial/samsung_tty.c              |   13 +
>  drivers/watchdog/s3c2410_wdt.c                |  127 +-
>  include/dt-bindings/clock/google,gs101.h      |  232 ++
>  30 files changed, 4985 insertions(+), 16 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
>  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>  create mode 100644 arch/arm64/boot/dts/google/Makefile
>  create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
>  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
>  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
>  create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>  create mode 100644 drivers/clk/samsung/clk-gs101.c
>  create mode 100644 include/dt-bindings/clock/google,gs101.h
> 
> -- 
> 2.42.0.655.g421f12c284-goog
> 

Re: [PATCH v3 13/20] pinctrl: samsung: Add filter selection support for alive banks

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Newer Exynos SoCs have a filter selection register on alive bank pins.
> This allows the selection of a digital or delay filter for each pin. If
> the filter selection register is not available then the default filter
> (digital) is applied.
>

I wonder if that solves any particular issue. For Exynos850 I decided
against adding this feature because I failed to find any benefits of
it. Didn't even come up with the way to test it. Is it really needed
for this SoC functioning? In case you have some more details on why
it's needed and how it can be tested, please add that info to the
commit message as well.

> On suspend we apply the analog filter to all pins in the bank, and on
> resume the digital filter is reapplied to all pins in the bank.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Heads up: I noticed some merge warnings when applying this patch onto
the most recent linux-next, like so:

8<---------------------------------------------------------------------->8
    Applying: pinctrl: samsung: Add filter selection support for alive banks
    Using index info to reconstruct a base tree...
    M    drivers/pinctrl/samsung/pinctrl-exynos.c
    M    drivers/pinctrl/samsung/pinctrl-exynos.h
    M    drivers/pinctrl/samsung/pinctrl-samsung.c
    M    drivers/pinctrl/samsung/pinctrl-samsung.h
    Falling back to patching base and 3-way merge...
    Auto-merging drivers/pinctrl/samsung/pinctrl-samsung.h
    Auto-merging drivers/pinctrl/samsung/pinctrl-samsung.c
    Auto-merging drivers/pinctrl/samsung/pinctrl-exynos.h
    Auto-merging drivers/pinctrl/samsung/pinctrl-exynos.c
8<---------------------------------------------------------------------->8

It was still applied, but maybe if you are going to send v4 try to
rebase your series on top of linux-next first.

Below are pretty minor comments for the code.

>  drivers/pinctrl/samsung/pinctrl-exynos.c  | 82 ++++++++++++++++++++++-
>  drivers/pinctrl/samsung/pinctrl-exynos.h  |  7 ++
>  drivers/pinctrl/samsung/pinctrl-samsung.c |  2 +
>  drivers/pinctrl/samsung/pinctrl-samsung.h | 23 +++++++
>  4 files changed, 113 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index a8212fc126bf..800831aa8357 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -269,6 +269,68 @@ struct exynos_eint_gpio_save {
>         u32 eint_mask;
>  };
>
> +static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d,
> +                                  struct samsung_pin_bank *bank, int filter)
> +{
> +       unsigned int flt_reg, flt_con = 0;
> +       unsigned int val, shift;
> +       int i;
> +       int loop_cnt;
> +
> +       /*
> +        * This function sets the desired filter (digital or delay) to
> +        * every pin in the bank. Note the filter selection bitfield is
> +        * only found on alive banks. The FLTCON register has the
> +        * following layout
> +        *
> +        * BitfieldName[PinNum][Bit:Bit]
> +        *
> +        * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
> +        * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
> +        * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
> +        * FLT_EN[0][7]  FLT_SEL[0][6]  FLT_WIDTH[0][5:0]
> +        */

Maybe move this comment above this function? Or split it in two parts:
function doc, and 'flt_con' variable doc.

> +
> +       flt_con |= EXYNOS9_FLTCON_EN;
> +
> +       if (filter)

Different values are passed as a 'filter' param to this function. But
here it's only used as a boolean value. Something doesn't feel right.

> +               flt_con |= EXYNOS9_FLTCON_SEL_DIGITAL;
> +
> +       flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
> +
> +       if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN)
> +               /*
> +                * if nr_pins > 4, we should set FLTCON0 register fully.
> +                * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
> +                */

Maybe move this comment above 'if' block? And start with capital
letter, for consistency with other multi-line comments.

> +               loop_cnt = EXYNOS9_FLTCON_NR_PIN;
> +       else
> +               loop_cnt = bank->nr_pins;
> +
> +       val = readl(d->virt_base + flt_reg);
> +

Maybe remove this empty line to make RMW block the whole?

> +       for (i = 0; i < loop_cnt; i++) {
> +               shift = i * EXYNOS9_FLTCON_LEN;
> +               val &= ~(EXYNOS9_FLTCON_MASK << shift);
> +               val |= (flt_con << shift);
> +       }
> +

Ditto.

> +       writel(val, d->virt_base + flt_reg);
> +
> +       /* loop for FLTCON1 pin 4 ~ 7 */

Start with a capital letter for consistency.

> +       if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) {
> +               val = readl(d->virt_base + flt_reg + 0x4);
> +               loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN);
> +
> +               for (i = 0; i < loop_cnt; i++) {
> +                       shift = i * EXYNOS9_FLTCON_LEN;
> +                       val &= ~(EXYNOS9_FLTCON_MASK << shift);
> +                       val |= (flt_con << shift);
> +               }

Code duplication, but it's minor.

> +               writel(val, d->virt_base + flt_reg + 0x4);
> +       }
> +}
> +
>  /*
>   * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
>   * @d: driver data of samsung pinctrl driver.
> @@ -321,6 +383,9 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
>                         goto err_domains;
>                 }
>
> +               /* Set Delay Analog Filter */
> +               if (bank->fltcon_type != FLT_DEFAULT)
> +                       exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DELAY);
>         }
>
>         return 0;
> @@ -555,6 +620,10 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
>                 if (bank->eint_type != EINT_TYPE_WKUP)
>                         continue;
>
> +               /* Set Digital Filter */
> +               if (bank->fltcon_type != FLT_DEFAULT)
> +                       exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DIGITAL);

Please stick to 80 characters per line when possible.

> +
>                 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
>                                               GFP_KERNEL);
>                 if (!bank->irq_chip) {
> @@ -658,6 +727,7 @@ static void exynos_pinctrl_suspend_bank(
>  void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
>  {
>         struct samsung_pin_bank *bank = drvdata->pin_banks;
> +       struct samsung_pinctrl_drv_data *d = bank->drvdata;
>         struct exynos_irq_chip *irq_chip = NULL;
>         int i;
>
> @@ -665,6 +735,9 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
>                 if (bank->eint_type == EINT_TYPE_GPIO)
>                         exynos_pinctrl_suspend_bank(drvdata, bank);
>                 else if (bank->eint_type == EINT_TYPE_WKUP) {
> +                       /* Setting Delay (Analog) Filter */
> +                       if (bank->fltcon_type != FLT_DEFAULT)
> +                               exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DELAY);

Please stick to 80 characters per line when possible.

>                         if (!irq_chip) {
>                                 irq_chip = bank->irq_chip;
>                                 irq_chip->set_eint_wakeup_mask(drvdata,
> @@ -707,11 +780,18 @@ static void exynos_pinctrl_resume_bank(
>  void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
>  {
>         struct samsung_pin_bank *bank = drvdata->pin_banks;
> +       struct samsung_pinctrl_drv_data *d = bank->drvdata;
>         int i;
>
>         for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
> -               if (bank->eint_type == EINT_TYPE_GPIO)
> +               if (bank->eint_type == EINT_TYPE_GPIO) {
>                         exynos_pinctrl_resume_bank(drvdata, bank);
> +               } else if (bank->eint_type == EINT_TYPE_WKUP ||
> +                       bank->eint_type == EINT_TYPE_WKUP_MUX) {

Indent it to be under the open bracket on the previous line.

> +                       /* Set Digital Filter */
> +                       if (bank->fltcon_type != FLT_DEFAULT)
> +                               exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DIGITAL);

Please stick to 80 characters per line when possible.

> +               }
>  }
>
>  static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 7bd6d82c9f36..63b2426ad5d6 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -50,6 +50,13 @@
>
>  #define EXYNOS_EINT_MAX_PER_BANK       8
>  #define EXYNOS_EINT_NR_WKUP_EINT
> +/* EINT filter configuration */
> +#define EXYNOS9_FLTCON_EN              BIT(7)
> +#define EXYNOS9_FLTCON_SEL_DIGITAL     BIT(6)
> +#define EXYNOS9_FLTCON_SEL_DELAY       0
> +#define EXYNOS9_FLTCON_MASK            0xff
> +#define EXYNOS9_FLTCON_LEN             8
> +#define EXYNOS9_FLTCON_NR_PIN          4
>

I guess we discussed using EXYNOS9 prefix during the review of
Exynos850 initial submission, and decided against it. But in case of
this SoC (which is obviously Exynos, but is called Google), I'm not
even sure which name would be appropriate. I mean, if it's ok to use
EXYNOS9 prefix, then maybe I should go ahead and rename existing
EXYNOS850 definitions to EXYNOS9 too, as it belongs to the same
platform family, to avoid any confusion.

Krzysztof, what's your take on this?

>  #define EXYNOS_PIN_BANK_EINTN(pins, reg, id)           \
>         {                                               \
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index e54847040b4a..449f8109d8b5 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1104,6 +1104,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
>                 bank->eint_func = bdata->eint_func;
>                 bank->eint_type = bdata->eint_type;
>                 bank->eint_mask = bdata->eint_mask;
> +               bank->fltcon_type = bdata->fltcon_type;
> +               bank->fltcon_offset = bdata->fltcon_offset;
>                 bank->eint_offset = bdata->eint_offset;
>                 bank->name = bdata->name;
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index 9af93e3d8d9f..de2ca8e8b378 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -82,6 +82,21 @@ enum eint_type {
>         EINT_TYPE_WKUP_MUX,
>  };
>
> +/**
> + * enum fltcon_type - filter selection
> + * @FLT_DEFAULT: filter not selectable, default digital filter
> + * @FLT_SELECT: filter selectable (digital or delay)
> + *
> + * Some banks on some SoCs (gs101 and possibly others) have a selectable
> + * filter on alive banks of 'delay/analog' or 'digital'. If the filter
> + * selection is not available then the default filter is used (digital).
> + */
> +

Maybe remove this empty line?

> +enum fltcon_type {
> +       FLT_DEFAULT,
> +       FLT_SELECTABLE,
> +};
> +
>  /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
>  #define PIN_NAME_LENGTH        10
>
> @@ -122,6 +137,8 @@ struct samsung_pin_bank_type {
>   * @eint_type: type of the external interrupt supported by the bank.
>   * @eint_mask: bit mask of pins which support EINT function.
>   * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
> + * @fltcon_type: whether the filter (delay/digital) is selectable
> + * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
>   * @name: name to be prefixed for each pin in this pin bank.
>   */
>  struct samsung_pin_bank_data {
> @@ -133,6 +150,8 @@ struct samsung_pin_bank_data {
>         enum eint_type  eint_type;
>         u32             eint_mask;
>         u32             eint_offset;
> +       enum fltcon_type fltcon_type;
> +       u32             fltcon_offset;
>         const char      *name;
>  };
>
> @@ -147,6 +166,8 @@ struct samsung_pin_bank_data {
>   * @eint_type: type of the external interrupt supported by the bank.
>   * @eint_mask: bit mask of pins which support EINT function.
>   * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
> + * @fltcon_type: whether the filter (delay/digital) is selectable
> + * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
>   * @name: name to be prefixed for each pin in this pin bank.
>   * @pin_base: starting pin number of the bank.
>   * @soc_priv: per-bank private data for SoC-specific code.
> @@ -169,6 +190,8 @@ struct samsung_pin_bank {
>         enum eint_type  eint_type;
>         u32             eint_mask;
>         u32             eint_offset;
> +       enum fltcon_type fltcon_type;
> +       u32             fltcon_offset;
>         const char      *name;
>
>         u32             pin_base;
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 00/20] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Hi folks,
>
> Firstly, thanks to everyone who reviewed the v2/V1 series! V3 incorporates
> all the review feedback received so far.
>
> As this series spans multiple subsytems the expectation is that Krzysztof
> will apply the whole series through the Samsung SoC tree. If the relevant
> subsystem maintainers can give a acked-by or reviewed-by on the relevant
> patches that would be most appreciated!
>
> This series adds initial SoC support for the GS101 SoC and also initial board
> support for Pixel 6 phone (Oriole).
>
> The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro
> (raven) phones. Currently DT is added for the gs101 SoC and Oriole.
> As you can see from the patches the SoC is based on a Samsung Exynos SoC,
> and therefore lots of the low level Exynos drivers and bindings can be
> re-used.
>
> The support added in this series consists of:
> * cpus
> * pinctrl
> * some CCF implementation
> * watchdog
> * uart
> * gpio
>
> This is enough to boot through to a busybox initramfs and shell using an
> upstream kernel though :) More platform support will be added over the
> following weeks and months.
>
> For further information on how to build and flash the upstream kernel on your
> Pixel 6, with a prebuilt busybox initramfs please refer to the script and
> README.md here:
>
> https://git.codelinaro.org/linaro/googlelt/pixelscripts
>
> Note 1: I've removed the dtbo overlay from v2 and later submissions and
> will re-submit once I have appropriate documentation for it.
>
> Note 2: I've left the bootargs in dts with earlycon for now, for two reasons.
> 1) The bootloader hangs if bootargs isn't present in the dtb as it tries to
> re-write this with additional bootargs.
> 2) there is a issue whereby the full serial console doesn't come up properly
> if earlycon isn't also specified. This issue needs further investigation.
>
> kind regards,
>
> Peter.
>
> Changes since v2:
>  - Fixup pinctrl@174d0000: interrupts: [..] is too long DTC warning (Tudor)
>  - Add missing windowed watchdog code (Guenter)
>  - Fixup UART YAML bindings error (Krzysztof)
>  - gs101.dtsi add missing serial_0 alias (me)
>  - samsung_tty.c: fixup gs101_serial_drv_data so fifosize os obtained from DT
>
> Changes since v1:
>  - Remove irq/gs101.h and replace macros with irq numbers globally
>  - exynos-pmu - keep alphabetical order
>  - add cmu_apm to clock bindings documentation
>  - sysreg bindings - remove superfluous `google,gs101-sysreg`
>  - watchdog bindings - Alphanumerical order, update gs201 comment
>  - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC
>  - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order
>  - samsung,pinctrl- add google,gs101-wakeup-eint compatible
>  - clk-pll: fixup typos
>  - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate)
>  - clk-gs101: fix alphabetical order
>  - clk-gs101: cmu_apm: fixup typo and missing empty entry
>  - clk-gs101: cmu_misc: remove clocks that were being registerred twice
>  - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield
>  - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well
>  - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter
>  - watchdog: s3c2410_wdt: remove dev_info prints
>  - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines
>    add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix
>  - gs101-oriole.dtso: Remove overlay until board_id is documented properly
>  - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones
>  - gpio-keys: update linux,code to use input-event-code macros
>  - add dedicated gs101-uart compatible
>
> Peter Griffin (20):
>   dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
>   dt-bindings: clock: Add Google gs101 clock management unit bindings
>   dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG
>     compatibles to GS101
>   dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings
>   dt-bindings: arm: google: Add bindings for Google ARM platforms
>   dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
>   dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
>   dt-bindings: serial: samsung: Add google-gs101-uart compatible
>   clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
>   clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates
>   clk: samsung: clk-gs101: add CMU_APM support
>   clk: samsung: clk-gs101: Add support for CMU_MISC clock unit

Maybe squash those 3 patches into one? If you're going to send v4.
Just a thought.

>   pinctrl: samsung: Add filter selection support for alive banks
>   pinctrl: samsung: Add gs101 SoC pinctrl configuration
>   watchdog: s3c2410_wdt: Add support for Google tensor SoCs
>   tty: serial: samsung: Add gs101 compatible and SoC data
>   arm64: dts: google: Add initial Google gs101 SoC support
>   arm64: dts: google: Add initial Oriole/pixel 6 board support
>   arm64: defconfig: Enable Google Tensor SoC
>   MAINTAINERS: add entry for Google Tensor SoC
>
>  .../devicetree/bindings/arm/google.yaml       |   46 +
>  .../bindings/clock/google,gs101-clock.yaml    |  125 +
>  .../samsung,pinctrl-wakeup-interrupt.yaml     |    2 +
>  .../bindings/pinctrl/samsung,pinctrl.yaml     |   22 +-
>  .../bindings/serial/samsung_uart.yaml         |    1 +
>  .../bindings/soc/samsung/exynos-pmu.yaml      |    2 +
>  .../soc/samsung/samsung,exynos-sysreg.yaml    |    6 +
>  .../bindings/watchdog/samsung-wdt.yaml        |   10 +-
>  MAINTAINERS                                   |   10 +
>  arch/arm64/Kconfig.platforms                  |    6 +
>  arch/arm64/boot/dts/Makefile                  |    1 +
>  arch/arm64/boot/dts/google/Makefile           |    4 +
>  arch/arm64/boot/dts/google/gs101-oriole.dts   |   79 +
>  arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 ++++++++++
>  arch/arm64/boot/dts/google/gs101-pinctrl.h    |   32 +
>  arch/arm64/boot/dts/google/gs101.dtsi         |  504 ++++
>  arch/arm64/configs/defconfig                  |    1 +
>  drivers/clk/samsung/Kconfig                   |    9 +
>  drivers/clk/samsung/Makefile                  |    2 +
>  drivers/clk/samsung/clk-gs101.c               | 2164 +++++++++++++++++
>  drivers/clk/samsung/clk-pll.c                 |    9 +-
>  drivers/clk/samsung/clk-pll.h                 |    3 +
>  .../pinctrl/samsung/pinctrl-exynos-arm64.c    |  163 ++
>  drivers/pinctrl/samsung/pinctrl-exynos.c      |   84 +-
>  drivers/pinctrl/samsung/pinctrl-exynos.h      |   41 +
>  drivers/pinctrl/samsung/pinctrl-samsung.c     |    4 +
>  drivers/pinctrl/samsung/pinctrl-samsung.h     |   24 +
>  drivers/tty/serial/samsung_tty.c              |   13 +
>  drivers/watchdog/s3c2410_wdt.c                |  127 +-
>  include/dt-bindings/clock/google,gs101.h      |  232 ++
>  30 files changed, 4985 insertions(+), 16 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
>  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>  create mode 100644 arch/arm64/boot/dts/google/Makefile
>  create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
>  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
>  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
>  create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>  create mode 100644 drivers/clk/samsung/clk-gs101.c
>  create mode 100644 include/dt-bindings/clock/google,gs101.h
>
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Provide dt-schema documentation for Google gs101 SoC clock controller.
> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
>  include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
>  2 files changed, 357 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>  create mode 100644 include/dt-bindings/clock/google,gs101.h
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..f74494594b3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,125 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 SoC clock controller
> +
> +maintainers:
> +  - Peter Griffin <peter.griffin@linaro.org>
> +
> +description: |
> +  Google GS101 clock controller is comprised of several CMU units, generating
> +  clocks for different domains. Those CMU units are modeled as separate device
> +  tree nodes, and might depend on each other. The root clock in that clock tree
> +  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> +  clock in dts.
> +
> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> +  Each clock is assigned an identifier and client nodes can use this identifier
> +  to specify the clock which they consume. All clocks available for usage
> +  in clock consumer nodes are defined as preprocessor macros in
> +  'dt-bindings/clock/gs101.h' header.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - google,gs101-cmu-top
> +      - google,gs101-cmu-apm
> +      - google,gs101-cmu-misc
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-top
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-misc
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +            - description: Misc bus clock (from CMU_TOP)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +            - const: dout_cmu_misc_bus
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-apm
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +required:
> +  - compatible
> +  - "#clock-cells"
> +  - clocks
> +  - clock-names
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock controller node for CMU_TOP
> +  - |
> +    #include <dt-bindings/clock/google,gs101.h>
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <1>;
> +
> +        cmu_top: clock-controller@1e080000 {
> +            compatible = "google,gs101-cmu-top";
> +            reg = <0x0 0x1e080000 0x8000>;
> +            #clock-cells = <1>;
> +            clocks = <&ext_24_5m>;
> +            clock-names = "oscclk";
> +        };
> +    };
> +
> +...
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> new file mode 100644
> index 000000000000..7765ba68f734
> --- /dev/null
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -0,0 +1,232 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Device Tree binding constants for Google gs101 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +
> +/* CMU_TOP PLL*/
> +#define CLK_FOUT_SHARED0_PLL           1
> +#define CLK_FOUT_SHARED1_PLL           2
> +#define CLK_FOUT_SHARED2_PLL           3
> +#define CLK_FOUT_SHARED3_PLL           4
> +#define CLK_FOUT_SPARE_PLL             5
> +
> +/* CMU_TOP MUX*/
> +#define CLK_MOUT_SHARED0_PLL           6
> +#define CLK_MOUT_SHARED1_PLL           7
> +#define CLK_MOUT_SHARED2_PLL           8
> +#define CLK_MOUT_SHARED3_PLL           9
> +#define CLK_MOUT_SPARE_PLL             10
> +#define CLK_MOUT_BUS0_BUS              11
> +#define CLK_MOUT_CMU_BOOST             12
> +#define CLK_MOUT_BUS1_BUS              13
> +#define CLK_MOUT_BUS2_BUS              14
> +#define CLK_MOUT_CORE_BUS              15
> +#define CLK_MOUT_EH_BUS                        16
> +#define CLK_MOUT_CPUCL2_SWITCH         17
> +#define CLK_MOUT_CPUCL1_SWITCH         18
> +#define CLK_MOUT_CPUCL0_SWITCH         19
> +#define CLK_MOUT_CPUCL0_DBG            20
> +#define CLK_MOUT_CMU_HPM               21
> +#define CLK_MOUT_G3D_SWITCH            22
> +#define CLK_MOUT_G3D_GLB               23
> +#define CLK_MOUT_DPU_BUS               24
> +#define CLK_MOUT_DISP_BUS              25
> +#define CLK_MOUT_G2D_G2D               26
> +#define CLK_MOUT_G2D_MSCL              27
> +#define CLK_MOUT_HSI0_USB31DRD         28
> +#define CLK_MOUT_HSI0_BUS              29
> +#define CLK_MOUT_HSI0_DPGTC            30
> +#define CLK_MOUT_HSI0_USBDPDGB         31
> +#define CLK_MOUT_HSI1_BUS              32
> +#define CLK_MOUT_HSI1_PCIE             33
> +#define CLK_MOUT_HSI2_BUS              34
> +#define CLK_MOUT_HSI2_PCIE             35
> +#define CLK_MOUT_HSI2_UFS_EMBD         36
> +#define CLK_MOUT_HSI2_MMC_CARD         37
> +#define CLK_MOUT_CSIS                  38
> +#define CLK_MOUT_PDP_BUS               39
> +#define CLK_MOUT_PDP_VRA               40
> +#define CLK_MOUT_IPP_BUS               41
> +#define CLK_MOUT_G3AA                  42
> +#define CLK_MOUT_ITP                   43
> +#define CLK_MOUT_DNS_BUS               44
> +#define CLK_MOUT_TNR_BUS               45
> +#define CLK_MOUT_MCSC_ITSC             46
> +#define CLK_MOUT_MCSC_MCSC             47
> +#define CLK_MOUT_GDC_SCSC              48
> +#define CLK_MOUT_GDC_GDC0              49
> +#define CLK_MOUT_GDC_GDC1              50
> +#define CLK_MOUT_MFC_MFC               51
> +#define CLK_MOUT_MIF_SWITCH            52
> +#define CLK_MOUT_MIF_BUS               53
> +#define CLK_MOUT_MISC_BUS              54
> +#define CLK_MOUT_MISC_SSS              55
> +#define CLK_MOUT_PERIC0_IP             56
> +#define CLK_MOUT_PERIC0_BUS            57
> +#define CLK_MOUT_PERIC1_IP             58
> +#define CLK_MOUT_PERIC1_BUS            59
> +#define CLK_MOUT_TPU_TPU               60
> +#define CLK_MOUT_TPU_TPUCTL            61
> +#define CLK_MOUT_TPU_BUS               62
> +#define CLK_MOUT_TPU_UART              63
> +#define CLK_MOUT_TPU_HPM               64
> +#define CLK_MOUT_BO_BUS                        65
> +#define CLK_MOUT_G3D_BUSD              66
> +
> +/* CMU_TOP Dividers*/
> +#define CLK_DOUT_SHARED0_DIV3          67
> +#define CLK_DOUT_SHARED0_DIV2          68
> +#define CLK_DOUT_SHARED0_DIV4          69
> +#define CLK_DOUT_SHARED0_DIV5          70
> +#define CLK_DOUT_SHARED1_DIV3          71
> +#define CLK_DOUT_SHARED1_DIV2          72
> +#define CLK_DOUT_SHARED1_DIV4          73
> +#define CLK_DOUT_SHARED2_DIV2          74
> +#define CLK_DOUT_SHARED3_DIV2          75
> +#define CLK_DOUT_BUS0_BUS              76
> +#define CLK_DOUT_CMU_BOOST             77
> +#define CLK_DOUT_BUS1_BUS              78
> +#define CLK_DOUT_BUS2_BUS              79
> +#define CLK_DOUT_CORE_BUS              80
> +#define CLK_DOUT_EH_BUS                        81
> +#define CLK_DOUT_CPUCL2_SWITCH         82
> +#define CLK_DOUT_CPUCL1_SWITCH         83
> +#define CLK_DOUT_CPUCL0_SWITCH         84
> +#define CLK_DOUT_CPUCL0_DBG            85
> +#define CLK_DOUT_CMU_HPM               86
> +#define CLK_DOUT_G3D_SWITCH            87
> +#define CLK_DOUT_G3D_GLB               88
> +#define CLK_DOUT_DPU_BUS               89
> +#define CLK_DOUT_DISP_BUS              90
> +#define CLK_DOUT_G2D_G2D               91
> +#define CLK_DOUT_G2D_MSCL              92
> +#define CLK_DOUT_HSI0_USB31DRD         93
> +#define CLK_DOUT_HSI0_BUS              94
> +#define CLK_DOUT_HSI0_DPGTC            95
> +#define CLK_DOUT_HSI0_USBDPDGB         96
> +#define CLK_DOUT_HSI1_BUS              97
> +#define CLK_DOUT_HSI1_PCIE             98
> +#define CLK_DOUT_HSI2_BUS              100
> +#define CLK_DOUT_HSI2_PCIE             101
> +#define CLK_DOUT_HSI2_UFS_EMBD         102
> +#define CLK_DOUT_HSI2_MMC_CARD         103
> +#define CLK_DOUT_CSIS                  104
> +#define CLK_DOUT_PDP_BUS               105
> +#define CLK_DOUT_PDP_VRA               106
> +#define CLK_DOUT_IPP_BUS               107
> +#define CLK_DOUT_G3AA                  108
> +#define CLK_DOUT_ITP                   109
> +#define CLK_DOUT_DNS_BUS               110
> +#define CLK_DOUT_TNR_BUS               111
> +#define CLK_DOUT_MCSC_ITSC             112
> +#define CLK_DOUT_MCSC_MCSC             113
> +#define CLK_DOUT_GDC_SCSC              114
> +#define CLK_DOUT_GDC_GDC0              115
> +#define CLK_DOUT_GDC_GDC1              116
> +#define CLK_DOUT_MFC_MFC               117
> +#define CLK_DOUT_MIF_BUS               118
> +#define CLK_DOUT_MISC_BUS              119
> +#define CLK_DOUT_MISC_SSS              120
> +#define CLK_DOUT_PERIC0_BUS            121
> +#define CLK_DOUT_PERIC0_IP             122
> +#define CLK_DOUT_PERIC1_BUS            123
> +#define CLK_DOUT_PERIC1_IP             124
> +#define CLK_DOUT_TPU_TPU               125
> +#define CLK_DOUT_TPU_TPUCTL            126
> +#define CLK_DOUT_TPU_BUS               127
> +#define CLK_DOUT_TPU_UART              128
> +#define CLK_DOUT_TPU_HPM               129
> +#define CLK_DOUT_BO_BUS                        130
> +
> +/* CMU_TOP Gates*/
> +#define CLK_GOUT_BUS0_BUS              131
> +#define CLK_GOUT_BUS1_BUS              132
> +#define CLK_GOUT_BUS2_BUS              133
> +#define CLK_GOUT_CORE_BUS              134
> +#define CLK_GOUT_EH_BUS                        135
> +#define CLK_GOUT_CPUCL2_SWITCH         136
> +#define CLK_GOUT_CPUCL1_SWITCH         137
> +#define CLK_GOUT_CPUCL0_SWITCH         138
> +#define CLK_GOUT_CPUCL0_DBG            139
> +#define CLK_GOUT_CMU_HPM               140
> +#define CLK_GOUT_G3D_SWITCH            141
> +#define CLK_GOUT_G3D_GLB               142
> +#define CLK_GOUT_DPU_BUS               143
> +#define CLK_GOUT_DISP_BUS              144
> +#define CLK_GOUT_G2D_G2D               145
> +#define CLK_GOUT_G2D_MSCL              146
> +#define CLK_GOUT_HSI0_USB31DRD         147
> +#define CLK_GOUT_HSI0_BUS              148
> +#define CLK_GOUT_HSI0_DPGTC            149
> +#define CLK_GOUT_HSI0_USBDPDGB         150
> +#define CLK_GOUT_HSI1_BUS              151
> +#define CLK_GOUT_HSI1_PCIE             152
> +#define CLK_GOUT_HSI2_BUS              153
> +#define CLK_GOUT_HSI2_PCIE             154
> +#define CLK_GOUT_HSI2_UFS_EMBD         155
> +#define CLK_GOUT_HSI2_MMC_CARD         156
> +#define CLK_GOUT_CSIS                  157
> +#define CLK_GOUT_PDP_BUS               158
> +#define CLK_GOUT_PDP_VRA               159
> +#define CLK_GOUT_IPP_BUS               160
> +#define CLK_GOUT_G3AA                  161
> +#define CLK_GOUT_ITP                   162
> +#define CLK_GOUT_DNS_BUS               163
> +#define CLK_GOUT_TNR_BUS               164
> +#define CLK_GOUT_MCSC_ITSC             165
> +#define CLK_GOUT_MCSC_MCSC             166
> +#define CLK_GOUT_GDC_SCSC              167
> +#define CLK_GOUT_GDC_GDC0              168
> +#define CLK_GOUT_GDC_GDC1              169
> +#define CLK_GOUT_MFC_MFC               170
> +#define CLK_GOUT_MIF_SWITCH            171
> +#define CLK_GOUT_MIF_BUS               172
> +#define CLK_GOUT_MISC_BUS              173
> +#define CLK_GOUT_MISC_SSS              174
> +#define CLK_GOUT_PERIC0_BUS            175
> +#define CLK_GOUT_PERIC0_IP             176
> +#define CLK_GOUT_PERIC1_BUS            177
> +#define CLK_GOUT_PERIC1_IP             178
> +#define CLK_GOUT_TPU_TPU               179
> +#define CLK_GOUT_TPU_TPUCTL            180
> +#define CLK_GOUT_TPU_BUS               181
> +#define CLK_GOUT_TPU_UART              182
> +#define CLK_GOUT_TPU_HPM               183
> +#define CLK_GOUT_BO_BUS                        184
> +#define CLK_GOUT_CMU_BOOST             185
> +
> +/* CMU_APM */
> +
> +#define CLK_MOUT_APM_FUNC                                      1
> +#define CLK_MOUT_APM_FUNCSRC                                   2
> +#define CLK_DOUT_APM_BOOST                                     3
> +#define CLK_DOUT_APM_USI0_UART                                 4
> +#define CLK_DOUT_APM_USI0_USI                                  5
> +#define CLK_DOUT_APM_USI1_UART                                 6
> +#define CLK_GOUT_APM_FUNC                                      7
> +#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK       8
> +#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK   9
> +#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK                10
> +#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK             11
> +#define CLK_APM_PLL_DIV2_APM                                   12
> +#define CLK_APM_PLL_DIV4_APM                                   13
> +#define CLK_APM_PLL_DIV16_APM                                  14
> +
> +/* CMU_MISC */
> +
> +#define CLK_MOUT_MISC_BUS_USER                                 1
> +#define CLK_MOUT_MISC_SSS_USER                                 2
> +#define CLK_DOUT_MISC_BUSP                                     3
> +#define CLK_DOUT_MISC_GIC                                      4
> +#define CLK_GOUT_MISC_PCLK                                     5
> +#define CLK_GOUT_MISC_SYSREG_PCLK                              6
> +#define CLK_GOUT_MISC_WDT_CLUSTER0                             7
> +#define CLK_GOUT_MISC_WDT_CLUSTER1                             8
> +
> +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 03/20] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> GS101 has three different SYSREG controllers, add dedicated
> compatibles for them to the documentation.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  .../bindings/soc/samsung/samsung,exynos-sysreg.yaml         | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> index 163e912e9cad..dbd12a97faad 100644
> --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> @@ -30,6 +30,12 @@ properties:
>                - samsung,exynos5433-fsys-sysreg
>            - const: samsung,exynos5433-sysreg
>            - const: syscon
> +      - items:
> +          - enum:
> +              - google,gs101-peric0-sysreg
> +              - google,gs101-peric1-sysreg
> +              - google,gs101-apm-sysreg
> +          - const: syscon
>        - items:
>            - enum:
>                - samsung,exynos5433-sysreg
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 04/20] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
> dt-schema documentation.
>
> gs101 SoC has two CPU clusters and each cluster has its own dedicated
> watchdog timer (similar to exynos850 and exynosautov9 SoCs).
>
> These WDT instances are controlled using different bits in PMU
> registers.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  .../devicetree/bindings/watchdog/samsung-wdt.yaml      | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> index 8fb6656ba0c2..67c8767f0499 100644
> --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> @@ -17,6 +17,8 @@ description: |+
>  properties:
>    compatible:
>      enum:
> +      - google,gs101-wdt                      # for Google gs101
> +      - google,gs201-wdt                      # for Google gs201
>        - samsung,s3c2410-wdt                   # for S3C2410
>        - samsung,s3c6410-wdt                   # for S3C6410, S5PV210 and Exynos4
>        - samsung,exynos5250-wdt                # for Exynos5250
> @@ -42,13 +44,13 @@ properties:
>    samsung,cluster-index:
>      $ref: /schemas/types.yaml#/definitions/uint32
>      description:
> -      Index of CPU cluster on which watchdog is running (in case of Exynos850)
> +      Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01)

Please stick to 80 characters per line when possible.

>
>    samsung,syscon-phandle:
>      $ref: /schemas/types.yaml#/definitions/phandle
>      description:
>        Phandle to the PMU system controller node (in case of Exynos5250,
> -      Exynos5420, Exynos7 and Exynos850).
> +      Exynos5420, Exynos7, Exynos850 and gsx01).
>
>  required:
>    - compatible
> @@ -69,6 +71,8 @@ allOf:
>                - samsung,exynos7-wdt
>                - samsung,exynos850-wdt
>                - samsung,exynosautov9-wdt
> +              - google,gs101-wdt
> +              - google,gs201-wdt
>      then:
>        required:
>          - samsung,syscon-phandle
> @@ -79,6 +83,8 @@ allOf:
>              enum:
>                - samsung,exynos850-wdt
>                - samsung,exynosautov9-wdt
> +              - google,gs101-wdt
> +              - google,gs201-wdt
>      then:
>        properties:
>          clocks:
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 05/20] dt-bindings: arm: google: Add bindings for Google ARM platforms

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> This introduces bindings and dt-schema for the Google tensor SoCs.
> Currently just gs101 and pixel 6 are supported.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/arm/google.yaml       | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml
> new file mode 100644
> index 000000000000..167945e4d5ee
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/google.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/google.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google Tensor platforms
> +
> +maintainers:
> +  - Peter Griffin <peter.griffin@linaro.org>
> +
> +description: |
> +  ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
> +  devices.
> +
> +  Currently upstream this is devices using "gs101" SoC which is found in Pixel
> +  6, Pixel 6 Pro and Pixel 6a.
> +
> +  Google have a few different names for the SoC.
> +  - Marketing name ("Tensor")
> +  - Codename ("Whitechapel")
> +  - SoC ID ("gs101")
> +  - Die ID ("S5P9845");
> +
> +  Likewise there are a couple of names for the actual device
> +  - Marketing name ("Pixel 6")
> +  - Codename ("Oriole")
> +
> +  Devicetrees should use the lowercased SoC ID and lowercased board codename.
> +  e.g. gs101 and gs101-oriole
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +

Is that empty line is actually needed here?

> +      - description: Google Pixel 6 / Oriole
> +        items:
> +          - enum:
> +              - google,gs101-oriole
> +          - const: google,gs101
> +
> +additionalProperties: true
> +
> +...
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 06/20] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add the "google,gs101-pinctrl" compatible to the dt-schema bindings
> documentation.
>
> Add maxItems of 50 for the interrupts property as gs101 can have
> multiple irqs.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  .../bindings/pinctrl/samsung,pinctrl.yaml     | 22 ++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> index 26614621774a..6dc648490668 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> @@ -35,6 +35,7 @@ properties:
>
>    compatible:
>      enum:
> +      - google,gs101-pinctrl
>        - samsung,s3c2412-pinctrl
>        - samsung,s3c2416-pinctrl
>        - samsung,s3c2440-pinctrl
> @@ -58,7 +59,8 @@ properties:
>    interrupts:
>      description:
>        Required for GPIO banks supporting external GPIO interrupts.
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 50
>
>    power-domains:
>      maxItems: 1
> @@ -134,6 +136,24 @@ allOf:
>            minItems: 1
>            maxItems: 1
>
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-pinctrl
> +    then:
> +      properties:
> +        interrupts:
> +          description:
> +            Required for external wakeup interrupts. List all external
> +            wakeup interrupts supported by this bank.
> +          minItems: 1
> +          maxItems: 50
> +    else:
> +      properties:
> +        interrupts:
> +          maxItems: 1
> +
>  additionalProperties: false
>
>  examples:
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 08/20] dt-bindings: serial: samsung: Add google-gs101-uart compatible

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add dedicated google-gs101-uart compatible to the dt-schema for
> representing uart of the Google Tensor gs101 SoC.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> index 8bd88d5cbb11..6e807b1b4d8c 100644
> --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> @@ -24,6 +24,7 @@ properties:
>        - enum:
>            - apple,s5l-uart
>            - axis,artpec8-uart
> +          - google,gs101-uart
>            - samsung,s3c2410-uart
>            - samsung,s3c2412-uart
>            - samsung,s3c2440-uart
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 09/20] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> These plls are found in the Tensor gs101 SoC found in the Pixel 6.
>
> pll0516x: Integer PLL with high frequency
> pll0517x: Integer PLL with middle frequency
> pll0518x: Integer PLL with low frequency
>
> PLL0516x
> FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
>
> PLL0517x and PLL0518x
> FOUT = (MDIV * FIN)/PDIV*2^SDIV)
>
> The PLLs are similar enough to pll_0822x that the same code can handle
> both. The main difference is the change in the fout formula for the
> high frequency 0516 pll.
>
> Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
>
> When defining the PLL the "con" parameter should be set to CON3
> register, like this
>
> PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
>     PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
>     NULL),
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/clk/samsung/clk-pll.c | 9 ++++++++-
>  drivers/clk/samsung/clk-pll.h | 3 +++
>  2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 74934c6182ce..4ef9fea2a425 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
>         pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
>         sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
>
> -       fvco *= mdiv;
> +       if (pll->type == pll_0516x)
> +               fvco = fvco * 2 * mdiv;
> +       else
> +               fvco *= mdiv;
> +

Can be written like this I guess:

       fvco *= mdiv;
       if (pll->type == pll_0516x)
              fvco *= 2;

if you think it's more neat. Other than that:

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>         do_div(fvco, (pdiv << sdiv));
>
>         return (unsigned long)fvco;
> @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>         case pll_1417x:
>         case pll_0818x:
>         case pll_0822x:
> +       case pll_0516x:
> +       case pll_0517x:
> +       case pll_0518x:
>                 pll->enable_offs = PLL0822X_ENABLE_SHIFT;
>                 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
>                 if (!pll->rate_table)
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 0725d485c6ee..ffd3d52c0dec 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -38,6 +38,9 @@ enum samsung_pll_type {
>         pll_0822x,
>         pll_0831x,
>         pll_142xx,
> +       pll_0516x,
> +       pll_0517x,
> +       pll_0518x,
>  };
>
>  #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
> --
> 2.42.0.655.g421f12c284-goog
>
>

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> CMU_TOP is the top level clock management unit which contains PLLs, muxes
> and gates that feed the other clock management units.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/clk/samsung/Kconfig     |    9 +
>  drivers/clk/samsung/Makefile    |    2 +
>  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
>  3 files changed, 1562 insertions(+)
>  create mode 100644 drivers/clk/samsung/clk-gs101.c
>
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..14362ec9c543 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
>         select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
>         select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
>         select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> +       select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
>         select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
>
>  config S3C64XX_COMMON_CLK
> @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
>           status of the certains clocks from SoC, but it could also be tied to
>           other devices as an input clock.
>
> +config GOOGLE_GS101_COMMON_CLK
> +       bool "Google gs101 clock controller support" if COMPILE_TEST
> +       depends on COMMON_CLK_SAMSUNG
> +       depends on EXYNOS_ARM64_COMMON_CLK
> +       help
> +         Support for the clock controller present on the Google gs101 SoC.
> +         Choose Y here only if you build for this SoC.
> +

Why is that new option needed? From the look of it, it could be just a
part of EXYNOS_ARM64_COMMON_CLK. Like clk-exynos850 or
clk-exynosautov9. Is there any particular feature that makes it SoC
special?

>  config TESLA_FSD_COMMON_CLK
>         bool "Tesla FSD clock controller support" if COMPILE_TEST
>         depends on COMMON_CLK_SAMSUNG
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index ebbeacabe88f..49146937d957 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -21,6 +21,8 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynos7885.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynos850.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynosautov9.o
> +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK)  += clk-gs101.o
>  obj-$(CONFIG_S3C64XX_COMMON_CLK)       += clk-s3c64xx.o
>  obj-$(CONFIG_S5PV210_COMMON_CLK)       += clk-s5pv210.o clk-s5pv210-audss.o
>  obj-$(CONFIG_TESLA_FSD_COMMON_CLK)     += clk-fsd.o
> +
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> new file mode 100644
> index 000000000000..e2c62754b1eb
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -0,0 +1,1551 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <peter.griffin@linaro.org>
> + *
> + * Common Clock Framework support for GS101.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/google,gs101.h>
> +
> +#include "clk.h"
> +#include "clk-exynos-arm64.h"
> +
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)

Please use tab for indentations like that. In this and subsequent patches.

> +
> +/* ---- CMU_TOP ------------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_TOP (0x1e080000) */
> +
> +#define PLL_LOCKTIME_PLL_SHARED0                       0x0000
> +#define PLL_LOCKTIME_PLL_SHARED1                       0x0004
> +#define PLL_LOCKTIME_PLL_SHARED2                       0x0008
> +#define PLL_LOCKTIME_PLL_SHARED3                       0x000c
> +#define PLL_LOCKTIME_PLL_SPARE                         0x0010
> +#define PLL_CON0_PLL_SHARED0                           0x0100
> +#define PLL_CON1_PLL_SHARED0                           0x0104
> +#define PLL_CON2_PLL_SHARED0                           0x0108
> +#define PLL_CON3_PLL_SHARED0                           0x010c
> +#define PLL_CON4_PLL_SHARED0                           0x0110
> +#define PLL_CON0_PLL_SHARED1                           0x0140
> +#define PLL_CON1_PLL_SHARED1                           0x0144
> +#define PLL_CON2_PLL_SHARED1                           0x0148
> +#define PLL_CON3_PLL_SHARED1                           0x014c
> +#define PLL_CON4_PLL_SHARED1                           0x0150
> +#define PLL_CON0_PLL_SHARED2                           0x0180
> +#define PLL_CON1_PLL_SHARED2                           0x0184
> +#define PLL_CON2_PLL_SHARED2                           0x0188
> +#define PLL_CON3_PLL_SHARED2                           0x018c
> +#define PLL_CON4_PLL_SHARED2                           0x0190
> +#define PLL_CON0_PLL_SHARED3                           0x01c0
> +#define PLL_CON1_PLL_SHARED3                           0x01c4
> +#define PLL_CON2_PLL_SHARED3                           0x01c8
> +#define PLL_CON3_PLL_SHARED3                           0x01cc
> +#define PLL_CON4_PLL_SHARED3                           0x01d0
> +#define PLL_CON0_PLL_SPARE                             0x0200
> +#define PLL_CON1_PLL_SPARE                             0x0204
> +#define PLL_CON2_PLL_SPARE                             0x0208
> +#define PLL_CON3_PLL_SPARE                             0x020c
> +#define PLL_CON4_PLL_SPARE                             0x0210
> +#define CMU_CMU_TOP_CONTROLLER_OPTION                  0x0800
> +#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0             0x0810
> +#define CMU_HCHGEN_CLKMUX_CMU_BOOST                    0x0840
> +#define CMU_HCHGEN_CLKMUX_TOP_BOOST                    0x0844
> +#define CMU_HCHGEN_CLKMUX                              0x0850
> +#define POWER_FAIL_DETECT_PLL                          0x0864
> +#define EARLY_WAKEUP_FORCED_0_ENABLE                   0x0870
> +#define EARLY_WAKEUP_FORCED_1_ENABLE                   0x0874
> +#define EARLY_WAKEUP_APM_CTRL                          0x0878
> +#define EARLY_WAKEUP_CLUSTER0_CTRL                     0x087c
> +#define EARLY_WAKEUP_DPU_CTRL                          0x0880
> +#define EARLY_WAKEUP_CSIS_CTRL                         0x0884
> +#define EARLY_WAKEUP_APM_DEST                          0x0890
> +#define EARLY_WAKEUP_CLUSTER0_DEST                     0x0894
> +#define EARLY_WAKEUP_DPU_DEST                          0x0898
> +#define EARLY_WAKEUP_CSIS_DEST                         0x089c
> +#define EARLY_WAKEUP_SW_TRIG_APM                       0x08c0
> +#define EARLY_WAKEUP_SW_TRIG_APM_SET                   0x08c4
> +#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR                 0x08c8
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0                  0x08d0
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET              0x08d4
> +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR            0x08d8
> +#define EARLY_WAKEUP_SW_TRIG_DPU                       0x08e0
> +#define EARLY_WAKEUP_SW_TRIG_DPU_SET                   0x08e4
> +#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR                 0x08e8
> +#define EARLY_WAKEUP_SW_TRIG_CSIS                      0x08f0
> +#define EARLY_WAKEUP_SW_TRIG_CSIS_SET                  0x08f4
> +#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR                        0x08f8
> +
> +#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS                  0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS                        0x1004
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS                        0x1008
> +#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS                        0x100c
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0                        0x1010
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1                        0x1014
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2                        0x1018
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3                        0x101c
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4                        0x1020
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5                        0x1024
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6                        0x1028
> +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7                        0x102c
> +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST               0x1030
> +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1       0x1034
> +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS                        0x1038
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG              0x103c
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH           0x1040
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH           0x1044
> +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH           0x1048
> +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS                        0x104c
> +#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS                        0x1050
> +#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS                 0x1054
> +#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS                 0x1058
> +#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS                  0x105c
> +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D                 0x1060
> +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL                        0x1064
> +#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA               0x1068
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD                        0x106c
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB                 0x1070
> +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH              0x1074
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0                        0x1078
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1                        0x107c
> +#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC                        0x1080
> +#define CLK_CON_MUX_MUX_CLKCMU_HPM                     0x1084
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS                        0x1088
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC              0x108c
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD           0x1090
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG           0x1094
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS                        0x1098
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE               0x109c
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS                        0x10a0
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD           0x10a4
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE               0x10a8
> +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD           0x10ac
> +#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS                 0x10b0
> +#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS                 0x10b4
> +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC               0x10b8
> +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC               0x10bc
> +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC                 0x10c0
> +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP                        0x10c4
> +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH              0x10c8
> +#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS                        0x10cc
> +#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS                        0x10d0
> +#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS                 0x10d4
> +#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA                 0x10d8
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS              0x10dc
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP               0x10e0
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS              0x10e4
> +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP               0x10e8
> +#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS                 0x10ec
> +#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1       0x10f0
> +#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF              0x10f4
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS                 0x10f8
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU                 0x10fc
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL              0x1100
> +#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART                        0x1104
> +#define CLK_CON_MUX_MUX_CMU_CMUREF                     0x1108
> +
> +#define CLK_CON_DIV_CLKCMU_BO_BUS                      0x1800
> +#define CLK_CON_DIV_CLKCMU_BUS0_BUS                    0x1804
> +#define CLK_CON_DIV_CLKCMU_BUS1_BUS                    0x1808
> +#define CLK_CON_DIV_CLKCMU_BUS2_BUS                    0x180c
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK0                    0x1810
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK1                    0x1814
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK2                    0x1818
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK3                    0x181c
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK4                    0x1820
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK5                    0x1824
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK6                    0x1828
> +#define CLK_CON_DIV_CLKCMU_CIS_CLK7                    0x182c
> +#define CLK_CON_DIV_CLKCMU_CORE_BUS                    0x1830
> +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG                  0x1834
> +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH               0x1838
> +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH               0x183c
> +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH               0x1840
> +#define CLK_CON_DIV_CLKCMU_CSIS_BUS                    0x1844
> +#define CLK_CON_DIV_CLKCMU_DISP_BUS                    0x1848
> +#define CLK_CON_DIV_CLKCMU_DNS_BUS                     0x184c
> +#define CLK_CON_DIV_CLKCMU_DPU_BUS                     0x1850
> +#define CLK_CON_DIV_CLKCMU_EH_BUS                      0x1854
> +#define CLK_CON_DIV_CLKCMU_G2D_G2D                     0x1858
> +#define CLK_CON_DIV_CLKCMU_G2D_MSCL                    0x185c
> +#define CLK_CON_DIV_CLKCMU_G3AA_G3AA                   0x1860
> +#define CLK_CON_DIV_CLKCMU_G3D_BUSD                    0x1864
> +#define CLK_CON_DIV_CLKCMU_G3D_GLB                     0x1868
> +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH                  0x186c
> +#define CLK_CON_DIV_CLKCMU_GDC_GDC0                    0x1870
> +#define CLK_CON_DIV_CLKCMU_GDC_GDC1                    0x1874
> +#define CLK_CON_DIV_CLKCMU_GDC_SCSC                    0x1878
> +#define CLK_CON_DIV_CLKCMU_HPM                         0x187c
> +#define CLK_CON_DIV_CLKCMU_HSI0_BUS                    0x1880
> +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC                  0x1884
> +#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD               0x1888
> +#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG               0x188c
> +#define CLK_CON_DIV_CLKCMU_HSI1_BUS                    0x1890
> +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE                   0x1894
> +#define CLK_CON_DIV_CLKCMU_HSI2_BUS                    0x1898
> +#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD               0x189c
> +#define CLK_CON_DIV_CLKCMU_HSI2_PCIE                   0x18a0
> +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD               0x18a4
> +#define CLK_CON_DIV_CLKCMU_IPP_BUS                     0x18a8
> +#define CLK_CON_DIV_CLKCMU_ITP_BUS                     0x18ac
> +#define CLK_CON_DIV_CLKCMU_MCSC_ITSC                   0x18b0
> +#define CLK_CON_DIV_CLKCMU_MCSC_MCSC                   0x18b4
> +#define CLK_CON_DIV_CLKCMU_MFC_MFC                     0x18b8
> +#define CLK_CON_DIV_CLKCMU_MIF_BUSP                    0x18bc
> +#define CLK_CON_DIV_CLKCMU_MISC_BUS                    0x18c0
> +#define CLK_CON_DIV_CLKCMU_MISC_SSS                    0x18c4
> +#define CLK_CON_DIV_CLKCMU_OTP                         0x18c8
> +#define CLK_CON_DIV_CLKCMU_PDP_BUS                     0x18cc
> +#define CLK_CON_DIV_CLKCMU_PDP_VRA                     0x18d0
> +#define CLK_CON_DIV_CLKCMU_PERIC0_BUS                  0x18d4
> +#define CLK_CON_DIV_CLKCMU_PERIC0_IP                   0x18d8
> +#define CLK_CON_DIV_CLKCMU_PERIC1_BUS                  0x18dc
> +#define CLK_CON_DIV_CLKCMU_PERIC1_IP                   0x18e0
> +#define CLK_CON_DIV_CLKCMU_TNR_BUS                     0x18e4
> +#define CLK_CON_DIV_CLKCMU_TPU_BUS                     0x18e8
> +#define CLK_CON_DIV_CLKCMU_TPU_TPU                     0x18ec
> +#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL                  0x18f0
> +#define CLK_CON_DIV_CLKCMU_TPU_UART                    0x18f4
> +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST               0x18f8
> +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF                 0x18fc
> +#define CLK_CON_DIV_PLL_SHARED0_DIV2                   0x1900
> +#define CLK_CON_DIV_PLL_SHARED0_DIV3                   0x1904
> +#define CLK_CON_DIV_PLL_SHARED0_DIV4                   0x1908
> +#define CLK_CON_DIV_PLL_SHARED0_DIV5                   0x190c
> +#define CLK_CON_DIV_PLL_SHARED1_DIV2                   0x1910
> +#define CLK_CON_DIV_PLL_SHARED1_DIV3                   0x1914
> +#define CLK_CON_DIV_PLL_SHARED1_DIV4                   0x1918
> +#define CLK_CON_DIV_PLL_SHARED2_DIV2                   0x191c
> +#define CLK_CON_DIV_PLL_SHARED3_DIV2                   0x1920
> +
> +/* CLK_CON_GAT_UPDATES */
> +#define CLK_CON_GAT_CLKCMU_BUS0_BOOST                  0x2000
> +#define CLK_CON_GAT_CLKCMU_BUS1_BOOST                  0x2004
> +#define CLK_CON_GAT_CLKCMU_BUS2_BOOST                  0x2008
> +#define CLK_CON_GAT_CLKCMU_CORE_BOOST                  0x200c
> +#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST                        0x2010
> +#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST                        0x2014
> +#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST                        0x2018
> +#define CLK_CON_GAT_CLKCMU_MIF_BOOST                   0x201c
> +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH                  0x2020
> +#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS                 0x2024
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS               0x2028
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS               0x202c
> +#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS               0x2030
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0               0x2034
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1               0x2038
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2               0x203c
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3               0x2040
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4               0x2044
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5               0x2048
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6               0x204c
> +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7               0x2050
> +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST              0x2054
> +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS               0x2058
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS         0x205c
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH          0x2060
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH          0x2064
> +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH          0x2068
> +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS               0x206c
> +#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS               0x2070
> +#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS                        0x2074
> +#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS                        0x2078
> +#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS                 0x207c
> +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D                        0x2080
> +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL               0x2084
> +#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA              0x2088
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD               0x208c
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB                        0x2090
> +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH             0x2094
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0               0x2098
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1               0x209c
> +#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC               0x20a0
> +#define CLK_CON_GAT_GATE_CLKCMU_HPM                    0x20a4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS               0x20a8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC             0x20ac
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD          0x20b0
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG          0x20b4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS               0x20b8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE              0x20bc
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS               0x20c0
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD           0x20c4
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE              0x20c8
> +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD          0x20cc
> +#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS                        0x20d0
> +#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS                        0x20d4
> +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC              0x20d8
> +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC              0x20dc
> +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC                        0x20e0
> +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP               0x20e4
> +#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS               0x20e8
> +#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS               0x20ec
> +#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS                        0x20f0
> +#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA                        0x20f4
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS             0x20f8
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP              0x20fc
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS             0x2100
> +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP              0x2104
> +#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS                        0x2108
> +#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF             0x210c
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS                        0x2110
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU                        0x2114
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL             0x2118
> +#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART               0x211c
> +
> +#define DMYQCH_CON_CMU_TOP_CMUREF_QCH                  0x3000
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0             0x3004
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1             0x3008
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2             0x300c
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3             0x3010
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4             0x3014
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5             0x3018
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6             0x301c
> +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7             0x3020
> +#define DMYQCH_CON_OTP_QCH                             0x3024
> +#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP                 0x3c00
> +#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP                   0x3c10
> +#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP                   0x3c14
> +#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP                   0x3c18
> +#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP                   0x3c1c
> +#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP                   0x3c20
> +#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP                   0x3c24
> +#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP                   0x3c28
> +#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP                   0x3c2c
> +#define MIFMIRROR_QUEUE_CTRL_REG                       0x3e00
> +#define MIFMIRROR_QUEUE_ENTRY0                         0x3e10
> +#define MIFMIRROR_QUEUE_ENTRY1                         0x3e14
> +#define MIFMIRROR_QUEUE_ENTRY2                         0x3e18
> +#define MIFMIRROR_QUEUE_ENTRY3                         0x3e1c
> +#define MIFMIRROR_QUEUE_ENTRY4                         0x3e20
> +#define MIFMIRROR_QUEUE_ENTRY5                         0x3e24
> +#define MIFMIRROR_QUEUE_ENTRY6                         0x3e28
> +#define MIFMIRROR_QUEUE_ENTRY7                         0x3e2c
> +#define MIFMIRROR_QUEUE_BUSY                           0x3e30
> +#define GENERALIO_ACD_CHANNEL_0                                0x3f00
> +#define GENERALIO_ACD_CHANNEL_1                                0x3f04
> +#define GENERALIO_ACD_CHANNEL_2                                0x3f08
> +#define GENERALIO_ACD_CHANNEL_3                                0x3f0c
> +#define GENERALIO_ACD_MASK                             0x3f14
> +
> +static const unsigned long cmu_top_clk_regs[] __initconst = {
> +       PLL_LOCKTIME_PLL_SHARED0,
> +       PLL_LOCKTIME_PLL_SHARED1,
> +       PLL_LOCKTIME_PLL_SHARED2,
> +       PLL_LOCKTIME_PLL_SHARED3,
> +       PLL_LOCKTIME_PLL_SPARE,
> +       PLL_CON0_PLL_SHARED0,
> +       PLL_CON1_PLL_SHARED0,
> +       PLL_CON2_PLL_SHARED0,
> +       PLL_CON3_PLL_SHARED0,
> +       PLL_CON4_PLL_SHARED0,
> +       PLL_CON0_PLL_SHARED1,
> +       PLL_CON1_PLL_SHARED1,
> +       PLL_CON2_PLL_SHARED1,
> +       PLL_CON3_PLL_SHARED1,
> +       PLL_CON4_PLL_SHARED1,
> +       PLL_CON0_PLL_SHARED2,
> +       PLL_CON1_PLL_SHARED2,
> +       PLL_CON2_PLL_SHARED2,
> +       PLL_CON3_PLL_SHARED2,
> +       PLL_CON4_PLL_SHARED2,
> +       PLL_CON0_PLL_SHARED3,
> +       PLL_CON1_PLL_SHARED3,
> +       PLL_CON2_PLL_SHARED3,
> +       PLL_CON3_PLL_SHARED3,
> +       PLL_CON4_PLL_SHARED3,
> +       PLL_CON0_PLL_SPARE,
> +       PLL_CON1_PLL_SPARE,
> +       PLL_CON2_PLL_SPARE,
> +       PLL_CON3_PLL_SPARE,
> +       PLL_CON4_PLL_SPARE,
> +       CMU_CMU_TOP_CONTROLLER_OPTION,
> +       CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
> +       CMU_HCHGEN_CLKMUX_CMU_BOOST,
> +       CMU_HCHGEN_CLKMUX_TOP_BOOST,
> +       CMU_HCHGEN_CLKMUX,
> +       POWER_FAIL_DETECT_PLL,
> +       EARLY_WAKEUP_FORCED_0_ENABLE,
> +       EARLY_WAKEUP_FORCED_1_ENABLE,
> +       EARLY_WAKEUP_APM_CTRL,
> +       EARLY_WAKEUP_CLUSTER0_CTRL,
> +       EARLY_WAKEUP_DPU_CTRL,
> +       EARLY_WAKEUP_CSIS_CTRL,
> +       EARLY_WAKEUP_APM_DEST,
> +       EARLY_WAKEUP_CLUSTER0_DEST,
> +       EARLY_WAKEUP_DPU_DEST,
> +       EARLY_WAKEUP_CSIS_DEST,
> +       EARLY_WAKEUP_SW_TRIG_APM,
> +       EARLY_WAKEUP_SW_TRIG_APM_SET,
> +       EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
> +       EARLY_WAKEUP_SW_TRIG_CLUSTER0,
> +       EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
> +       EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
> +       EARLY_WAKEUP_SW_TRIG_DPU,
> +       EARLY_WAKEUP_SW_TRIG_DPU_SET,
> +       EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
> +       EARLY_WAKEUP_SW_TRIG_CSIS,
> +       EARLY_WAKEUP_SW_TRIG_CSIS_SET,
> +       EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
> +       CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
> +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
> +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
> +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
> +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
> +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
> +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
> +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
> +       CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
> +       CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
> +       CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
> +       CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
> +       CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
> +       CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
> +       CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
> +       CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
> +       CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
> +       CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
> +       CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
> +       CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
> +       CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
> +       CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
> +       CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
> +       CLK_CON_MUX_MUX_CLKCMU_HPM,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
> +       CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
> +       CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
> +       CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
> +       CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
> +       CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
> +       CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
> +       CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
> +       CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
> +       CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
> +       CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
> +       CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
> +       CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
> +       CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
> +       CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
> +       CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
> +       CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
> +       CLK_CON_MUX_MUX_CMU_CMUREF,
> +       CLK_CON_DIV_CLKCMU_BO_BUS,
> +       CLK_CON_DIV_CLKCMU_BUS0_BUS,
> +       CLK_CON_DIV_CLKCMU_BUS1_BUS,
> +       CLK_CON_DIV_CLKCMU_BUS2_BUS,
> +       CLK_CON_DIV_CLKCMU_CIS_CLK0,
> +       CLK_CON_DIV_CLKCMU_CIS_CLK1,
> +       CLK_CON_DIV_CLKCMU_CIS_CLK2,
> +       CLK_CON_DIV_CLKCMU_CIS_CLK3,
> +       CLK_CON_DIV_CLKCMU_CIS_CLK4,
> +       CLK_CON_DIV_CLKCMU_CIS_CLK5,
> +       CLK_CON_DIV_CLKCMU_CIS_CLK6,
> +       CLK_CON_DIV_CLKCMU_CIS_CLK7,
> +       CLK_CON_DIV_CLKCMU_CORE_BUS,
> +       CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
> +       CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
> +       CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
> +       CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
> +       CLK_CON_DIV_CLKCMU_CSIS_BUS,
> +       CLK_CON_DIV_CLKCMU_DISP_BUS,
> +       CLK_CON_DIV_CLKCMU_DNS_BUS,
> +       CLK_CON_DIV_CLKCMU_DPU_BUS,
> +       CLK_CON_DIV_CLKCMU_EH_BUS,
> +       CLK_CON_DIV_CLKCMU_G2D_G2D,
> +       CLK_CON_DIV_CLKCMU_G2D_MSCL,
> +       CLK_CON_DIV_CLKCMU_G3AA_G3AA,
> +       CLK_CON_DIV_CLKCMU_G3D_BUSD,
> +       CLK_CON_DIV_CLKCMU_G3D_GLB,
> +       CLK_CON_DIV_CLKCMU_G3D_SWITCH,
> +       CLK_CON_DIV_CLKCMU_GDC_GDC0,
> +       CLK_CON_DIV_CLKCMU_GDC_GDC1,
> +       CLK_CON_DIV_CLKCMU_GDC_SCSC,
> +       CLK_CON_DIV_CLKCMU_HPM,
> +       CLK_CON_DIV_CLKCMU_HSI0_BUS,
> +       CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
> +       CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
> +       CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
> +       CLK_CON_DIV_CLKCMU_HSI1_BUS,
> +       CLK_CON_DIV_CLKCMU_HSI1_PCIE,
> +       CLK_CON_DIV_CLKCMU_HSI2_BUS,
> +       CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
> +       CLK_CON_DIV_CLKCMU_HSI2_PCIE,
> +       CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
> +       CLK_CON_DIV_CLKCMU_IPP_BUS,
> +       CLK_CON_DIV_CLKCMU_ITP_BUS,
> +       CLK_CON_DIV_CLKCMU_MCSC_ITSC,
> +       CLK_CON_DIV_CLKCMU_MCSC_MCSC,
> +       CLK_CON_DIV_CLKCMU_MFC_MFC,
> +       CLK_CON_DIV_CLKCMU_MIF_BUSP,
> +       CLK_CON_DIV_CLKCMU_MISC_BUS,
> +       CLK_CON_DIV_CLKCMU_MISC_SSS,
> +       CLK_CON_DIV_CLKCMU_OTP,
> +       CLK_CON_DIV_CLKCMU_PDP_BUS,
> +       CLK_CON_DIV_CLKCMU_PDP_VRA,
> +       CLK_CON_DIV_CLKCMU_PERIC0_BUS,
> +       CLK_CON_DIV_CLKCMU_PERIC0_IP,
> +       CLK_CON_DIV_CLKCMU_PERIC1_BUS,
> +       CLK_CON_DIV_CLKCMU_PERIC1_IP,
> +       CLK_CON_DIV_CLKCMU_TNR_BUS,
> +       CLK_CON_DIV_CLKCMU_TPU_BUS,
> +       CLK_CON_DIV_CLKCMU_TPU_TPU,
> +       CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
> +       CLK_CON_DIV_CLKCMU_TPU_UART,
> +       CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
> +       CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
> +       CLK_CON_DIV_PLL_SHARED0_DIV2,
> +       CLK_CON_DIV_PLL_SHARED0_DIV3,
> +       CLK_CON_DIV_PLL_SHARED0_DIV4,
> +       CLK_CON_DIV_PLL_SHARED0_DIV5,
> +       CLK_CON_DIV_PLL_SHARED1_DIV2,
> +       CLK_CON_DIV_PLL_SHARED1_DIV3,
> +       CLK_CON_DIV_PLL_SHARED1_DIV4,
> +       CLK_CON_DIV_PLL_SHARED2_DIV2,
> +       CLK_CON_DIV_PLL_SHARED3_DIV2,
> +       CLK_CON_GAT_CLKCMU_BUS0_BOOST,
> +       CLK_CON_GAT_CLKCMU_BUS1_BOOST,
> +       CLK_CON_GAT_CLKCMU_BUS2_BOOST,
> +       CLK_CON_GAT_CLKCMU_CORE_BOOST,
> +       CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
> +       CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
> +       CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
> +       CLK_CON_GAT_CLKCMU_MIF_BOOST,
> +       CLK_CON_GAT_CLKCMU_MIF_SWITCH,
> +       CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
> +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
> +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
> +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
> +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
> +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
> +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
> +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
> +       CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
> +       CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
> +       CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
> +       CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
> +       CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
> +       CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
> +       CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
> +       CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
> +       CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
> +       CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
> +       CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
> +       CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
> +       CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
> +       CLK_CON_GAT_GATE_CLKCMU_HPM,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
> +       CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
> +       CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
> +       CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
> +       CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
> +       CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
> +       CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
> +       CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
> +       CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
> +       CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
> +       CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
> +       CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
> +       CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
> +       CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
> +       CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
> +       DMYQCH_CON_CMU_TOP_CMUREF_QCH,
> +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
> +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
> +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
> +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
> +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
> +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
> +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
> +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
> +       DMYQCH_CON_OTP_QCH,
> +       QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
> +       QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
> +       QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
> +       QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
> +       QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
> +       QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
> +       QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
> +       QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
> +       QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
> +       MIFMIRROR_QUEUE_CTRL_REG,
> +       MIFMIRROR_QUEUE_ENTRY0,
> +       MIFMIRROR_QUEUE_ENTRY1,
> +       MIFMIRROR_QUEUE_ENTRY2,
> +       MIFMIRROR_QUEUE_ENTRY3,
> +       MIFMIRROR_QUEUE_ENTRY4,
> +       MIFMIRROR_QUEUE_ENTRY5,
> +       MIFMIRROR_QUEUE_ENTRY6,
> +       MIFMIRROR_QUEUE_ENTRY7,
> +       MIFMIRROR_QUEUE_BUSY,
> +       GENERALIO_ACD_CHANNEL_0,
> +       GENERALIO_ACD_CHANNEL_1,
> +       GENERALIO_ACD_CHANNEL_2,
> +       GENERALIO_ACD_CHANNEL_3,
> +       GENERALIO_ACD_MASK,
> +};
> +
> +static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
> +       /* CMU_TOP_PURECLKCOMP */
> +       PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> +           NULL),
> +       PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
> +           NULL),
> +       PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
> +           NULL),
> +       PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
> +           NULL),
> +       PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
> +           NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_TOP */
> +PNAME(mout_shared0_pll_p)      = { "oscclk", "fout_shared0_pll" };
> +PNAME(mout_shared1_pll_p)      = { "oscclk", "fout_shared1_pll" };
> +PNAME(mout_shared2_pll_p)      = { "oscclk", "fout_shared2_pll" };
> +PNAME(mout_shared3_pll_p)      = { "oscclk", "fout_shared3_pll" };
> +PNAME(mout_spare_pll_p)                = { "oscclk", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */
> +PNAME(mout_cmu_bus0_bus_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> +                                   "dout_shared2_div2", "dout_shared3_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_cmu_boost_p)    = { "dout_shared0_div4", "dout_shared1_div4",
> +                                   "dout_shared2_div2", "dout_shared3_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */
> +PNAME(mout_cmu_bus1_bus_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */
> +PNAME(mout_cmu_bus2_bus_p)     = { "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div3", "dout_shared1_div3",
> +                                   "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
> +PNAME(mout_cmu_core_bus_p)     = { "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div3", "dout_shared1_div3",
> +                                   "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */
> +PNAME(mout_cmu_eh_bus_p)       = { "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div3", "dout_shared1_div3",
> +                                   "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */
> +PNAME(mout_cmu_cpucl2_switch_p)        = { "fout_shared1_pll", "dout_shared0_div2",
> +                                   "dout_shared1_div2", "fout_shared2_pll",
> +                                   "fout_shared3_pll", "dout_shared0_div3",
> +                                   "dout_shared1_div3", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
> +PNAME(mout_cmu_cpucl1_switch_p)        = { "fout_shared1_pll", "dout_shared0_div2",
> +                                   "dout_shared1_div2", "fout_shared2_pll",
> +                                   "fout_shared3_pll", "dout_shared0_div3",
> +                                   "dout_shared1_div3", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
> +PNAME(mout_cmu_cpucl0_switch_p)        = { "fout_shared1_pll", "dout_shared0_div2",
> +                                   "dout_shared1_div2", "fout_shared2_pll",
> +                                   "fout_shared3_pll", "dout_shared0_div3",
> +                                   "dout_shared1_div3", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_cpucl0_dbg_p)   = { "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div4", "dout_shared1_div4",
> +                                   "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hpm_p)          = { "oscclk", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
> +PNAME(mout_cmu_g3d_switch_p)   = { "fout_shared2_pll", "dout_shared0_div3",
> +                                   "fout_shared3_pll", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "dout_shared1_div4",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g3d_busd_p)     = { "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div3", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g3d_glb_p)      = { "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div3", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
> +PNAME(mout_cmu_dpu_p)          = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */
> +PNAME(mout_cmu_disp_bus_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> +PNAME(mout_cmu_g2d_g2d_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_g2d_mscl_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> +                                   "dout_shared2_div2", "dout_shared3_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */
> +PNAME(mout_cmu_hsi0_usb31drd_p)        = { "oscclk", "dout_shared2_div2" };
> +
> +PNAME(mout_cmu_hsi0_bus_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> +                                   "dout_shared2_div2", "dout_shared3_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi0_dpgtc_p)   = { "oscclk", "dout_shared0_div4",
> +                                   "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi0_usbdpdbg_p)        = { "oscclk", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */
> +PNAME(mout_cmu_hsi1_bus_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> +                                   "dout_shared2_div2", "dout_shared3_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi1_pcie_p)    = { "oscclk", "dout_shared2_div2" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */
> +PNAME(mout_cmu_hsi2_bus_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> +                                   "dout_shared2_div2", "dout_shared3_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi2_pcie0_p)   = { "oscclk", "dout_shared2_div2" };
> +
> +PNAME(mout_cmu_hsi2_ufs_embd_p)        = { "oscclk", "dout_shared0_div4",
> +                                   "dout_shared2_div2", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_hsi2_mmc_card_p)        = { "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div4", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
> +PNAME(mout_cmu_csis_bus_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
> +PNAME(mout_cmu_pdp_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_pdp_vra_p)      = { "fout_shared2_pll", "dout_shared0_div3",
> +                                   "fout_shared3_pll", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "dout_shared1_div4",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
> +PNAME(mout_cmu_ipp_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
> +PNAME(mout_cmu_g3aa_p)         = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
> +PNAME(mout_cmu_itp_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
> +PNAME(mout_cmu_dns_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
> +PNAME(mout_cmu_tnr_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
> +PNAME(mout_cmu_mcsc_itsc_p)    = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_mcsc_mcsc_p)    = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
> +PNAME(mout_cmu_gdc_scsc_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_gdc_gdc0_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +PNAME(mout_cmu_gdc_gdc1_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
> +PNAME(mout_cmu_mfc_mfc_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> +                                   "dout_shared1_div3", "dout_shared0_div4",
> +                                   "dout_shared1_div4", "dout_shared2_div2",
> +                                   "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
> +
> +PNAME(mout_cmu_mif_switch_p)   = { "fout_shared0_pll", "fout_shared1_pll",
> +                                   "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "dout_shared0_div3",
> +                                   "fout_shared3_pll", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
> +PNAME(mout_cmu_mif_busp_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> +                                   "dout_shared0_div5", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
> +PNAME(mout_cmu_misc_bus_p)     = { "dout_shared0_div4", "dout_shared2_div2",
> +                                   "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_misc_sss_p)     = { "dout_shared0_div4", "dout_shared2_div2",
> +                                   "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
> +PNAME(mout_cmu_peric0_bus_p)   = { "dout_shared0_div4", "dout_shared2_div2",
> +                                   "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_peric0_ip_p)    = { "dout_shared0_div4", "dout_shared2_div2",
> +                                   "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
> +PNAME(mout_cmu_peric1_bus_p)   = { "dout_shared0_div4", "dout_shared2_div2",
> +                                   "dout_shared3_div2", "fout_spare_pll" };
> +PNAME(mout_cmu_peric1_ip_p)    = { "dout_shared0_div4", "dout_shared2_div2",
> +                                   "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
> +PNAME(mout_cmu_tpu_tpu_p)      = { "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div3", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_tpuctl_p)   = { "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div3", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_bus_p)      = { "dout_shared0_div2", "dout_shared1_div2",
> +                                   "fout_shared2_pll", "fout_shared3_pll",
> +                                   "dout_shared0_div3", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "fout_spare_pll" };
> +
> +PNAME(mout_cmu_tpu_uart_p)     = { "dout_shared0_div4", "dout_shared2_div2",
> +                                   "dout_shared3_div2", "fout_spare_pll" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
> +PNAME(mout_cmu_bo_bus_p)       = { "fout_shared2_pll", "dout_shared0_div3",
> +                                   "fout_shared3_pll", "dout_shared1_div3",
> +                                   "dout_shared0_div4", "dout_shared1_div4",
> +                                   "fout_spare_pll" };
> +
> +/* gs101 */

Maybe remove this comment.

> +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> +       /* CMU_TOP_PURECLKCOMP */
> +       MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> +           PLL_CON0_PLL_SHARED0, 4, 1),
> +       MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> +           PLL_CON0_PLL_SHARED1, 4, 1),
> +       MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> +           PLL_CON0_PLL_SHARED2, 4, 1),
> +       MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> +           PLL_CON0_PLL_SHARED3, 4, 1),
> +       MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> +           PLL_CON0_PLL_SPARE, 4, 1),
> +
> +       /* BUS0 */
> +       MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> +       MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
> +           CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> +
> +       /* BUS1 */
> +       MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> +
> +       /* BUS2 */
> +       MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> +
> +       /* CORE */
> +       MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> +       /* EH */
> +       MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> +       /* CPUCL{0,1,2,} */
> +       MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,

Here and further: please stick to 80 characters per line when possible.

> +           CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> +
> +       MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> +           CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> +
> +       MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> +           CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> +
> +       MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> +           CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> +
> +       MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
> +
> +       /* G3D */
> +       MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p,
> +           CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
> +
> +       MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
> +           CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2),
> +
> +       MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
> +           CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2),
> +       /* DPU */
> +       MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
> +           CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2),
> +
> +       /* DISP */
> +       MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2),
> +
> +       /* G2D */
> +       MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
> +           CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
> +
> +       MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
> +           CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
> +
> +       /* HSI0 */
> +       MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2),
> +
> +       MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2),
> +
> +       MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
> +
> +       MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2),
> +
> +       /* HSI1 */
> +       MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2),
> +
> +       MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2),
> +       /* HSI2 */
> +       MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
> +
> +       MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
> +
> +       MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2),
> +
> +       MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p,
> +           CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2),
> +
> +       /* CSIS */
> +       MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
> +
> +       /* PDP */
> +       MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> +
> +       /* PDP */
> +       MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
> +           CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
> +
> +       /* IPP */
> +       MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> +
> +       /* G3AA */
> +       MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> +           CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
> +
> +       /* ITP */
> +       MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
> +
> +       /* DNS */
> +       MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
> +
> +       /* TNR */
> +       MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
> +
> +       /* MCSC*/
> +       MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
> +           CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
> +
> +       MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
> +           CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
> +
> +       /* GDC */
> +       MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
> +           CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
> +
> +       MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
> +           CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
> +
> +       MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
> +           CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
> +
> +       /* MFC */
> +       MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
> +           CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
> +
> +       /* DDRPHY0/1/2/3 */
> +       MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
> +           CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
> +
> +       /* MIF0/1/2/3 */
> +       MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
> +           CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
> +
> +       /* MISC */
> +       MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
> +       MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
> +           CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
> +
> +       /* PERI0 */
> +       MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
> +           CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> +       MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> +       /* PERI1 */
> +       MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
> +           CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> +       MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> +
> +       /* TPU */
> +       MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
> +           CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
> +
> +       MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
> +           CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
> +
> +       MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
> +
> +       MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
> +           CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
> +
> +       /* BO */
> +       MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
> +           CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
> +};
> +
> +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
> +       /* CMU_TOP_PURECLKCOMP */
> +       DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
> +           CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> +       DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
> +           CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> +       DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
> +           CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
> +       DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
> +           CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> +
> +       DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
> +           CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> +       DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
> +           CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> +       DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
> +           CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> +
> +       DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
> +           CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> +
> +       DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
> +           CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
> +
> +       /* BUS0 */
> +       DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
> +           CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
> +       DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
> +           CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
> +
> +       /* BUS1 */
> +       DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
> +           CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
> +
> +       /* BUS2 */
> +       DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
> +           CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
> +
> +       /* CORE */
> +       DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
> +           CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
> +
> +       /* EH */
> +       DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
> +           CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
> +
> +       /* CPUCL{0,1,2,} */
> +       DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch",
> +           CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
> +
> +       DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
> +           CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
> +
> +       DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch",
> +           CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
> +
> +       DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
> +           CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
> +
> +       DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
> +           CLK_CON_DIV_CLKCMU_HPM, 0, 2),
> +
> +       /* G3D */
> +       DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
> +           CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
> +
> +       DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
> +           CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
> +
> +       DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
> +           CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
> +
> +       /* DPU */
> +       DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
> +           CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
> +
> +       /* DISP */
> +       DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
> +           CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
> +
> +       /* G2D */
> +       DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
> +           CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
> +
> +       DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
> +           CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
> +
> +       /* HSI0 */
> +       DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd",
> +           CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
> +
> +       DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
> +           CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
> +
> +       DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
> +           CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
> +
> +       /* TODO register exists but all lower bits are reserved */
> +       DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg",
> +           CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
> +
> +       /* HSI1 */
> +       DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
> +           CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
> +
> +       DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
> +           CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
> +       /* HSI2 */
> +       DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
> +           CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
> +
> +       DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
> +           CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
> +
> +       DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd",
> +           CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
> +
> +       DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card",
> +           CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
> +
> +       /* CSIS */
> +       DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
> +           CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
> +
> +       /* PDP */
> +       DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
> +           CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
> +
> +       DIV(CLK_DOUT_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",
> +           CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
> +
> +       /* IPP */
> +       DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
> +           CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
> +
> +       /* G3AA */
> +       DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa",
> +           CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
> +
> +       /* ITP */
> +       DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
> +           CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
> +
> +       /* DNS */
> +       DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
> +           CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
> +
> +       /* TNR */
> +       DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
> +           CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
> +
> +       /* MCSC*/
> +       DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
> +           CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
> +
> +       DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
> +           CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
> +
> +       /* GDC */
> +       DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
> +           CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
> +
> +       DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
> +           CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
> +
> +       DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
> +           CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
> +
> +       /* MFC */
> +       DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
> +           CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
> +
> +       /* MIF0/1/2/3 */
> +       DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
> +           CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
> +
> +       /* MISC */
> +       DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
> +           CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
> +       DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
> +           CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
> +
> +       /* PERI0 */
> +       DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
> +           CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
> +       DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
> +           CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
> +
> +       /* PERI1 */
> +       DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
> +           CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
> +       DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
> +           CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
> +
> +       /* TPU */
> +       DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
> +           CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
> +
> +       DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
> +           CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
> +
> +       DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
> +           CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
> +
> +       DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
> +           CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
> +
> +       /* BO */
> +       DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
> +           CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
> +

Empty line here is unnecessary.

> +};
> +
> +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
> +       /* BUS0 */
> +       GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
> +
> +       /* BUS1 */
> +       GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
> +
> +       /* BUS2 */
> +       GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
> +
> +       /* CORE */
> +       GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
> +
> +       /* EH */
> +       GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
> +
> +       /* CPUCL{0,1,2,} */
> +       GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch",
> +            CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
> +            CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
> +            CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
> +            CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
> +            CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
> +
> +       /* G3D */
> +       GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
> +            CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
> +            CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
> +            CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
> +       /* DPU */
> +       GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
> +       /* DISP */
> +       GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
> +
> +       /* G2D */
> +       GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
> +            CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
> +            CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
> +       /* HSI0 */
> +       GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0),
> +       /* HSI1 */
> +       GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
> +       /* HSI2 */
> +       GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
> +       GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0),
> +       GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card",
> +            CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0),
> +       /* CSIS */
> +       GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> +       /* PDP */
> +       GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
> +            CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
> +       /* IPP */
> +       GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> +       /* G3AA */
> +       GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> +            CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
> +
> +       /* ITP */
> +       GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
> +
> +       /* DNS */
> +       GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
> +
> +       /* TNR */
> +       GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
> +
> +       /* MCSC*/
> +       GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
> +            CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
> +            CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
> +
> +       /* GDC */
> +       GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
> +            CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
> +            CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
> +            CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
> +
> +       /* MFC */
> +       GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
> +            CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
> +
> +       /* DDRPHY0/1/2/3 */
> +       GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
> +            CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
> +
> +       /* MIF0/1/2/3 */
> +       GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
> +            CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
> +
> +       GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost",
> +            CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
> +
> +       /* MISC */
> +       GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
> +       GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
> +            CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
> +
> +       /* PERI0 */
> +       GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
> +       GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
> +            CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
> +
> +       /* PERI1 */
> +       GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
> +       GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
> +            CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
> +
> +       /* TPU */
> +       GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
> +            CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
> +       GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
> +            CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
> +       GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
> +       GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
> +            CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
> +
> +       /* BO */
> +       GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
> +            CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
> +

Empty line here is unnecessary.

> +};
> +
> +static const struct samsung_cmu_info top_cmu_info __initconst = {
> +       .pll_clks               = cmu_top_pll_clks,
> +       .nr_pll_clks            = ARRAY_SIZE(cmu_top_pll_clks),
> +       .mux_clks               = cmu_top_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(cmu_top_mux_clks),
> +       .div_clks               = cmu_top_div_clks,
> +       .nr_div_clks            = ARRAY_SIZE(cmu_top_div_clks),
> +       .gate_clks              = cmu_top_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(cmu_top_gate_clks),
> +       .nr_clk_ids             = TOP_NR_CLK,
> +       .clk_regs               = cmu_top_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(cmu_top_clk_regs),
> +};
> +
> +static void __init gs101_cmu_top_init(struct device_node *np)
> +{
> +       exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
> +}
> +
> +/* Register CMU_TOP early, as it's a dependency for other early domains */
> +CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
> +              gs101_cmu_top_init);
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 11/20] clk: samsung: clk-gs101: add CMU_APM support

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:51 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> This patch adds all the registers for the APM clock controller unit.
>
> We register all the muxes and dividers, but only a few of the
> gates currently for PMU and GPIO.
>
> One clock is marked CLK_IS_CRITICAL because the system
> hangs if this clock is disabled.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Please merge all 3 clk patches together. Frankly in this case I'm not
sure there is a lot of value in keeping those separate.

>  drivers/clk/samsung/clk-gs101.c | 301 ++++++++++++++++++++++++++++++++
>  1 file changed, 301 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index e2c62754b1eb..525f95e60665 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -19,6 +19,7 @@
>
>  /* NOTE: Must be equal to the last clock ID increased by one */
>  #define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
> +#define APM_NR_CLK                     (CLK_APM_PLL_DIV16_APM + 1)

Tabs for the indentation.

>
>  /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -1549,3 +1550,303 @@ static void __init gs101_cmu_top_init(struct device_node *np)
>  /* Register CMU_TOP early, as it's a dependency for other early domains */
>  CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
>                gs101_cmu_top_init);
> +
> +/* ---- CMU_APM ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_APM (0x17400000) */
> +#define APM_CMU_APM_CONTROLLER_OPTION                                                  0x0800
> +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0                                             0x0810
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC                                                        0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC                                             0x1004
> +#define CLK_CON_DIV_DIV_CLK_APM_BOOST                                                  0x1800
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART                                              0x1804
> +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI                                               0x1808
> +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART                                              0x180c
> +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK                         0x2000
> +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1                                             0x2004
> +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1                                              0x2008
> +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1                                             0x200c
> +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC                                               0x2010
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK                   0x2014
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK               0x2018
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK                    0x201c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK                          0x2020
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK                         0x2024
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK                     0x2028
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK                      0x202c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK                      0x2030
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK                       0x2034
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK                     0x2038
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK                      0x203c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK                         0x2040
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK                            0x2044
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK                   0x2048
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK                             0x204c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK                             0x2050
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK                     0x2054
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK                  0x2058
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK                     0x205c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK                     0x2060
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK                 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK               0x2068
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK                    0x206c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK                     0x2070
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK                    0x2074
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK                    0x207c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK                    0x2080
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK                     0x2084
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK                 0x2088
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK                       0x208c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK                     0x2090
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK                     0x2094
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK                        0x2098
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK          0x209c
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK           0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK          0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK                         0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK                     0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK                         0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK                         0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK                     0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK                     0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK    0x20c0

Oh my, is that one is long :)

> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2                     0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK                         0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK                           0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK                           0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK                       0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK                       0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK                         0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK                         0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK                      0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK                      0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK                         0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK                         0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK                            0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK                         0x20fc
> +#define PCH_CON_LHM_AXI_G_SWD_PCH                      0x3000
> +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH                   0x3004
> +#define PCH_CON_LHM_AXI_P_APM_PCH                      0x3008
> +#define PCH_CON_LHS_AXI_D_APM_PCH                      0x300c
> +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH                  0x3010
> +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH                        0x3014
> +#define QCH_CON_APBIF_GPIO_ALIVE_QCH                   0x3018
> +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH               0x301c
> +#define QCH_CON_APBIF_PMU_ALIVE_QCH                    0x3020
> +#define QCH_CON_APBIF_RTC_QCH                          0x3024
> +#define QCH_CON_APBIF_TRTC_QCH                         0x3028
> +#define QCH_CON_APM_CMU_APM_QCH                                0x302c
> +#define QCH_CON_APM_USI0_UART_QCH                      0x3030
> +#define QCH_CON_APM_USI0_USI_QCH                       0x3034
> +#define QCH_CON_APM_USI1_UART_QCH                      0x3038
> +#define QCH_CON_D_TZPC_APM_QCH                         0x303c
> +#define QCH_CON_GPC_APM_QCH                            0x3040
> +#define QCH_CON_GREBEINTEGRATION_QCH_DBG               0x3044
> +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE             0x3048
> +#define QCH_CON_INTMEM_QCH                             0x304c
> +#define QCH_CON_LHM_AXI_G_SWD_QCH                      0x3050
> +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH                   0x3054
> +#define QCH_CON_LHM_AXI_P_APM_QCH                      0x3058
> +#define QCH_CON_LHS_AXI_D_APM_QCH                      0x305c
> +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH                  0x3060
> +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH                        0x3064
> +#define QCH_CON_MAILBOX_APM_AOC_QCH                    0x3068
> +#define QCH_CON_MAILBOX_APM_AP_QCH                     0x306c
> +#define QCH_CON_MAILBOX_APM_GSA_QCH                    0x3070
> +#define QCH_CON_MAILBOX_APM_SWD_QCH                    0x3078
> +#define QCH_CON_MAILBOX_APM_TPU_QCH                    0x307c
> +#define QCH_CON_MAILBOX_AP_AOC_QCH                     0x3080
> +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH                 0x3084
> +#define QCH_CON_PMU_INTR_GEN_QCH                       0x3088
> +#define QCH_CON_ROM_CRC32_HOST_QCH                     0x308c
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE         0x3090
> +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG     0x3094
> +#define QCH_CON_SPEEDY_APM_QCH                         0x3098
> +#define QCH_CON_SPEEDY_SUB_APM_QCH                     0x309c
> +#define QCH_CON_SSMT_D_APM_QCH                         0x30a0
> +#define QCH_CON_SSMT_G_DBGCORE_QCH                     0x30a4
> +#define QCH_CON_SS_DBGCORE_QCH_DBG                     0x30a8
> +#define QCH_CON_SS_DBGCORE_QCH_GREBE                   0x30ac
> +#define QCH_CON_SYSMMU_D_APM_QCH                       0x30b0
> +#define QCH_CON_SYSREG_APM_QCH                         0x30b8
> +#define QCH_CON_UASC_APM_QCH                           0x30bc
> +#define QCH_CON_UASC_DBGCORE_QCH                       0x30c0
> +#define QCH_CON_UASC_G_SWD_QCH                         0x30c4
> +#define QCH_CON_UASC_P_AOCAPM_QCH                      0x30c8
> +#define QCH_CON_UASC_P_APM_QCH                         0x30cc
> +#define QCH_CON_WDT_APM_QCH                            0x30d0
> +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM                 0x3c00
> +
> +static const unsigned long apm_clk_regs[] __initconst = {
> +       APM_CMU_APM_CONTROLLER_OPTION,
> +       CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
> +       CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
> +       CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
> +       CLK_CON_DIV_DIV_CLK_APM_BOOST,
> +       CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
> +       CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
> +       CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
> +       CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
> +       CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
> +       CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
> +       CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
> +};
> +
> +PNAME(mout_apm_func_p) = { "oscclk_apmgsa", "mout_apm_funcsrc", "pad_clk_apm" };
> +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" };
> +
> +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
> +       FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000),
> +       FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000),
> +       FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000),
> +};
> +
> +static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
> +       MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
> +           CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
> +       MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
> +           CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
> +};
> +
> +static const struct samsung_div_clock apm_div_clks[] __initconst = {
> +       DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
> +           CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
> +       DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
> +           CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
> +       DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
> +           CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
> +       DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
> +           CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
> +};
> +
> +static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
> +       GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
> +            CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
> +

Empty lines are not necessary in cases like that.

> +       GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> +            "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func",
> +            CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
> +            21, 0, 0),
> +
> +       GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> +            "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func",
> +            CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
> +            21, 0, 0),
> +
> +       GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> +            "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func",
> +            CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
> +            21, CLK_IS_CRITICAL, 0),
> +
> +       GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> +            "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func",
> +            CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
> +            21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info apm_cmu_info __initconst = {
> +       .mux_clks               = apm_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(apm_mux_clks),
> +       .div_clks               = apm_div_clks,
> +       .nr_div_clks            = ARRAY_SIZE(apm_div_clks),
> +       .gate_clks              = apm_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(apm_gate_clks),
> +       .fixed_clks             = apm_fixed_clks,
> +       .nr_fixed_clks          = ARRAY_SIZE(apm_fixed_clks),
> +       .nr_clk_ids             = APM_NR_CLK,
> +       .clk_regs               = apm_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(apm_clk_regs),
> +};
> +
> +/* ---- platform_driver ----------------------------------------------------- */
> +
> +static int __init gs101_cmu_probe(struct platform_device *pdev)
> +{
> +       const struct samsung_cmu_info *info;
> +       struct device *dev = &pdev->dev;
> +
> +       info = of_device_get_match_data(dev);
> +       exynos_arm64_register_cmu(dev, dev->of_node, info);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id gs101_cmu_of_match[] = {
> +       {
> +               .compatible = "google,gs101-cmu-apm",
> +               .data = &apm_cmu_info,
> +       }, {
> +       },
> +};
> +
> +static struct platform_driver gs101_cmu_driver __refdata = {
> +       .driver = {
> +               .name = "gs101-cmu",
> +               .of_match_table = gs101_cmu_of_match,
> +               .suppress_bind_attrs = true,
> +       },
> +       .probe = gs101_cmu_probe,
> +};
> +
> +static int __init gs101_cmu_init(void)
> +{
> +       return platform_driver_register(&gs101_cmu_driver);
> +}
> +core_initcall(gs101_cmu_init);
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 12/20] clk: samsung: clk-gs101: Add support for CMU_MISC clock unit

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> CMU Misc clocks IPs such as Watchdog. Add support for the
> muxes, dividers and gates in this CMU.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/clk/samsung/clk-gs101.c | 312 ++++++++++++++++++++++++++++++++
>  1 file changed, 312 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 525f95e60665..bf2bd8cd39d0 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -20,6 +20,7 @@
>  /* NOTE: Must be equal to the last clock ID increased by one */
>  #define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
>  #define APM_NR_CLK                     (CLK_APM_PLL_DIV16_APM + 1)
> +#define MISC_NR_CLK                    (CLK_GOUT_MISC_WDT_CLUSTER1 + 1)

Tabs for the indentation.

>
>  /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -1815,6 +1816,314 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
>         .nr_clk_regs            = ARRAY_SIZE(apm_clk_regs),
>  };
>
> +/* ---- CMU_MISC ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_MISC (0x10010000) */
> +#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER      0x0600
> +#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER      0x0604
> +#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER      0x0610
> +#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER      0x0614
> +#define MISC_CMU_MISC_CONTROLLER_OPTION                0x0800
> +#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0   0x0810
> +#define CLK_CON_MUX_MUX_CLK_MISC_GIC           0x1000
> +#define CLK_CON_DIV_DIV_CLK_MISC_BUSP          0x1800
> +#define CLK_CON_DIV_DIV_CLK_MISC_GIC           0x1804
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK              0x2000
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK           0x2004
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK           0x2008
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK            0x200c
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK    0x2010
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM              0x2014
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM               0x2018
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM               0x201c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A                    0x2020
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK               0x2024
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK                     0x2028
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK                  0x202c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK       0x2030
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK            0x2034
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK            0x2038
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK           0x203c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK          0x2040
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK       0x2044
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK            0x2048
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK                       0x204c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK              0x2050
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK              0x2054
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK               0x2058
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK                      0x205c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK                  0x2060
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK                 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK                 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK                      0x206c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK                    0x2070
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK                    0x2074
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK                   0x2078
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK                   0x207c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK               0x2080
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK               0x2084
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK                   0x2088
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK                   0x208c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK                  0x2090
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK                  0x2094
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK                    0x2098
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK                    0x209c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK     0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK     0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK      0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK      0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK                    0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK                    0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK                     0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK                  0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK                  0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK                 0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK                 0x20c8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK             0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK             0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK                 0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK                 0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK                        0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK                        0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK                  0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK                  0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK                     0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK                     0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2             0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1              0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK               0x20fc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK                   0x2100
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK                   0x2104
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK              0x2108
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK              0x210c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK                        0x2110
> +#define DMYQCH_CON_PPMU_DMA_QCH                        0x3000
> +#define DMYQCH_CON_PUF_QCH                     0x3004
> +#define PCH_CON_LHM_AXI_D_SSS_PCH              0x300c
> +#define PCH_CON_LHM_AXI_P_GIC_PCH              0x3010
> +#define PCH_CON_LHM_AXI_P_MISC_PCH             0x3014
> +#define PCH_CON_LHS_ACEL_D_MISC_PCH            0x3018
> +#define PCH_CON_LHS_AST_IRI_GICCPU_PCH         0x301c
> +#define PCH_CON_LHS_AXI_D_SSS_PCH              0x3020
> +#define QCH_CON_ADM_AHB_SSS_QCH                        0x3024
> +#define QCH_CON_DIT_QCH                                0x3028
> +#define QCH_CON_GIC_QCH                                0x3030
> +#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH         0x3038
> +#define QCH_CON_LHM_AXI_D_SSS_QCH              0x303c
> +#define QCH_CON_LHM_AXI_P_GIC_QCH              0x3040
> +#define QCH_CON_LHM_AXI_P_MISC_QCH             0x3044
> +#define QCH_CON_LHS_ACEL_D_MISC_QCH            0x3048
> +#define QCH_CON_LHS_AST_IRI_GICCPU_QCH         0x304c
> +#define QCH_CON_LHS_AXI_D_SSS_QCH              0x3050
> +#define QCH_CON_MCT_QCH                                0x3054
> +#define QCH_CON_MISC_CMU_MISC_QCH              0x3058
> +#define QCH_CON_OTP_CON_BIRA_QCH               0x305c
> +#define QCH_CON_OTP_CON_BISR_QCH               0x3060
> +#define QCH_CON_OTP_CON_TOP_QCH                        0x3064
> +#define QCH_CON_PDMA_QCH                       0x3068
> +#define QCH_CON_PPMU_MISC_QCH                  0x306c
> +#define QCH_CON_QE_DIT_QCH                     0x3070
> +#define QCH_CON_QE_PDMA_QCH                    0x3074
> +#define QCH_CON_QE_PPMU_DMA_QCH                        0x3078
> +#define QCH_CON_QE_RTIC_QCH                    0x307c
> +#define QCH_CON_QE_SPDMA_QCH                   0x3080
> +#define QCH_CON_QE_SSS_QCH                     0x3084
> +#define QCH_CON_RTIC_QCH                       0x3088
> +#define QCH_CON_SPDMA_QCH                      0x308c
> +#define QCH_CON_SSMT_DIT_QCH                   0x3090
> +#define QCH_CON_SSMT_PDMA_QCH                  0x3094
> +#define QCH_CON_SSMT_PPMU_DMA_QCH              0x3098
> +#define QCH_CON_SSMT_RTIC_QCH                  0x309c
> +#define QCH_CON_SSMT_SPDMA_QCH                 0x30a0
> +#define QCH_CON_SSMT_SSS_QCH                   0x30a4
> +#define QCH_CON_SSS_QCH                                0x30a8
> +#define QCH_CON_SYSMMU_MISC_QCH                        0x30ac
> +#define QCH_CON_SYSMMU_SSS_QCH                 0x30b0
> +#define QCH_CON_SYSREG_MISC_QCH                        0x30b4
> +#define QCH_CON_TMU_SUB_QCH                    0x30b8
> +#define QCH_CON_TMU_TOP_QCH                    0x30bc
> +#define QCH_CON_WDT_CLUSTER0_QCH               0x30c0
> +#define QCH_CON_WDT_CLUSTER1_QCH               0x30c4
> +#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC       0x3c00
> +
> +static const unsigned long misc_clk_regs[] __initconst = {
> +       PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
> +       PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
> +       PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
> +       PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
> +       MISC_CMU_MISC_CONTROLLER_OPTION,
> +       CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
> +       CLK_CON_MUX_MUX_CLK_MISC_GIC,
> +       CLK_CON_DIV_DIV_CLK_MISC_BUSP,
> +       CLK_CON_DIV_DIV_CLK_MISC_GIC,
> +       CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
> +       CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
> +       CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
> +       CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
> +       CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
> +       DMYQCH_CON_PPMU_DMA_QCH,
> +       DMYQCH_CON_PUF_QCH,
> +       PCH_CON_LHM_AXI_D_SSS_PCH,
> +       PCH_CON_LHM_AXI_P_GIC_PCH,
> +       PCH_CON_LHM_AXI_P_MISC_PCH,
> +       PCH_CON_LHS_ACEL_D_MISC_PCH,
> +       PCH_CON_LHS_AST_IRI_GICCPU_PCH,
> +       PCH_CON_LHS_AXI_D_SSS_PCH,
> +       QCH_CON_ADM_AHB_SSS_QCH,
> +       QCH_CON_DIT_QCH,
> +       QCH_CON_GIC_QCH,
> +       QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
> +       QCH_CON_LHM_AXI_D_SSS_QCH,
> +       QCH_CON_LHM_AXI_P_GIC_QCH,
> +       QCH_CON_LHM_AXI_P_MISC_QCH,
> +       QCH_CON_LHS_ACEL_D_MISC_QCH,
> +       QCH_CON_LHS_AST_IRI_GICCPU_QCH,
> +       QCH_CON_LHS_AXI_D_SSS_QCH,
> +       QCH_CON_MCT_QCH,
> +       QCH_CON_MISC_CMU_MISC_QCH,
> +       QCH_CON_OTP_CON_BIRA_QCH,
> +       QCH_CON_OTP_CON_BISR_QCH,
> +       QCH_CON_OTP_CON_TOP_QCH,
> +       QCH_CON_PDMA_QCH,
> +       QCH_CON_PPMU_MISC_QCH,
> +       QCH_CON_QE_DIT_QCH,
> +       QCH_CON_QE_PDMA_QCH,
> +       QCH_CON_QE_PPMU_DMA_QCH,
> +       QCH_CON_QE_RTIC_QCH,
> +       QCH_CON_QE_SPDMA_QCH,
> +       QCH_CON_QE_SSS_QCH,
> +       QCH_CON_RTIC_QCH,
> +       QCH_CON_SPDMA_QCH,
> +       QCH_CON_SSMT_DIT_QCH,
> +       QCH_CON_SSMT_PDMA_QCH,
> +       QCH_CON_SSMT_PPMU_DMA_QCH,
> +       QCH_CON_SSMT_RTIC_QCH,
> +       QCH_CON_SSMT_SPDMA_QCH,
> +       QCH_CON_SSMT_SSS_QCH,
> +       QCH_CON_SSS_QCH,
> +       QCH_CON_SYSMMU_MISC_QCH,
> +       QCH_CON_SYSMMU_SSS_QCH,
> +       QCH_CON_SYSREG_MISC_QCH,
> +       QCH_CON_TMU_SUB_QCH,
> +       QCH_CON_TMU_TOP_QCH,
> +       QCH_CON_WDT_CLUSTER0_QCH,
> +       QCH_CON_WDT_CLUSTER1_QCH,
> +       QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_MISC */
> +PNAME(mout_misc_bus_user_p)            = { "oscclk", "dout_cmu_misc_bus" };
> +PNAME(mout_misc_sss_user_p)            = { "oscclk", "dout_cmu_misc_sss" };
> +
> +static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
> +       MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
> +           PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
> +       MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
> +           PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
> +};
> +
> +static const struct samsung_div_clock misc_div_clks[] __initconst = {
> +       DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
> +           CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
> +       DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
> +           CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
> +};
> +
> +static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
> +       GATE(CLK_GOUT_MISC_PCLK, "gout_misc_pclk", "dout_misc_busp",
> +            CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
> +            21, 0, 0),
> +

No need in empty lines.

> +       GATE(CLK_GOUT_MISC_SYSREG_PCLK, "gout_misc_sysreg_pclk", "dout_misc_busp",
> +            CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
> +            21, 0, 0),
> +
> +       GATE(CLK_GOUT_MISC_WDT_CLUSTER0, "gout_misc_wdt_cluster0", "dout_misc_busp",
> +            CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
> +            21, 0, 0),
> +
> +       GATE(CLK_GOUT_MISC_WDT_CLUSTER1, "gout_misc_wdt_cluster1", "dout_misc_busp",
> +            CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
> +            21, 0, 0),
> +

Unnecessary empty line.

> +};
> +
> +static const struct samsung_cmu_info misc_cmu_info __initconst = {
> +       .mux_clks               = misc_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(misc_mux_clks),
> +       .div_clks               = misc_div_clks,
> +       .nr_div_clks            = ARRAY_SIZE(misc_div_clks),
> +       .gate_clks              = misc_gate_clks,
> +       .nr_gate_clks           = ARRAY_SIZE(misc_gate_clks),
> +       .nr_clk_ids             = MISC_NR_CLK,
> +       .clk_regs               = misc_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(misc_clk_regs),
> +       .clk_name               = "dout_misc_bus",
> +};
> +
>  /* ---- platform_driver ----------------------------------------------------- */
>
>  static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -1832,6 +2141,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
>         {
>                 .compatible = "google,gs101-cmu-apm",
>                 .data = &apm_cmu_info,
> +       }, {
> +               .compatible = "google,gs101-cmu-misc",
> +               .data = &misc_cmu_info,
>         }, {
>         },
>  };
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 15/20] watchdog: s3c2410_wdt: Add support for Google tensor SoCs

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> This patch adds the compatibles and drvdata for the Google
> gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> to Exynos850 it has two watchdog instances, one for each cluster
> and has some control bits in PMU registers.
>
> The watchdog IP found in gs101 SoCs also supports a few
> additional bits/features in the WTCON register which we add
> support for and an additional register detailed below.
>
> dbgack-mask - Enables masking WDT interrupt and reset request
> according to asserted DBGACK input
>
> windowed-mode - Enabled Windowed watchdog mode
>
> Windowed watchdog mode also has an additional register WTMINCNT.
> If windowed watchdog is enabled and you reload WTCNT when the
> value is greater than WTMINCNT, it prompts interrupt or reset
> request as if the watchdog time has expired.
>

A couple of thoughts in addition to what Guenter said.

From the description it looks like this patch should be split into 3 patches:
  1. Add "dbgack" feature
  2. Add "windowed mode" feature
  3. Enable gsX01 support

Also, it's not clear if those features are mandatory for gsX01 wdt to
function properly, or optional? From the code it looks like both
dbgack and windowed mode will only affect gsX01 variants (because of
quirk flags), but maybe the commit message should be more clear about
that.

> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/watchdog/s3c2410_wdt.c | 127 ++++++++++++++++++++++++++++++---
>  1 file changed, 116 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 0b4bd883ff28..36c170047180 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -31,12 +31,14 @@
>  #define S3C2410_WTDAT          0x04
>  #define S3C2410_WTCNT          0x08
>  #define S3C2410_WTCLRINT       0x0c
> -
> +#define S3C2410_WTMINCNT       0x10
>  #define S3C2410_WTCNT_MAXCNT   0xffff
>
> -#define S3C2410_WTCON_RSTEN    (1 << 0)
> -#define S3C2410_WTCON_INTEN    (1 << 2)
> -#define S3C2410_WTCON_ENABLE   (1 << 5)
> +#define S3C2410_WTCON_RSTEN            (1 << 0)
> +#define S3C2410_WTCON_INTEN            (1 << 2)
> +#define S3C2410_WTCON_ENABLE           (1 << 5)
> +#define S3C2410_WTCON_DBGACK_MASK      (1 << 16)
> +#define S3C2410_WTCON_WINDOWED_WD      (1 << 20)

Maybe use BIT() macro here?

>
>  #define S3C2410_WTCON_DIV16    (0 << 3)
>  #define S3C2410_WTCON_DIV32    (1 << 3)
> @@ -51,6 +53,7 @@
>
>  #define S3C2410_WATCHDOG_ATBOOT                (0)
>  #define S3C2410_WATCHDOG_DEFAULT_TIME  (15)
> +#define S3C2410_WINDOW_MULTIPLIER      2
>
>  #define EXYNOS5_RST_STAT_REG_OFFSET            0x0404
>  #define EXYNOS5_WDT_DISABLE_REG_OFFSET         0x0408
> @@ -67,6 +70,13 @@
>  #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT     25
>  #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT     24
>
> +#define GS_CLUSTER0_NONCPU_OUT                 0x1220
> +#define GS_CLUSTER1_NONCPU_OUT                 0x1420
> +#define GS_CLUSTER0_NONCPU_INT_EN              0x1244
> +#define GS_CLUSTER1_NONCPU_INT_EN              0x1444
> +#define GS_CLUSTER2_NONCPU_INT_EN              0x1644
> +#define GS_RST_STAT_REG_OFFSET                 0x3B44

Please move those to the section above, where similar registers are
described for other SoCs.

> +
>  /**
>   * DOC: Quirk flags for different Samsung watchdog IP-cores
>   *
> @@ -106,6 +116,8 @@
>  #define QUIRK_HAS_PMU_RST_STAT                 (1 << 2)
>  #define QUIRK_HAS_PMU_AUTO_DISABLE             (1 << 3)
>  #define QUIRK_HAS_PMU_CNT_EN                   (1 << 4)
> +#define QUIRK_HAS_DBGACK_BIT                   (1 << 5)
> +#define QUIRK_HAS_WTMINCNT_REG                 (1 << 6)

Please also document those two quirks in the kernel-doc comment above.
Btw, the comment correctness can be checked like this:

    $ scripts/kernel-doc -v -none drivers/watchdog/s3c2410_wdt.c

or without "-none" option to see how the comment is parsed by kernel-doc.

>
>  /* These quirks require that we have a PMU register map */
>  #define QUIRKS_HAVE_PMUREG \
> @@ -263,6 +275,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
>                   QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
>  };
>
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> +       .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> +       .mask_bit = 2,
> +       .mask_reset_inv = true,
> +       .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +       .rst_stat_bit = 0,
> +       .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> +       .cnt_en_bit = 8,
> +       .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |

Here and further: please stick to 80 characters per line when possible.

> +                 QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> +       .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> +       .mask_bit = 2,
> +       .mask_reset_inv = true,
> +       .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +       .rst_stat_bit = 1,
> +       .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> +       .cnt_en_bit = 7,
> +       .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +                 QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
> +       .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> +       .mask_bit = 2,
> +       .mask_reset_inv = true,
> +       .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +       .rst_stat_bit = 0,
> +       .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> +       .cnt_en_bit = 8,
> +       .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +                 QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
> +       .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> +       .mask_bit = 2,
> +       .mask_reset_inv = true,
> +       .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +       .rst_stat_bit = 1,
> +       .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> +       .cnt_en_bit = 7,
> +       .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +                 QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
>  static const struct of_device_id s3c2410_wdt_match[] = {
>         { .compatible = "samsung,s3c2410-wdt",
>           .data = &drv_data_s3c2410 },
> @@ -278,6 +338,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
>           .data = &drv_data_exynos850_cl0 },
>         { .compatible = "samsung,exynosautov9-wdt",
>           .data = &drv_data_exynosautov9_cl0 },
> +       { .compatible = "google,gs101-wdt",
> +         .data = &drv_data_gs101_cl0 },
> +       { .compatible = "google,gs201-wdt",
> +         .data = &drv_data_gs201_cl0 },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> @@ -375,6 +439,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
>         return 0;
>  }
>
> +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
> +{
> +       unsigned long wtcon;
> +
> +       if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
> +               return;
> +
> +       wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> +       if (mask)
> +               wtcon |= S3C2410_WTCON_DBGACK_MASK;
> +       else
> +               wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
> +       writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> +}
> +
>  static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
>  {
>         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> @@ -410,7 +489,7 @@ static int s3c2410wdt_stop(struct watchdog_device *wdd)
>
>  static int s3c2410wdt_start(struct watchdog_device *wdd)
>  {
> -       unsigned long wtcon;
> +       unsigned long wtcon, wtmincnt;
>         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
>         unsigned long flags;
>
> @@ -432,6 +511,12 @@ static int s3c2410wdt_start(struct watchdog_device *wdd)
>         dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
>                 wdt->count, wtcon);
>
> +       if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) {
> +               wtcon |= S3C2410_WTCON_WINDOWED_WD;
> +               wtmincnt = wdt->count * S3C2410_WINDOW_MULTIPLIER;
> +               writel(wtmincnt, wdt->reg_base + S3C2410_WTMINCNT);
> +       }
> +
>         writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
>         writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
>         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> @@ -447,7 +532,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
>         unsigned long freq = s3c2410wdt_get_freq(wdt);
>         unsigned int count;
>         unsigned int divisor = 1;
> -       unsigned long wtcon;
> +       unsigned long wtcon, wtmincnt;
>
>         if (timeout < 1)
>                 return -EINVAL;
> @@ -478,6 +563,11 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
>         count = DIV_ROUND_UP(count, divisor);
>         wdt->count = count;
>
> +       if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) {
> +               wtmincnt = count * S3C2410_WINDOW_MULTIPLIER;
> +               writel(wtmincnt, wdt->reg_base + S3C2410_WTMINCNT);
> +       }
> +
>         /* update the pre-scaler */
>         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
>         wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
> @@ -496,14 +586,20 @@ static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
>  {
>         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
>         void __iomem *wdt_base = wdt->reg_base;
> +       unsigned long wtcon;
>
>         /* disable watchdog, to be safe  */
>         writel(0, wdt_base + S3C2410_WTCON);
>
>         /* put initial values into count and data */
> +       if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> +               writel(0x100, wdt_base + S3C2410_WTMINCNT);
>         writel(0x80, wdt_base + S3C2410_WTCNT);
>         writel(0x80, wdt_base + S3C2410_WTDAT);
>
> +       if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> +               wtcon |= S3C2410_WTCON_WINDOWED_WD;
> +
>         /* set the watchdog to go and reset... */
>         writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
>                 S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
> @@ -585,9 +681,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
>         }
>
>  #ifdef CONFIG_OF
> -       /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> +       /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */

Please keep 80 characters per line.

>         if (variant == &drv_data_exynos850_cl0 ||
> -           variant == &drv_data_exynosautov9_cl0) {
> +           variant == &drv_data_exynosautov9_cl0 ||
> +           variant == &drv_data_gs101_cl0 ||
> +           variant == &drv_data_gs201_cl0) {
>                 u32 index;
>                 int err;
>
> @@ -600,9 +698,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
>                 case 0:
>                         break;
>                 case 1:
> -                       variant = (variant == &drv_data_exynos850_cl0) ?
> -                               &drv_data_exynos850_cl1 :
> -                               &drv_data_exynosautov9_cl1;
> +                       if (variant == &drv_data_exynos850_cl0)
> +                               variant = &drv_data_exynos850_cl1;
> +                       else if (variant == &drv_data_exynosautov9_cl0)
> +                               variant = &drv_data_exynosautov9_cl1;
> +                       else if (variant == &drv_data_gs101_cl0)
> +                               variant = &drv_data_gs101_cl1;
> +                       else if (variant == &drv_data_gs201_cl0)
> +                               variant = &drv_data_gs201_cl1;
>                         break;
>                 default:
>                         return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> @@ -700,6 +803,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
>         wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
>         wdt->wdt_device.parent = dev;
>
> +       s3c2410wdt_mask_dbgack(wdt, true);
> +
>         /*
>          * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
>          * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add serial driver data for Google Tensor gs101 SoC.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  drivers/tty/serial/samsung_tty.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index 07fb8a9dac63..26bc52e681a4 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -2597,14 +2597,22 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
>         .fifosize = { 256, 64, 64, 64 },
>  };
>
> +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> +       EXYNOS_COMMON_SERIAL_DRV_DATA(),
> +       /* rely on samsung,uart-fifosize DT property for fifosize */
> +       .fifosize = { 0 },
> +};
> +
>  #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
>  #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
>  #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
> +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
>
>  #else
>  #define EXYNOS4210_SERIAL_DRV_DATA NULL
>  #define EXYNOS5433_SERIAL_DRV_DATA NULL
>  #define EXYNOS850_SERIAL_DRV_DATA NULL
> +#define GS101_SERIAL_DRV_DATA NULL
>  #endif
>
>  #ifdef CONFIG_ARCH_APPLE
> @@ -2688,6 +2696,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
>         }, {
>                 .name           = "artpec8-uart",
>                 .driver_data    = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
> +       }, {
> +               .name           = "gs101-uart",
> +               .driver_data    = (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
>         },
>         { },
>  };
> @@ -2709,6 +2720,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
>                 .data = EXYNOS850_SERIAL_DRV_DATA },
>         { .compatible = "axis,artpec8-uart",
>                 .data = ARTPEC8_SERIAL_DRV_DATA },
> +       { .compatible = "google,gs101-uart",
> +               .data =  GS101_SERIAL_DRV_DATA },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 14/20] pinctrl: samsung: Add gs101 SoC pinctrl configuration

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add support for the pin-controller found on the gs101 SoC used in
> Pixel 6 phones.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 163 ++++++++++++++++++
>  drivers/pinctrl/samsung/pinctrl-exynos.c      |   2 +
>  drivers/pinctrl/samsung/pinctrl-exynos.h      |  34 ++++
>  drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
>  drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
>  5 files changed, 202 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index cb965cf93705..db47001d1b35 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
>         .ctrl           = fsd_pin_ctrl,
>         .num_ctrl       = ARRAY_SIZE(fsd_pin_ctrl),
>  };
> +
> +/*
> + * bank type for non-alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> + */
> +static struct samsung_pin_bank_type gs101_bank_type_off  = {
> +       .fld_width = { 4, 1, 4, 4, 2, 4, },
> +       .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> +};
> +
> +/*
> + * bank type for alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + */
> +static const struct samsung_pin_bank_type gs101_bank_type_alive = {
> +       .fld_width = { 4, 1, 4, 4, },
> +       .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> +};
> +
> +/* pin banks of gs101 pin-controller (ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),

Here and further: please keep 80 characters per line when possible.

> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACORE) */
> +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACTRL) */
> +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC0) */
> +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC1) */
> +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI1) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI2) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> +       {
> +               /* pin banks of gs101 pin-controller (ALIVE) */
> +               .pin_banks      = gs101_pin_alive,
> +               .nr_banks       = ARRAY_SIZE(gs101_pin_alive),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .eint_wkup_init = exynos_eint_wkup_init,

Is it ok to have both .eint_gpio_init and .eint_wkup_init set here and
further? I remember doing something like that for Exynos850 before,
only to realize further if was a mistake. Please check commit
96f79935015c ("pinctrl: samsung: Remove EINT handler for Exynos850
ALIVE and CMGP gpios"). Maybe it's ok in your case.

> +               .suspend        = exynos_pinctrl_suspend,
> +               .resume         = exynos_pinctrl_resume,

Did you manage to actually test those suspend/resume callbacks
somehow? If so, can you please share the procedure? I guess I had some
Power Domains and clock related problems on Exynos850 when I tried
that before, so just curious.

> +       }, {
> +               /* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +               .pin_banks      = gs101_pin_far_alive,
> +               .nr_banks       = ARRAY_SIZE(gs101_pin_far_alive),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .eint_wkup_init = exynos_eint_wkup_init,
> +               .suspend        = exynos_pinctrl_suspend,
> +               .resume         = exynos_pinctrl_resume,
> +       }, {
> +               /* pin banks of gs101 pin-controller (GSACORE) */
> +               .pin_banks      = gs101_pin_gsacore,
> +               .nr_banks       = ARRAY_SIZE(gs101_pin_gsacore),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +       }, {
> +               /* pin banks of gs101 pin-controller (GSACTRL) */
> +               .pin_banks      = gs101_pin_gsactrl,
> +               .nr_banks       = ARRAY_SIZE(gs101_pin_gsactrl),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +       }, {
> +               /* pin banks of gs101 pin-controller (PERIC0) */
> +               .pin_banks      = gs101_pin_peric0,
> +               .nr_banks       = ARRAY_SIZE(gs101_pin_peric0),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = exynos_pinctrl_suspend,
> +               .resume         = exynos_pinctrl_resume,
> +       }, {
> +               /* pin banks of gs101 pin-controller (PERIC1) */
> +               .pin_banks      = gs101_pin_peric1,
> +               .nr_banks       = ARRAY_SIZE(gs101_pin_peric1),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = exynos_pinctrl_suspend,
> +               .resume = exynos_pinctrl_resume,
> +       }, {
> +               /* pin banks of gs101 pin-controller (HSI1) */
> +               .pin_banks      = gs101_pin_hsi1,
> +               .nr_banks       = ARRAY_SIZE(gs101_pin_hsi1),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = exynos_pinctrl_suspend,
> +               .resume         = exynos_pinctrl_resume,
> +       }, {
> +               /* pin banks of gs101 pin-controller (HSI2) */
> +               .pin_banks      = gs101_pin_hsi2,
> +               .nr_banks       = ARRAY_SIZE(gs101_pin_hsi2),
> +               .eint_gpio_init = exynos_eint_gpio_init,
> +               .suspend        = exynos_pinctrl_suspend,
> +               .resume         = exynos_pinctrl_resume,
> +       },
> +};
> +
> +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> +       .ctrl           = gs101_pin_ctrl,
> +       .num_ctrl       = ARRAY_SIZE(gs101_pin_ctrl),
> +};
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index 800831aa8357..014f0c37f97f 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -533,6 +533,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
>                         .data = &exynos7_wkup_irq_chip },
>         { .compatible = "samsung,exynosautov9-wakeup-eint",
>                         .data = &exynos7_wkup_irq_chip },
> +       { .compatible = "google,gs101-wakeup-eint",
> +                       .data = &exynos7_wkup_irq_chip },
>         { }
>  };
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 63b2426ad5d6..0dd013654bd2 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -147,6 +147,40 @@
>                 .name           = id                            \
>         }
>
> +#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id)   \
> +       {                                               \
> +               .type           = &types,               \
> +               .pctl_offset    = reg,                  \
> +               .nr_pins        = pins,                 \
> +               .eint_type      = EINT_TYPE_NONE,       \
> +               .fltcon_type    = FLT_DEFAULT           \
> +               .name           = id                    \
> +       }
> +
> +#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> +       {                                               \
> +               .type           = &types,               \
> +               .pctl_offset    = reg,                  \
> +               .nr_pins        = pins,                 \
> +               .eint_type      = EINT_TYPE_GPIO,       \
> +               .eint_offset    = offs,                 \
> +               .fltcon_type    = fltcontype,           \
> +               .fltcon_offset  = fltcon_offs,          \
> +               .name           = id                    \
> +       }
> +
> +#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> +       {                                               \
> +               .type           = &types,               \
> +               .pctl_offset    = reg,                  \
> +               .nr_pins        = pins,                 \
> +               .eint_type      = EINT_TYPE_WKUP,       \
> +               .eint_offset    = offs,                 \
> +               .fltcon_type    = fltcontype,           \
> +               .fltcon_offset  = fltcon_offs,          \
> +               .name           = id                    \
> +       }
> +

Looks to me that instead of adding new macros the already existing
EXYNOS850_PIN_BANK_* should be extended and re-used. Because those
pinctrl IP-cores on all modern Exynos chips look very similar, even if
you compare the downstream code. If EXYNOS850 prefix looks confusing,
maybe it can be renamed to EXYNOS9 or something like that. Those
filter parameters are also present in Exynos850 downstream kernel
code. So I just feel like the proper way to add that feature would be
to add that also for all modern ARM64 Exynos variants while at it.

>  /**
>   * struct exynos_weint_data: irq specific data for all the wakeup interrupts
>   * generated by the external wakeup interrupt controller.
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 449f8109d8b5..12176f98440d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
>                 .data = &exynosautov9_of_data },
>         { .compatible = "tesla,fsd-pinctrl",
>                 .data = &fsd_of_data },
> +       { .compatible = "google,gs101-pinctrl",
> +               .data = &gs101_of_data },
>  #endif
>  #ifdef CONFIG_PINCTRL_S3C64XX
>         { .compatible = "samsung,s3c64xx-pinctrl",
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index de2ca8e8b378..e62e909fb10d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -374,6 +374,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
>  extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
>  extern const struct samsung_pinctrl_of_match_data fsd_of_data;
> +extern const struct samsung_pinctrl_of_match_data gs101_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
>  extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 20/20] MAINTAINERS: add entry for Google Tensor SoC

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add maintainers entry for the Google tensor SoC based
> platforms.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  MAINTAINERS | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 90f13281d297..149a0c364309 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8836,6 +8836,16 @@ S:       Maintained
>  T:     git git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git
>  F:     drivers/firmware/google/
>
> +GOOGLE TENSOR SoC SUPPORT
> +M:     Peter Griffin <peter.griffin@linaro.org>
> +L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +L:     linux-samsung-soc@vger.kernel.org
> +S:     Maintained
> +F:     Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> +F:     arch/arm64/boot/dts/google/
> +F:     drivers/clk/samsung/clk-gs101.c
> +F:     include/dt-bindings/clock/google,clk-gs101.h
> +
>  GPD POCKET FAN DRIVER
>  M:     Hans de Goede <hdegoede@redhat.com>
>  L:     platform-driver-x86@vger.kernel.org
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data

[Arnd Bergmann]

On Wed, Oct 11, 2023, at 20:48, Peter Griffin wrote:
> Add serial driver data for Google Tensor gs101 SoC.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

While the patch is now correct, I would point out a few
improvements we could make on top:

> +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> +	EXYNOS_COMMON_SERIAL_DRV_DATA(),
> +	/* rely on samsung,uart-fifosize DT property for fifosize */
> +	.fifosize = { 0 },
> +};
> +
>  #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
>  #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
>  #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
> +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)

Since this is now actually correct for any Exynos variant that
has the FIFO size listed in the DT, we could use a variable/macro
name that leads itself to being used by future chips.

There is also the question of whether we want to address the
ordering bug for the other SoC types. The way I understand it,
the .fifosize array logic is wrong because it relies on having
a particular alias for each of the ports to match the entry in
the array. For the exynosautov9, this would be trivially fixed
by using the same data as gs101 (since it already lists the
correct size in DT), but for the other ones we'd need a different
logic.

> @@ -2688,6 +2696,9 @@ static const struct platform_device_id 
> s3c24xx_serial_driver_ids[] = {
>  	}, {
>  		.name		= "artpec8-uart",
>  		.driver_data	= (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
> +	}, {
> +		.name		= "gs101-uart",
> +		.driver_data	= (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
>  	},
>  	{ },
>  };

I just noticed that the platform_device_id array is currently
only used for mach-crag6410, since everything else uses DT
based probing. s3c64xx is scheduled for removal in early 2024
(though no patch has been sent), and we can probably just
remove all the atags/platform_device based code when that happens.

      Arnd

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Krzysztof Kozlowski]

On 11/10/2023 23:48, William McVicker wrote:
> On 10/11/2023, Peter Griffin wrote:
>> Provide dt-schema documentation for Google gs101 SoC clock controller.
>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
>>
>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> 
> Tested-by: Will McVicker <willmcvicker@google.com>

And how do you perform testing of a binding?

Best regards,
Krzysztof

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Krzysztof Kozlowski]

On 11/10/2023 20:48, Peter Griffin wrote:
> Provide dt-schema documentation for Google gs101 SoC clock controller.
> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
>  include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
>  2 files changed, 357 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>  create mode 100644 include/dt-bindings/clock/google,gs101.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..f74494594b3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,125 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 SoC clock controller
> +
> +maintainers:
> +  - Peter Griffin <peter.griffin@linaro.org>
> +
> +description: |
> +  Google GS101 clock controller is comprised of several CMU units, generating
> +  clocks for different domains. Those CMU units are modeled as separate device
> +  tree nodes, and might depend on each other. The root clock in that clock tree
> +  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> +  clock in dts.
> +
> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> +  Each clock is assigned an identifier and client nodes can use this identifier
> +  to specify the clock which they consume. All clocks available for usage
> +  in clock consumer nodes are defined as preprocessor macros in
> +  'dt-bindings/clock/gs101.h' header.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - google,gs101-cmu-top
> +      - google,gs101-cmu-apm
> +      - google,gs101-cmu-misc
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +allOf:

No improvements here from v1.

> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-top
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:

enum:
  - google,gs101-cmu-apm
  - google,gs101-cmu-misc


Best regards,
Krzysztof

Re: [PATCH v3 07/20] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible

[Krzysztof Kozlowski]

On 11/10/2023 20:48, Peter Griffin wrote:
> gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9
> where more than one pin controller can do external wake-up interrupt.
> So add a dedicated compatible for it.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml      | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> index 1de91a51234d..7cddce761c46 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> @@ -29,6 +29,7 @@ description: |
>  properties:
>    compatible:
>      enum:
> +      - google,gs101-wakeup-eint
>        - samsung,s3c2410-wakeup-eint
>        - samsung,s3c2412-wakeup-eint
>        - samsung,s3c64xx-wakeup-eint
> @@ -99,6 +100,7 @@ allOf:
>              enum:
>                - samsung,exynos850-wakeup-eint
>                - samsung,exynosautov9-wakeup-eint
> +              - google,gs101-wakeup-eint

Please order alphabetically.


Best regards,
Krzysztof

Re: [PATCH v3 19/20] arm64: defconfig: Enable Google Tensor SoC

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add the Google Tensor SoC to the arm64 defconfig
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 5315789f4868..8a34603b1822 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -41,6 +41,7 @@ CONFIG_ARCH_BCMBCA=y
>  CONFIG_ARCH_BRCMSTB=y
>  CONFIG_ARCH_BERLIN=y
>  CONFIG_ARCH_EXYNOS=y
> +CONFIG_ARCH_GOOGLE_TENSOR=y
>  CONFIG_ARCH_SPARX5=y
>  CONFIG_ARCH_K3=y
>  CONFIG_ARCH_LG1K=y
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 15/20] watchdog: s3c2410_wdt: Add support for Google tensor SoCs

[Krzysztof Kozlowski]

On 11/10/2023 20:48, Peter Griffin wrote:
> This patch adds the compatibles and drvdata for the Google
> gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> to Exynos850 it has two watchdog instances, one for each cluster
> and has some control bits in PMU registers.
> 
> The watchdog IP found in gs101 SoCs also supports a few
> additional bits/features in the WTCON register which we add
> support for and an additional register detailed below.
> 
> dbgack-mask - Enables masking WDT interrupt and reset request
> according to asserted DBGACK input
> 
> windowed-mode - Enabled Windowed watchdog mode
> 
> Windowed watchdog mode also has an additional register WTMINCNT.
> If windowed watchdog is enabled and you reload WTCNT when the
> value is greater than WTMINCNT, it prompts interrupt or reset
> request as if the watchdog time has expired.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/watchdog/s3c2410_wdt.c | 127 ++++++++++++++++++++++++++++++---
>  1 file changed, 116 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 0b4bd883ff28..36c170047180 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -31,12 +31,14 @@
>  #define S3C2410_WTDAT		0x04
>  #define S3C2410_WTCNT		0x08
>  #define S3C2410_WTCLRINT	0x0c
> -
> +#define S3C2410_WTMINCNT	0x10
>  #define S3C2410_WTCNT_MAXCNT	0xffff
>  
> -#define S3C2410_WTCON_RSTEN	(1 << 0)
> -#define S3C2410_WTCON_INTEN	(1 << 2)
> -#define S3C2410_WTCON_ENABLE	(1 << 5)
> +#define S3C2410_WTCON_RSTEN		(1 << 0)
> +#define S3C2410_WTCON_INTEN		(1 << 2)
> +#define S3C2410_WTCON_ENABLE		(1 << 5)
> +#define S3C2410_WTCON_DBGACK_MASK	(1 << 16)
> +#define S3C2410_WTCON_WINDOWED_WD	(1 << 20)
>  
>  #define S3C2410_WTCON_DIV16	(0 << 3)
>  #define S3C2410_WTCON_DIV32	(1 << 3)
> @@ -51,6 +53,7 @@
>  
>  #define S3C2410_WATCHDOG_ATBOOT		(0)
>  #define S3C2410_WATCHDOG_DEFAULT_TIME	(15)
> +#define S3C2410_WINDOW_MULTIPLIER	2
>  
>  #define EXYNOS5_RST_STAT_REG_OFFSET		0x0404
>  #define EXYNOS5_WDT_DISABLE_REG_OFFSET		0x0408
> @@ -67,6 +70,13 @@
>  #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT	25
>  #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT	24
>  
> +#define GS_CLUSTER0_NONCPU_OUT			0x1220
> +#define GS_CLUSTER1_NONCPU_OUT			0x1420
> +#define GS_CLUSTER0_NONCPU_INT_EN		0x1244
> +#define GS_CLUSTER1_NONCPU_INT_EN		0x1444
> +#define GS_CLUSTER2_NONCPU_INT_EN		0x1644
> +#define GS_RST_STAT_REG_OFFSET			0x3B44
> +
>  /**
>   * DOC: Quirk flags for different Samsung watchdog IP-cores
>   *
> @@ -106,6 +116,8 @@
>  #define QUIRK_HAS_PMU_RST_STAT			(1 << 2)
>  #define QUIRK_HAS_PMU_AUTO_DISABLE		(1 << 3)
>  #define QUIRK_HAS_PMU_CNT_EN			(1 << 4)
> +#define QUIRK_HAS_DBGACK_BIT			(1 << 5)
> +#define QUIRK_HAS_WTMINCNT_REG			(1 << 6)
>  
>  /* These quirks require that we have a PMU register map */
>  #define QUIRKS_HAVE_PMUREG \
> @@ -263,6 +275,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
>  		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
>  };
>  
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> +	.mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = 0,
> +	.cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> +	.cnt_en_bit = 8,
> +	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> +	.mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = 1,
> +	.cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> +	.cnt_en_bit = 7,
> +	.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {

I do not see the difference between this and drv_data_gs101_cl0. Same
for cluster 1. Looks like these are compatible, so make them compatible.

Also same concerns as Guenter's has.

Best regards,
Krzysztof

Re: [PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data

[Krzysztof Kozlowski]

On 11/10/2023 20:48, Peter Griffin wrote:
> Add serial driver data for Google Tensor gs101 SoC.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/tty/serial/samsung_tty.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index 07fb8a9dac63..26bc52e681a4 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -2597,14 +2597,22 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
>  	.fifosize = { 256, 64, 64, 64 },
>  };
>  
> +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> +	EXYNOS_COMMON_SERIAL_DRV_DATA(),
> +	/* rely on samsung,uart-fifosize DT property for fifosize */

It's an optional property, so you cannot rely on it.

> +	.fifosize = { 0 },

Looks like it is compatible with exynos850_serial_drv_data, so most
likely it should be expressed as compatible in the bindings.



Best regards,
Krzysztof

Re: [PATCH v3 00/20] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board

[Krzysztof Kozlowski]

On 11/10/2023 20:48, Peter Griffin wrote:
> Hi folks,
> 
> Firstly, thanks to everyone who reviewed the v2/V1 series! V3 incorporates
> all the review feedback received so far.
> 

patch:47: new blank line at EOF.
patch:1321: new blank line at EOF.

Best regards,
Krzysztof

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Krzysztof Kozlowski]

On 11/10/2023 20:48, Peter Griffin wrote:

...

> diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> new file mode 100644
> index 000000000000..37fb0a4dc8d3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> @@ -0,0 +1,504 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC
> + *
> + * Copyright 2019-2023 Google LLC
> + *
> + */
> +
> +#include <dt-bindings/clock/google,gs101.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "google,gs101";
> +	#address-cells = <2>;
> +	#size-cells = <1>;
> +
> +	interrupt-parent = <&gic>;
> +
> +	aliases {
> +		pinctrl0 = &pinctrl_0;
> +		pinctrl1 = &pinctrl_1;
> +		pinctrl2 = &pinctrl_2;
> +		pinctrl3 = &pinctrl_3;
> +		pinctrl4 = &pinctrl_4;
> +		pinctrl5 = &pinctrl_5;
> +		pinctrl6 = &pinctrl_6;
> +		pinctrl7 = &pinctrl_7;
> +		serial0 = &serial_0;
> +	};
> +
> +	arm-pmu {

pmu-0

> +		compatible = "arm,armv8-pmuv3";
> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	dsu-pmu-0 {

pmu-1


> +		compatible = "arm,dsu-pmu";
> +		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
> +		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
> +		       <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> +	};
> +
> +	/* TODO replace with CCF clock */
> +	dummy_clk: oscillator {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <12345>;
> +		clock-output-names = "pclk";
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu4>;
> +				};
> +				core1 {
> +					cpu = <&cpu5>;
> +				};
> +			};
> +
> +			cluster2 {
> +				core0 {
> +					cpu = <&cpu6>;
> +				};
> +				core1 {
> +					cpu = <&cpu7>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0000>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +			capacity-dmips-mhz = <250>;
> +			dynamic-power-coefficient = <70>;
> +		};
> +
> +		cpu1: cpu@100 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0100>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +			capacity-dmips-mhz = <250>;
> +			dynamic-power-coefficient = <70>;
> +		};
> +
> +		cpu2: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0200>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +			capacity-dmips-mhz = <250>;
> +			dynamic-power-coefficient = <70>;
> +		};
> +
> +		cpu3: cpu@300 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0300>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +			capacity-dmips-mhz = <250>;
> +			dynamic-power-coefficient = <70>;
> +		};
> +
> +		cpu4: cpu@400 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0400>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> +			capacity-dmips-mhz = <620>;
> +			dynamic-power-coefficient = <284>;
> +		};
> +
> +		cpu5: cpu@500 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0500>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> +			capacity-dmips-mhz = <620>;
> +			dynamic-power-coefficient = <284>;
> +		};
> +
> +		cpu6: cpu@600 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0600>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&HERA_CPU_SLEEP>;
> +			capacity-dmips-mhz = <1024>;
> +			dynamic-power-coefficient = <650>;
> +		};
> +
> +		cpu7: cpu@700 {
> +			device_type = "cpu";
> +			compatible = "arm,armv8";
> +			reg = <0x0 0x0700>;
> +			enable-method = "psci";
> +			cpu-idle-states =  <&HERA_CPU_SLEEP>;
> +			capacity-dmips-mhz = <1024>;
> +			dynamic-power-coefficient = <650>;
> +		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> +				idle-state-name = "c2";
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010000>;
> +				entry-latency-us = <70>;
> +				exit-latency-us = <160>;
> +				min-residency-us = <2000>;
> +			};
> +
> +			ENYO_CPU_SLEEP: cpu-enyo-sleep {
> +				idle-state-name = "c2";
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010000>;
> +				entry-latency-us = <150>;
> +				exit-latency-us = <190>;
> +				min-residency-us = <2500>;
> +			};
> +
> +			HERA_CPU_SLEEP: cpu-hera-sleep {
> +				idle-state-name = "c2";
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010000>;
> +				entry-latency-us = <235>;
> +				exit-latency-us = <220>;
> +				min-residency-us = <3500>;
> +			};
> +		};
> +	};
> +
> +	/* bootloader requires ect node */
> +	ect {

This needs bindings.

> +		parameter_address = <0x90000000>;

No underscores in property names. Use hyphen.

> +		parameter_size = <0x53000>;

No underscores.

> +	};
> +
> +	ext_24_5m: clock-1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <24576000>;
> +		clock-output-names = "oscclk";
> +	};


Best regards,
Krzysztof

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Krzysztof Kozlowski]

On 11/10/2023 20:48, Peter Griffin wrote:
> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> phones. It features:
> * 4xA55 little cluster
> * 2xA76 Mid cluster
> * 2xX1 Big cluster
> 

...

> +	gpa10: gpa10-gpio-bank  {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> +			   <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	uart15_bus: uart15-bus-pins {
> +	       samsung,pins = "gpa2-3", "gpa2-4";
> +	       samsung,pin-function = <2>;

GS101_PIN_FUNC_2

> +	       samsung,pin-pud = <0>;

GS101_PIN_PULL_NONE

> +	};
> +
> +	uart16_bus: uart16-bus-pins {
> +	       samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> +	       samsung,pin-function = <GS101_PIN_FUNC_2>;
> +	       samsung,pin-pud = <GS101_PIN_PULL_NONE>;

But here it is correct...

> +	};
> +
> +	uart16_bus_rts: uart1-bus-rts-pins {
> +		samsung,pins = "gpa3-2";
> +		samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +		samsung,pin-val = <1>;

Why do you set UART RTS pin value?

> +	};
> +
> +	uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
> +		samsung,pins = "gpa3-1";
> +		samsung,pin-val = <1>;
> +	};
> +


Best regards,
Krzysztof

Re: [PATCH v3 18/20] arm64: dts: google: Add initial Oriole/pixel 6 board support

[Krzysztof Kozlowski]

On 11/10/2023 20:48, Peter Griffin wrote:
> Add initial board support for the Pixel 6 phone code named Oriole. This
> has been tested with a minimal busybox initramfs and boots to a shell.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  arch/arm64/boot/dts/google/Makefile         |  4 ++
>  arch/arm64/boot/dts/google/gs101-oriole.dts | 79 +++++++++++++++++++++
>  2 files changed, 83 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/google/Makefile
>  create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
> 
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> new file mode 100644
> index 000000000000..5cea8ff27141
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> +	gs101-oriole.dtb \
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
> new file mode 100644
> index 000000000000..3bebca989d34
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "gs101-pinctrl.h"
> +#include "gs101.dtsi"
> +
> +/ {
> +	model = "Oriole";
> +	compatible = "google,gs101-oriole", "google,gs101";
> +
> +	chosen {
> +		bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0";


Nothing improved here.

> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&key_voldown &key_volup &key_power>;
> +
> +		button-vol-down {
> +			label = "KEY_VOLUMEDOWN";
> +			linux,code = <KEY_VOLUMEDOWN>;
> +			gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +
> +		button-vol-up {
> +			label = "KEY_VOLUMEUP";
> +			linux,code = <KEY_VOLUMEUP>;
> +			gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +
> +		button-power {
> +			label = "KEY_POWER";
> +			linux,code = <KEY_POWER>;
> +			gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +	};
> +};
> +
> +&pinctrl_1 {
> +	key_voldown: key-voldown-pins {
> +		samsung,pins = "gpa7-3";
> +		samsung,pin-function = <0xf>;

GS101_PIN_FUNC_EINT

> +		samsung,pin-pud = <0>;

GS101_PIN_PULL_NONE

> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +
> +	key_volup: key-volup-pins {
> +		samsung,pins = "gpa8-1";
> +		samsung,pin-function = <0xf>;
> +		samsung,pin-pud = <0>;
> +		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +	};
> +};
> +
> +&pinctrl_0 {
> +	key_power: key-power-pins {
> +		samsung,pins = "gpa10-1";
> +		samsung,pin-function = <0xf>;
> +		samsung,pin-pud = <0>;


Best regards,
Krzysztof

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> phones. It features:
> * 4xA55 little cluster
> * 2xA76 Mid cluster
> * 2xX1 Big cluster
>
> This commit adds the basic device tree for gs101 (SoC).
> Further platform support will be added over time.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  arch/arm64/Kconfig.platforms                  |    6 +
>  arch/arm64/boot/dts/Makefile                  |    1 +
>  arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 +++++++++++++++++
>  arch/arm64/boot/dts/google/gs101-pinctrl.h    |   32 +
>  arch/arm64/boot/dts/google/gs101.dtsi         |  504 +++++++
>  5 files changed, 1818 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
>  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
>  create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 6069120199bb..a5ed1b719488 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -107,6 +107,12 @@ config ARCH_EXYNOS
>         help
>           This enables support for ARMv8 based Samsung Exynos SoC family.
>
> +config ARCH_GOOGLE_TENSOR
> +       bool "Google Tensor SoC fmaily"
> +       depends on ARCH_EXYNOS
> +       help
> +         Support for ARMv8 based Google Tensor platforms.
> +
>  config ARCH_SPARX5
>         bool "Microchip Sparx5 SoC family"
>         select PINCTRL
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..a4ee7b628114 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -13,6 +13,7 @@ subdir-y += broadcom
>  subdir-y += cavium
>  subdir-y += exynos
>  subdir-y += freescale
> +subdir-y += google
>  subdir-y += hisilicon
>  subdir-y += intel
>  subdir-y += lg
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> new file mode 100644
> index 000000000000..ba88000c3ed8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> @@ -0,0 +1,1275 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright 2019-2023 Google LLC
> + *

This line is not needed. Also, maybe also add Linaro copyright here?

> + */
> +
> +#include "gs101-pinctrl.h"
> +
> +/* GPIO_ALIVE */
> +&pinctrl_0 {

Why not just rename it to pinctrl_alive and remove the comment? The
same goes for all pinctrl nodes below.

> +       gpa0: gpa0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

Here and further: please align it to be at the same indentation level
as above line.

> +                          <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa1: gpa1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa2: gpa2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa3: gpa3-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa4: gpa4-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa5: gpa5-gpio-bank  {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa9: gpa9-gpio-bank  {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa10: gpa10-gpio-bank  {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       uart15_bus: uart15-bus-pins {
> +              samsung,pins = "gpa2-3", "gpa2-4";
> +              samsung,pin-function = <2>;
> +              samsung,pin-pud = <0>;

Could above two lines be replaced with some meaningful consts? I see
it's done below.

> +       };
> +
> +       uart16_bus: uart16-bus-pins {
> +              samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> +              samsung,pin-function = <GS101_PIN_FUNC_2>;
> +              samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +       };
> +
> +       uart16_bus_rts: uart1-bus-rts-pins {
> +               samsung,pins = "gpa3-2";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-val = <1>;
> +       };
> +
> +       uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
> +               samsung,pins = "gpa3-1";
> +               samsung,pin-val = <1>;
> +       };
> +
> +       uart16_bus_tx_con: uart1-bus-tx-con-pins {
> +               samsung,pins = "gpa3-1";
> +               samsung,pin-function = <1>;

Named const?

> +       };
> +
> +       uart17_bus: uart17-bus-pins {
> +              samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
> +              samsung,pin-function = <2>;
> +              samsung,pin-pud = <0>;

Here and further: if possible, try to use named constants.

> +       };
> +
> +       spi15_bus: spi15-bus-pins {
> +               samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi15_cs: spi15-cs-pins {
> +               samsung,pins = "gpa4-3";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +};
> +
> +/* GPIO_FAR_ALIVE */
> +&pinctrl_1 {
> +       gpa6: gpa6-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa7: gpa7-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa8: gpa8-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       gpa11: gpa11-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> +                          <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +};
> +
> +/* GPIO_GSACORE */
> +&pinctrl_2 {
> +       gps0: gps0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gps1: gps1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gps2: gps2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
> +/* GPIO_GSACTRL */
> +&pinctrl_3 {
> +       gps3: gps3-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +};
> +
> +/* GPIO_HSI1 */
> +&pinctrl_6 {
> +       gph0: gph0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gph1: gph1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       pcie0_clkreq: pcie0-clkreq-pins{
> +               samsung,pins = "gph0-1";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <3>;
> +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +               samsung,pin-con-pdn = <3>;
> +               samsung,pin-pud-pdn = <3>;

What are those two properties? I don't see them documented in
dt-bindings or being mentioned in the driver.

> +       };
> +
> +       pcie0_perst: pcie0-perst-pins {
> +               samsung,pins = "gph0-0";
> +               samsung,pin-function = <1>;
> +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +               samsung,pin-con-pdn = <3>;
> +       };
> +};
> +
> +/* GPIO_HSI2 */
> +&pinctrl_7 {
> +       gph2: gph2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gph3: gph3-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gph4: gph4-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       sd2_clk: sd2-clk-pins {
> +               samsung,pins = "gph4-0";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +       };
> +
> +       sd2_cmd: sd2-cmd-pins {
> +               samsung,pins = "gph4-1";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <3>;
> +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +       };
> +
> +       sd2_bus1: sd2-bus-width1-pins {
> +               samsung,pins = "gph4-2";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <3>;
> +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +       };
> +
> +       sd2_bus4: sd2-bus-width4-pins {
> +               samsung,pins = "gph4-3", "gph4-4", "gph4-5";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <3>;
> +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +       };
> +
> +       sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
> +               samsung,pins = "gph4-0";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
> +               samsung,pins = "gph4-0";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
> +               samsung,pins = "gph4-0";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> +       };
> +
> +       sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
> +               samsung,pins = "gph4-0";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +       };
> +
> +       ufs_rst_n: ufs-rst-n-pins {
> +               samsung,pins = "gph3-1";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-con-pdn = <3>;
> +               samsung,pin-pud-pdn = <0>;
> +       };
> +
> +       ufs_refclk_out: ufs-refclk-out-pins {
> +               samsung,pins = "gph3-0";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-con-pdn = <3>;
> +               samsung,pin-pud-pdn = <0>;
> +       };
> +
> +       pcie1_clkreq: pcie1-clkreq-pins {
> +               samsung,pins = "gph2-1";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <3>;
> +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +               samsung,pin-con-pdn = <3>;
> +               samsung,pin-pud-pdn = <3>;
> +       };
> +
> +       pcie1_perst: pcie1-perst-pins {
> +               samsung,pins = "gph2-0";
> +               samsung,pin-function = <1>;
> +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> +               samsung,pin-con-pdn = <3>;
> +       };
> +};
> +
> +/* GPIO_PERIC0 */
> +&pinctrl_4 {
> +       gpp0: gpp0-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp1: gpp1-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp2: gpp2-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp3: gpp3-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp4: gpp4-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp5: gpp5-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp6: gpp6-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp7: gpp7-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp8: gpp8-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp9: gpp9-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp10: gpp10-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp11: gpp11-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp12: gpp12-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp13: gpp13-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp14: gpp14-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp15: gpp15-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp16: gpp16-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp17: gpp17-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp18: gpp18-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp19: gpp19-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       /* USI_PERIC0_UART_DBG */
> +       uart0_bus: uart0-bus-pins {
> +               samsung,pins = "gpp1-2", "gpp1-3";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       disp_te_pri_on: disp-te-pri-on-pins {
> +               samsung,pins = "gpp0-3";
> +               samsung,pin-function = <0xf>;
> +       };
> +
> +       disp_te_pri_off: disp-te-pri-off-pins {
> +               samsung,pins = "gpp0-3";
> +               samsung,pin-function = <0>;
> +       };
> +
> +       disp_te_sec_on: disp-te-sec-on-pins {
> +               samsung,pins = "gpp0-4";
> +               samsung,pin-function = <0xf>;
> +       };
> +
> +       disp_te_sec_off: disp-te-sec-off-pins {
> +               samsung,pins = "gpp0-4";
> +               samsung,pin-function = <0>;
> +       };
> +
> +       sensor_mclk1_out: sensor-mclk1-out-pins {
> +               samsung,pins = "gpp3-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk1_fn: sensor-mclk1-fn-pins {
> +               samsung,pins = "gpp3-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk2_out: sensor-mclk2-out-pins {
> +               samsung,pins = "gpp5-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk2_fn: sensor-mclk2-fn-pins {
> +               samsung,pins = "gpp5-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk3_out: sensor-mclk3-out-pins {
> +               samsung,pins = "gpp7-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk3_fn: sensor-mclk3-fn-pins {
> +               samsung,pins = "gpp7-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk4_out: sensor-mclk4-out-pins {
> +               samsung,pins = "gpp9-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk4_fn: sensor-mclk4-fn-pins {
> +               samsung,pins = "gpp9-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk5_out: sensor-mclk5-out-pins {
> +               samsung,pins = "gpp11-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk5_fn: sensor-mclk5-fn-pins {
> +               samsung,pins = "gpp11-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk6_out: sensor-mclk6-out-pins {
> +               samsung,pins = "gpp13-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk6_fn: sensor-mclk6-fn-pins {
> +               samsung,pins = "gpp13-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk7_out: sensor-mclk7-out-pins {
> +               samsung,pins = "gpp15-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk7_fn: sensor-mclk7-fn-pins {
> +               samsung,pins = "gpp15-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk8_out: sensor-mclk8-out-pins {
> +               samsung,pins = "gpp17-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       sensor_mclk8_fn: sensor-mclk8-fn-pins {
> +               samsung,pins = "gpp17-0";
> +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> +       };
> +
> +       hsi2c14_bus: hsi2c14-bus-pins {
> +               samsung,pins = "gpp18-0", "gpp18-1";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart14_bus_single: uart14-bus-pins {
> +               samsung,pins = "gpp18-0", "gpp18-1",
> +                              "gpp18-2", "gpp18-3";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi14_bus: spi14-bus-pins {
> +               samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi14_cs: spi14-cs-pins {
> +               samsung,pins = "gpp18-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi14_cs_func: spi14-cs-func-pins {
> +               samsung,pins = "gpp18-3";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c8_bus: hsi2c8-bus-pins {
> +               samsung,pins = "gpp16-0", "gpp16-1";
> +               samsung,pin-function = <GS101_PIN_FUNC_3>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +               samsung,pin-pud-pdn = <GS101_PIN_PDN_OUT0>;
> +       };
> +
> +       uart8_bus_single: uart8-bus-pins {
> +               samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
> +                              "gpp16-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi8_bus: spi8-bus-pins {
> +               samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi8_cs: spi8-cs-pins {
> +               samsung,pins = "gpp16-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi8_cs_func: spi8-cs-func-pins {
> +               samsung,pins = "gpp16-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c7_bus: hsi2c7-bus-pins {
> +               samsung,pins = "gpp14-0", "gpp14-1";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart7_bus_single: uart7-bus-pins {
> +               samsung,pins = "gpp14-0", "gpp14-1",
> +                              "gpp14-2", "gpp14-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi7_bus: spi7-bus-pins {
> +               samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi7_cs: spi7-cs-pins {
> +               samsung,pins = "gpp14-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi7_cs_func: spi7-cs-func-pins {
> +               samsung,pins = "gpp14-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c6_bus: hsi2c6-bus-pins {
> +               samsung,pins = "gpp12-0", "gpp12-1";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart6_bus_single: uart6-bus-pins {
> +               samsung,pins = "gpp12-0", "gpp12-1",
> +                              "gpp12-2", "gpp12-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi6_bus: spi6-bus-pins {
> +               samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi6_cs: spi6-cs-pins {
> +               samsung,pins = "gpp12-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi6_cs_func: spi6-cs-func-pins {
> +               samsung,pins = "gpp12-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c5_bus: hsi2c5-bus-pins {
> +               samsung,pins = "gpp10-0", "gpp10-1";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart5_bus_single: uart5-bus-pins {
> +               samsung,pins = "gpp10-0", "gpp10-1",
> +                              "gpp10-2", "gpp10-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi5_bus: spi5-bus-pins {
> +               samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +               samsung,pin-function = <GS101_PIN_FUNC_3>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
> +               samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
> +       };
> +
> +       spi5_cs_func: spi5-cs-func-pins {
> +               samsung,pins = "gpp10-3";
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +               samsung,pin-function = <GS101_PIN_FUNC_3>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
> +               samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
> +       };
> +
> +       hsi2c4_bus: hsi2c4-bus-pins {
> +               samsung,pins = "gpp8-0", "gpp8-1";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart4_bus_single: uart4-bus-pins {
> +               samsung,pins = "gpp8-0", "gpp8-1",
> +                              "gpp8-2", "gpp8-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi4_bus: spi4-bus-pins {
> +               samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi4_cs: spi4-cs-pins {
> +               samsung,pins = "gpp8-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi4_cs_func: spi4-cs-func-pins {
> +               samsung,pins = "gpp8-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c3_bus: hsi2c3-bus-pins {
> +               samsung,pins = "gpp6-0", "gpp6-1";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart3_bus_single: uart3-bus-pins {
> +               samsung,pins = "gpp6-0", "gpp6-1",
> +                              "gpp6-2", "gpp6-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi3_bus: spi3-bus-pins {
> +               samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi3_cs: spi3-cs-pins {
> +               samsung,pins = "gpp6-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi3_cs_func: spi3-cs-func-pins {
> +               samsung,pins = "gpp6-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c2_bus: hsi2c2-bus-pins {
> +               samsung,pins = "gpp4-0", "gpp4-1";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart2_bus_single: uart2-bus-pins {
> +               samsung,pins = "gpp4-0", "gpp4-1",
> +                              "gpp4-2", "gpp4-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi2_bus: spi2-bus-pins {
> +               samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi2_cs: spi2-cs-pins {
> +               samsung,pins = "gpp4-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi2_cs_func: spi2-cs-func-pins {
> +               samsung,pins = "gpp4-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c1_bus: hsi2c1-bus-pins {
> +               samsung,pins = "gpp2-0", "gpp2-1";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart1_bus_single: uart1-bus-pins {
> +               samsung,pins = "gpp2-0", "gpp2-1",
> +                              "gpp2-2", "gpp2-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi1_bus: spi1-bus-pins {
> +               samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi1_cs: spi1-cs-pins {
> +               samsung,pins = "gpp2-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi1_cs_func: spi1-cs-func-pins {
> +               samsung,pins = "gpp2-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +};
> +
> +/* GPIO_PERIC1 */
> +&pinctrl_5 {
> +       gpp20: gpp20-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp21: gpp21-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp22: gpp22-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp23: gpp23-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp24: gpp24-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp25: gpp25-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp26: gpp26-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       gpp27: gpp27-gpio-bank {
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       hsi2c13_bus: hsi2c13-bus-pins  {
> +               samsung,pins = "gpp25-0", "gpp25-1";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart13_bus_single: uart13-bus-pins {
> +              samsung,pins = "gpp25-0", "gpp25-1",
> +                             "gpp25-2", "gpp25-3";
> +              samsung,pin-function = <2>;
> +              samsung,pin-pud = <0>;
> +       };
> +
> +       spi13_bus: spi13-bus-pins {
> +               samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi13_cs: spi13-cs-pins {
> +               samsung,pins = "gpp25-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi13_cs_func: spi13-cs-func-pins {
> +               samsung,pins = "gpp25-3";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c12_bus: hsi2c12-bus-pins {
> +               samsung,pins = "gpp23-4", "gpp23-5";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart12_bus_single: uart12-bus-pins {
> +               samsung,pins = "gpp23-4", "gpp23-5",
> +                              "gpp23-6", "gpp23-7";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi12_bus: spi12-bus-pins {
> +               samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi14_cs2: spi14-cs2-pins {
> +               samsung,pins = "gpp23-6";
> +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi12_cs: spi12-cs-pins {
> +               samsung,pins = "gpp23-7";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi12_cs_func: spi12-cs-func-pins {
> +               samsung,pins = "gpp23-7";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c11_bus: hsi2c11-bus-pins {
> +               samsung,pins = "gpp23-0", "gpp23-1";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart11_bus_single: uart11-bus-pins {
> +               samsung,pins = "gpp23-0", "gpp23-1",
> +                              "gpp23-2", "gpp23-3";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi11_bus: spi11-bus-pins {
> +               samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi11_cs: spi11-cs-pins {
> +               samsung,pins = "gpp23-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi11_cs_func: spi11-cs-func-pins {
> +               samsung,pins = "gpp23-3";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c10_bus: hsi2c10-bus-pins {
> +               samsung,pins = "gpp21-0", "gpp21-1";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart10_bus_single: uart10-bus-pins {
> +               samsung,pins = "gpp21-0", "gpp21-1",
> +                              "gpp21-2", "gpp21-3";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi10_bus: spi10-bus-pins {
> +               samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi10_cs: spi10-cs-pins {
> +               samsung,pins = "gpp21-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi10_cs_func: spi10-cs-func-pins {
> +               samsung,pins = "gpp21-3";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c9_bus: hsi2c9-bus-pins {
> +               samsung,pins = "gpp20-4", "gpp20-5";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart9_bus_single: uart9-bus-pins {
> +               samsung,pins = "gpp20-4", "gpp20-5",
> +                              "gpp20-6", "gpp20-7";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi9_bus: spi9-bus-pins {
> +               samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi9_cs: spi9-cs-pins {
> +               samsung,pins = "gpp20-7";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi9_cs_func: spi9-cs-func-pins {
> +               samsung,pins = "gpp20-7";
> +               samsung,pin-function = <2>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       hsi2c0_bus: hsi2c0-bus-pins {
> +               samsung,pins = "gpp20-0", "gpp20-1";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       uart0_bus_single: uart0-bus-pins {
> +               samsung,pins = "gpp20-0", "gpp20-1",
> +                              "gpp20-2", "gpp20-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +       };
> +
> +       spi0_bus: spi0-bus-pins {
> +               samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi0_cs: spi0-cs-pins {
> +               samsung,pins = "gpp20-3";
> +               samsung,pin-function = <1>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       spi0_cs_func: spi0-cs-func-pins {
> +               samsung,pins = "gpp20-3";
> +               samsung,pin-function = <3>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +};
> +
> diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> new file mode 100644
> index 000000000000..16c54888f4bb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Pinctrl binding constants for GS101
> + *
> + * Copyright (c) 2020-2023 Google, LLC.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
> +#define __DT_BINDINGS_PINCTRL_GS101_H__
> +
> +#define GS101_PIN_PULL_NONE            0
> +#define GS101_PIN_PULL_DOWN            1
> +#define GS101_PIN_PULL_UP              3
> +
> +/* Pin function in power down mode */
> +#define GS101_PIN_PDN_OUT0             0
> +#define GS101_PIN_PDN_OUT1             1
> +#define GS101_PIN_PDN_INPUT            2
> +#define GS101_PIN_PDN_PREV             3
> +
> +/* GS101 drive strengths */
> +#define GS101_PIN_DRV_2_5_MA           0
> +#define GS101_PIN_DRV_5_MA             1
> +#define GS101_PIN_DRV_7_5_MA           2
> +#define GS101_PIN_DRV_10_MA            3
> +
> +#define GS101_PIN_FUNC_INPUT           0
> +#define GS101_PIN_FUNC_OUTPUT          1
> +#define GS101_PIN_FUNC_2               2
> +#define GS101_PIN_FUNC_3               3
> +

Maybe it's possible to somehow re-use already existing values in
arch/arm64/boot/dts/exynos/exynos-pinctrl.h?

> +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
> diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> new file mode 100644
> index 000000000000..37fb0a4dc8d3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> @@ -0,0 +1,504 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * GS101 SoC
> + *
> + * Copyright 2019-2023 Google LLC
> + *

This line is not needed. Also (but not sure): maybe add the author and
Linaro copyright?

> + */
> +
> +#include <dt-bindings/clock/google,gs101.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       compatible = "google,gs101";
> +       #address-cells = <2>;
> +       #size-cells = <1>;
> +
> +       interrupt-parent = <&gic>;
> +
> +       aliases {
> +               pinctrl0 = &pinctrl_0;
> +               pinctrl1 = &pinctrl_1;
> +               pinctrl2 = &pinctrl_2;
> +               pinctrl3 = &pinctrl_3;
> +               pinctrl4 = &pinctrl_4;
> +               pinctrl5 = &pinctrl_5;
> +               pinctrl6 = &pinctrl_6;
> +               pinctrl7 = &pinctrl_7;
> +               serial0 = &serial_0;
> +       };
> +
> +       arm-pmu {
> +               compatible = "arm,armv8-pmuv3";

Is there any more specifi Cortex PMU compatible for this chip?

> +               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

Please try to keep it to 80 characters per line.

> +       };
> +
> +       dsu-pmu-0 {
> +               compatible = "arm,dsu-pmu";
> +               interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
> +               cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
> +                      <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> +       };
> +
> +       /* TODO replace with CCF clock */
> +       dummy_clk: oscillator {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <12345>;
> +               clock-output-names = "pclk";
> +       };
> +
> +       cpus {
> +               #address-cells = <2>;

Why 2-cells is needed here? If you make it 1, all below reg properties
can be made 1-cell, which removes not needed 0x0.

> +               #size-cells = <0>;
> +
> +               cpu-map {
> +                       cluster0 {
> +                               core0 {
> +                                       cpu = <&cpu0>;
> +                               };
> +                               core1 {
> +                                       cpu = <&cpu1>;
> +                               };
> +                               core2 {
> +                                       cpu = <&cpu2>;
> +                               };
> +                               core3 {
> +                                       cpu = <&cpu3>;
> +                               };
> +                       };
> +
> +                       cluster1 {
> +                               core0 {
> +                                       cpu = <&cpu4>;
> +                               };
> +                               core1 {
> +                                       cpu = <&cpu5>;
> +                               };
> +                       };
> +
> +                       cluster2 {
> +                               core0 {
> +                                       cpu = <&cpu6>;
> +                               };
> +                               core1 {
> +                                       cpu = <&cpu7>;
> +                               };
> +                       };
> +               };
> +
> +               cpu0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";

Is there maybe any more specific Cortex compatible?

> +                       reg = <0x0 0x0000>;
> +                       enable-method = "psci";
> +                       cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +                       capacity-dmips-mhz = <250>;
> +                       dynamic-power-coefficient = <70>;
> +               };
> +
> +               cpu1: cpu@100 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x0 0x0100>;
> +                       enable-method = "psci";
> +                       cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +                       capacity-dmips-mhz = <250>;
> +                       dynamic-power-coefficient = <70>;
> +               };
> +
> +               cpu2: cpu@200 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x0 0x0200>;
> +                       enable-method = "psci";
> +                       cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +                       capacity-dmips-mhz = <250>;
> +                       dynamic-power-coefficient = <70>;
> +               };
> +
> +               cpu3: cpu@300 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x0 0x0300>;
> +                       enable-method = "psci";
> +                       cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> +                       capacity-dmips-mhz = <250>;
> +                       dynamic-power-coefficient = <70>;
> +               };
> +
> +               cpu4: cpu@400 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x0 0x0400>;
> +                       enable-method = "psci";
> +                       cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> +                       capacity-dmips-mhz = <620>;
> +                       dynamic-power-coefficient = <284>;
> +               };
> +
> +               cpu5: cpu@500 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x0 0x0500>;
> +                       enable-method = "psci";
> +                       cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> +                       capacity-dmips-mhz = <620>;
> +                       dynamic-power-coefficient = <284>;
> +               };
> +
> +               cpu6: cpu@600 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x0 0x0600>;
> +                       enable-method = "psci";
> +                       cpu-idle-states =  <&HERA_CPU_SLEEP>;
> +                       capacity-dmips-mhz = <1024>;
> +                       dynamic-power-coefficient = <650>;
> +               };
> +
> +               cpu7: cpu@700 {
> +                       device_type = "cpu";
> +                       compatible = "arm,armv8";
> +                       reg = <0x0 0x0700>;
> +                       enable-method = "psci";
> +                       cpu-idle-states =  <&HERA_CPU_SLEEP>;
> +                       capacity-dmips-mhz = <1024>;
> +                       dynamic-power-coefficient = <650>;
> +               };
> +
> +               idle-states {
> +                       entry-method = "psci";
> +
> +                       ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> +                               idle-state-name = "c2";
> +                               compatible = "arm,idle-state";
> +                               arm,psci-suspend-param = <0x0010000>;
> +                               entry-latency-us = <70>;
> +                               exit-latency-us = <160>;
> +                               min-residency-us = <2000>;
> +                       };
> +
> +                       ENYO_CPU_SLEEP: cpu-enyo-sleep {
> +                               idle-state-name = "c2";
> +                               compatible = "arm,idle-state";
> +                               arm,psci-suspend-param = <0x0010000>;
> +                               entry-latency-us = <150>;
> +                               exit-latency-us = <190>;
> +                               min-residency-us = <2500>;
> +                       };
> +
> +                       HERA_CPU_SLEEP: cpu-hera-sleep {
> +                               idle-state-name = "c2";
> +                               compatible = "arm,idle-state";
> +                               arm,psci-suspend-param = <0x0010000>;
> +                               entry-latency-us = <235>;
> +                               exit-latency-us = <220>;
> +                               min-residency-us = <3500>;
> +                       };
> +               };
> +       };
> +
> +       /* bootloader requires ect node */
> +       ect {
> +               parameter_address = <0x90000000>;
> +               parameter_size = <0x53000>;
> +       };

The bootloader doesn't work if you just remove this?

> +
> +       ext_24_5m: clock-1 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <24576000>;

The frequency is probably should be set in board dts file. Because the
crystal is actually soldered on the board, not in SoC.

> +               clock-output-names = "oscclk";
> +       };
> +
> +       ext_200m: clock-2 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <200000000>;

Ditto.

> +               clock-output-names = "ext-200m";
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       reserved_memory: reserved-memory {
> +               #address-cells = <2>;

Doesn't look like 2-cell address is really needed here.

> +               #size-cells = <1>;
> +               ranges;
> +
> +               gsa_reserved_protected: gsa@90200000 {
> +                       reg = <0x0 0x90200000 0x400000>;
> +                       no-map;
> +               };
> +
> +               tpu_fw_reserved: tpu-fw@93000000 {
> +                       reg = <0x0 0x93000000 0x1000000>;
> +                       no-map;
> +               };
> +
> +               aoc_reserve: aoc@94000000 {
> +                       reg = <0x0 0x94000000 0x03000000>;
> +                       no-map;
> +               };
> +
> +               abl_reserved: abl@f8800000 {
> +                       reg = <0x0 0xf8800000 0x02000000>;
> +                       no-map;
> +               };
> +
> +               dss_log_reserved: dss-log-reserved@fd3f0000 {
> +                       reg = <0 0xfd3f0000 0x0000e000>;
> +                       no-map;
> +               };
> +
> +               debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
> +                       reg = <0 0xfd3fe000 0x00001000>;
> +                       no-map;
> +               };
> +
> +               bldr_log_reserved: bldr-log-reserved@fd800000 {
> +                       reg = <0 0xfd800000 0x00100000>;
> +                       no-map;
> +               };
> +
> +               bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
> +                       reg = <0 0xfd900000 0x00002000>;
> +                       no-map;
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> +               clock-frequency = <24576000>;
> +       };
> +
> +       soc: soc@0 {
> +               compatible = "simple-bus";
> +               #address-cells = <2>;

Is 2 cells are really needed for the addresses in this node? I only
see 32-bit addresses below in reg properties.

> +               #size-cells = <1>;
> +               ranges;
> +
> +               cmu_misc: clock-controller@10010000 {
> +                       compatible = "google,gs101-cmu-misc";
> +                       reg = <0x0 0x10010000 0x8000>;
> +                       #clock-cells = <1>;
> +                       clocks =  <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
> +                       clock-names = "oscclk", "dout_cmu_misc_bus";
> +               };
> +
> +               watchdog_cl0: watchdog@10060000 {
> +                       compatible = "google,gs101-wdt";
> +                       reg = <0x0 0x10060000 0x100>;
> +                       interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
> +                       clock-names = "watchdog", "watchdog_src";
> +                       samsung,syscon-phandle = <&pmu_system_controller>;
> +                       samsung,cluster-index = <0>;
> +               };
> +
> +               watchdog_cl1: watchdog@10070000 {
> +                       compatible = "google,gs101-wdt";
> +                       reg = <0x0 0x10070000 0x100>;
> +                       interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
> +                       clock-names = "watchdog", "watchdog_src";
> +                       samsung,syscon-phandle = <&pmu_system_controller>;
> +                       samsung,cluster-index = <1>;
> +                       status = "disabled";
> +               };
> +
> +               gic: interrupt-controller@10400000 {
> +                    compatible = "arm,gic-v3";
> +                    #interrupt-cells = <3>;
> +                    interrupt-controller;
> +                    reg = <0x0 0x10400000 0x10000>,    /* GICD */
> +                          <0x0 0x10440000 0x100000>;   /* GICR * 8 */
> +                    interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               sysreg_peric0: syscon@10821000 {
> +                       compatible = "google,gs101-peric0-sysreg", "syscon";
> +                       reg = <0x0 0x10821000 0x40000>;
> +               };
> +
> +               /* GPIO_PERIC0 */

This comment won't be needed if you rename pinctrl_4 -> pinctrl_peric0 :)

> +               pinctrl_4: pinctrl@10840000 {
> +                       compatible = "google,gs101-pinctrl";
> +                       reg = <0x0 0x10840000 0x00001000>;
> +                       interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               serial_0: serial@10a00000 {
> +                       compatible = "google,gs101-uart";
> +                       reg = <0x0 0x10a00000 0xc0>;
> +                       reg-io-width = <4>;
> +                       samsung,uart-fifosize = <256>;
> +                       interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> +                       clock-names = "uart", "clk_uart_baud0";
> +               };

Does this SoC have USI blocks? If so, maybe this node should be made a
children of some USI node?

> +
> +               /* GPIO_PERIC1 */
> +               pinctrl_5: pinctrl@10c40000 {
> +                       compatible = "google,gs101-pinctrl";
> +                       reg = <0x0 0x10C40000 0x00001000>;
> +                       interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               sysreg_peric1: syscon@10c21000 {
> +                       compatible = "google,gs101-peric1-sysreg", "syscon";
> +                       reg = <0x0 0x10C21000 0x40000>;
> +               };
> +
> +               /* GPIO_HSI1 */
> +               pinctrl_6: pinctrl@11840000 {
> +                       compatible = "google,gs101-pinctrl";
> +                       reg = <0x0 0x11840000 0x00001000>;
> +                       interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               /* GPIO_HSI2 */
> +               pinctrl_7: pinctrl@14440000 {
> +                       compatible = "google,gs101-pinctrl";
> +                       reg = <0x0 0x14440000 0x00001000>;
> +                       interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               cmu_apm: clock-controller@17400000 {
> +                       compatible = "google,gs101-cmu-apm";
> +                       reg = <0x0 0x17400000 0x8000>;
> +                       #clock-cells = <1>;
> +
> +                       clocks = <&ext_24_5m>;
> +                       clock-names = "oscclk";
> +               };
> +
> +               sysreg_apm: syscon@174204e0 {
> +                       compatible = "google,gs101-apm-sysreg", "syscon";
> +                       reg = <0x0 0x174204e0 0x1000>;
> +               };

Sure it doesn't need any clock? I remember having some issues until I
declared a clock for some Exynos850 sysreg node.

> +
> +               pmu_system_controller: system-controller@17460000 {
> +                       compatible = "google,gs101-pmu", "syscon";
> +                       reg = <0x0 0x17460000 0x10000>;
> +               };
> +
> +               /* GPIO_ALIVE */
> +               pinctrl_0: pinctrl@174d0000 {
> +                       compatible = "google,gs101-pinctrl";
> +                       reg = <0x0 0x174d0000 0x00001000>;
> +                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

Are you sure all those interrupts are actually needed? Please check
this patch: daeb1c2b50fb ("arm64: dts: exynos: drop incorrectly placed
wakeup interrupts in Exynos850"). If you decide to remove those
interrupts, then bindings doc should be changed too I guess.

> +
> +                       wakeup-interrupt-controller {
> +                               compatible = "google,gs101-wakeup-eint";
> +                       };
> +               };
> +
> +               /* GPIO_FAR_ALIVE */
> +               pinctrl_1: pinctrl@174e0000 {
> +                       compatible = "google,gs101-pinctrl";
> +                       reg = <0x0 0x174e0000 0x00001000>;
> +                       interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +
> +                       wakeup-interrupt-controller {
> +                               compatible = "google,gs101-wakeup-eint";
> +                       };
> +               };
> +
> +               /* GPIO_GSACTRL */
> +               pinctrl_3: pinctrl@17940000 {
> +                       compatible = "google,gs101-pinctrl";
> +                       reg = <0x0 0x17940000 0x00001000>;
> +               };
> +
> +               /* GPIO_GSACORE */
> +               pinctrl_2: pinctrl@17a80000 {
> +                       compatible = "google,gs101-pinctrl";
> +                       reg = <0x0 0x17a80000 0x00001000>;
> +               };
> +
> +               cmu_top: clock-controller@1e080000 {

Move it up to other cmus, to make nodes under soc ordered alphabetically?

> +                       compatible = "google,gs101-cmu-top";
> +                       reg = <0x0 0x1e080000 0x8000>;
> +                       #clock-cells = <1>;
> +
> +                       clocks = <&ext_24_5m>;
> +                       clock-names = "oscclk";
> +               };
> +       };
> +};
> +
> +#include "gs101-pinctrl.dtsi"
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Krzysztof Kozlowski]

On 12/10/2023 09:23, Sam Protsenko wrote:
>> +
>> +               cpu0: cpu@0 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,armv8";
> 
> Is there maybe any more specific Cortex compatible?

Thanks for noticing. It must be a specific compatible. This is *ONLY*
for software models.

I really wished people stopped upstreaming junk vendor DTS, but instead
take recent, clean DTS and customize it. The approach with junk vendor
DTS is always a pain. For everyone.


Best regards,
Krzysztof

Re: [PATCH v3 18/20] arm64: dts: google: Add initial Oriole/pixel 6 board support

[Sam Protsenko]

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Add initial board support for the Pixel 6 phone code named Oriole. This
> has been tested with a minimal busybox initramfs and boots to a shell.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  arch/arm64/boot/dts/google/Makefile         |  4 ++
>  arch/arm64/boot/dts/google/gs101-oriole.dts | 79 +++++++++++++++++++++
>  2 files changed, 83 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/google/Makefile
>  create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts
>
> diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
> new file mode 100644
> index 000000000000..5cea8ff27141
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_GOOGLE_TENSOR) += \
> +       gs101-oriole.dtb \
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
> new file mode 100644
> index 000000000000..3bebca989d34
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;

Why is this needed? Is that really not possible to build this board
dts as actual dtb, not dtbo (and remove this 'plugin' line)? If GS
bootloader is similar to Exynos850 bootloader, it should be possible
to only use dtb, and flash empty dtbo image. Just a thought.

> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "gs101-pinctrl.h"
> +#include "gs101.dtsi"
> +
> +/ {
> +       model = "Oriole";
> +       compatible = "google,gs101-oriole", "google,gs101";
> +
> +       chosen {
> +               bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0";

Why is that earlycon is needed here? The serial should work fine (and
actually even better) without that. Might be very useful for debugging
though, but in production dts I'd remove that bit. Also, not sure why
console is needed. Isn't it enough to just have something like:

        stdout-path = &serial_0;

inside of /chosen node?

Btw, why isn't serial node enabled somewhere in this dts?

> +       };
> +
> +       gpio-keys {
> +               compatible = "gpio-keys";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&key_voldown &key_volup &key_power>;
> +
> +               button-vol-down {
> +                       label = "KEY_VOLUMEDOWN";
> +                       linux,code = <KEY_VOLUMEDOWN>;
> +                       gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
> +                       wakeup-source;
> +               };
> +
> +               button-vol-up {
> +                       label = "KEY_VOLUMEUP";
> +                       linux,code = <KEY_VOLUMEUP>;
> +                       gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
> +                       wakeup-source;
> +               };
> +
> +               button-power {
> +                       label = "KEY_POWER";
> +                       linux,code = <KEY_POWER>;
> +                       gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
> +                       wakeup-source;
> +               };
> +       };
> +};
> +
> +&pinctrl_1 {
> +       key_voldown: key-voldown-pins {
> +               samsung,pins = "gpa7-3";
> +               samsung,pin-function = <0xf>;
> +               samsung,pin-pud = <0>;

Here and further: maybe replace pid-function and pin-pud hard-coded
values with corresponding named constants?

> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +
> +       key_volup: key-volup-pins {
> +               samsung,pins = "gpa8-1";
> +               samsung,pin-function = <0xf>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +};
> +
> +&pinctrl_0 {
> +       key_power: key-power-pins {
> +               samsung,pins = "gpa10-1";
> +               samsung,pin-function = <0xf>;
> +               samsung,pin-pud = <0>;
> +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> +       };
> +};
> +
> +&watchdog_cl0 {
> +       timeout-sec = <30>;

No status = "okay" here? The same question goes for wdt_cl1.

> +};
> --
> 2.42.0.655.g421f12c284-goog
>

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Peter Griffin]

Hi Krzysztof,

On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 11/10/2023 23:48, William McVicker wrote:
> > On 10/11/2023, Peter Griffin wrote:
> >> Provide dt-schema documentation for Google gs101 SoC clock controller.
> >> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> >>
> >> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> >
> > Tested-by: Will McVicker <willmcvicker@google.com>
>
> And how do you perform testing of a binding?

I guess if William is using my script to build and flash the kernel it actually
runs the DTC checks as part of the build process.

See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44

regards,

Peter.

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Krzysztof Kozlowski]

On 12/10/2023 10:56, Peter Griffin wrote:
> Hi Krzysztof,
> 
> On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 11/10/2023 23:48, William McVicker wrote:
>>> On 10/11/2023, Peter Griffin wrote:
>>>> Provide dt-schema documentation for Google gs101 SoC clock controller.
>>>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
>>>>
>>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>>
>>> Tested-by: Will McVicker <willmcvicker@google.com>
>>
>> And how do you perform testing of a binding?
> 
> I guess if William is using my script to build and flash the kernel it actually
> runs the DTC checks as part of the build process.
> 
> See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44

So it is a build test? We do not consider building as a test procedure,
otherwise I should add my and robots tested-by to many other patches.
Shall I consider other Tested-by tags here also as build-tested only?

Best regards,
Krzysztof

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Peter Griffin]

Hi Krzysztof,

Thanks for your review.

On Thu, 12 Oct 2023 at 07:11, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 11/10/2023 20:48, Peter Griffin wrote:
> > Provide dt-schema documentation for Google gs101 SoC clock controller.
> > Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
> >  include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
> >  2 files changed, 357 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> >  create mode 100644 include/dt-bindings/clock/google,gs101.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> > new file mode 100644
> > index 000000000000..f74494594b3b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> > @@ -0,0 +1,125 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Google GS101 SoC clock controller
> > +
> > +maintainers:
> > +  - Peter Griffin <peter.griffin@linaro.org>
> > +
> > +description: |
> > +  Google GS101 clock controller is comprised of several CMU units, generating
> > +  clocks for different domains. Those CMU units are modeled as separate device
> > +  tree nodes, and might depend on each other. The root clock in that clock tree
> > +  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> > +  clock in dts.
> > +
> > +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> > +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> > +
> > +  Each clock is assigned an identifier and client nodes can use this identifier
> > +  to specify the clock which they consume. All clocks available for usage
> > +  in clock consumer nodes are defined as preprocessor macros in
> > +  'dt-bindings/clock/gs101.h' header.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - google,gs101-cmu-top
> > +      - google,gs101-cmu-apm
> > +      - google,gs101-cmu-misc
> > +
> > +  clocks:
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  clock-names:
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  "#clock-cells":
> > +    const: 1
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +allOf:
>
> No improvements here from v1.

Seems I missed the
"required:" go before "allOf:" comment here. Sorry about that I've fixed that
in v4.

Seems like a few other exynos clock yaml bindings need that fix to.

>
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: google,gs101-cmu-top
> > +
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: External reference clock (24.576 MHz)
> > +
> > +        clock-names:
> > +          items:
> > +            - const: oscclk
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
>
> enum:
>   - google,gs101-cmu-apm
>   - google,gs101-cmu-misc

Ok just to be clear, are you saying I should have it like this?

  - if:
      properties:
        compatible:
          contains:
            enum:
              - google,gs101-cmu-misc
              - google,gs101-cmu-apm

    then:
      properties:
        clocks:
          minItems: 1
          items:
            - description: External reference clock (24.576 MHz)
            - description: Misc bus clock (from CMU_TOP)

        clock-names:
          minItems: 1
          items:
            - const: oscclk
            - const: dout_cmu_misc_bus

Instead of a dedicated  'if: const <compatible> then: ' for each CMU?

If I'm wrong above would you been kind enough to elaborate a bit
more on what you want, as all this dt-schema yaml stuff is a bit new
for me

Many thanks,

Peter

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Krzysztof Kozlowski]

On 12/10/2023 12:15, Peter Griffin wrote:

>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: google,gs101-cmu-top
>>> +
>>> +    then:
>>> +      properties:
>>> +        clocks:
>>> +          items:
>>> +            - description: External reference clock (24.576 MHz)
>>> +
>>> +        clock-names:
>>> +          items:
>>> +            - const: oscclk
>>> +
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>
>> enum:
>>   - google,gs101-cmu-apm
>>   - google,gs101-cmu-misc
> 
> Ok just to be clear, are you saying I should have it like this?
> 
>   - if:
>       properties:
>         compatible:
>           contains:
>             enum:
>               - google,gs101-cmu-misc

No, my bad, I meant apm + google,gs101-cmu-top

>               - google,gs101-cmu-apm




Best regards,
Krzysztof

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Peter Griffin]

Hi Krzysztof

On Thu, 12 Oct 2023 at 11:20, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 12/10/2023 12:15, Peter Griffin wrote:
>
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>> +            const: google,gs101-cmu-top
> >>> +
> >>> +    then:
> >>> +      properties:
> >>> +        clocks:
> >>> +          items:
> >>> +            - description: External reference clock (24.576 MHz)
> >>> +
> >>> +        clock-names:
> >>> +          items:
> >>> +            - const: oscclk
> >>> +
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>
> >> enum:
> >>   - google,gs101-cmu-apm
> >>   - google,gs101-cmu-misc
> >
> > Ok just to be clear, are you saying I should have it like this?
> >
> >   - if:
> >       properties:
> >         compatible:
> >           contains:
> >             enum:
> >               - google,gs101-cmu-misc
>
> No, my bad, I meant apm + google,gs101-cmu-top
>
> >               - google,gs101-cmu-apm

Ah OK, yes that makes more sense. Thanks for the clarification :)

Peter.

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Peter Griffin]

Hi Krzysztof,

On Thu, 12 Oct 2023 at 10:36, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 12/10/2023 10:56, Peter Griffin wrote:
> > Hi Krzysztof,
> >
> > On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 11/10/2023 23:48, William McVicker wrote:
> >>> On 10/11/2023, Peter Griffin wrote:
> >>>> Provide dt-schema documentation for Google gs101 SoC clock controller.
> >>>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> >>>>
> >>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> >>>
> >>> Tested-by: Will McVicker <willmcvicker@google.com>
> >>
> >> And how do you perform testing of a binding?
> >
> > I guess if William is using my script to build and flash the kernel it actually
> > runs the DTC checks as part of the build process.
> >
> > See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44
>
> So it is a build test? We do not consider building as a test procedure,
> otherwise I should add my and robots tested-by to many other patches.

Ok so I should only add the Tested-by on the .c patches?

> Shall I consider other Tested-by tags here also as build-tested only?

No. William indicated here
https://lore.kernel.org/linux-arm-kernel/ZScZu-QB2LmB4CSM@google.com/T/#mbd96a26b725d6c85eb4193de8cd70ff277bc728e
that he booted it on his Oriole device.

Peter.

Re: [PATCH v3 04/20] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings

[Peter Griffin]

Hi Sam,

Thanks for the review.

On Wed, 11 Oct 2023 at 23:58, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the
> > dt-schema documentation.
> >
> > gs101 SoC has two CPU clusters and each cluster has its own dedicated
> > watchdog timer (similar to exynos850 and exynosautov9 SoCs).
> >
> > These WDT instances are controlled using different bits in PMU
> > registers.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  .../devicetree/bindings/watchdog/samsung-wdt.yaml      | 10 ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> > index 8fb6656ba0c2..67c8767f0499 100644
> > --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> > +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
> > @@ -17,6 +17,8 @@ description: |+
> >  properties:
> >    compatible:
> >      enum:
> > +      - google,gs101-wdt                      # for Google gs101
> > +      - google,gs201-wdt                      # for Google gs201
> >        - samsung,s3c2410-wdt                   # for S3C2410
> >        - samsung,s3c6410-wdt                   # for S3C6410, S5PV210 and Exynos4
> >        - samsung,exynos5250-wdt                # for Exynos5250
> > @@ -42,13 +44,13 @@ properties:
> >    samsung,cluster-index:
> >      $ref: /schemas/types.yaml#/definitions/uint32
> >      description:
> > -      Index of CPU cluster on which watchdog is running (in case of Exynos850)
> > +      Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01)
>
> Please stick to 80 characters per line when possible.

Will fix in v4.

Peter

Re: [PATCH v3 05/20] dt-bindings: arm: google: Add bindings for Google ARM platforms

[Peter Griffin]

Hi Sam,

Thanks for the review.

On Thu, 12 Oct 2023 at 00:06, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > This introduces bindings and dt-schema for the Google tensor SoCs.
> > Currently just gs101 and pixel 6 are supported.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> >  .../devicetree/bindings/arm/google.yaml       | 46 +++++++++++++++++++
> >  1 file changed, 46 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/google.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentation/devicetree/bindings/arm/google.yaml
> > new file mode 100644
> > index 000000000000..167945e4d5ee
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/google.yaml
> > @@ -0,0 +1,46 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/google.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Google Tensor platforms
> > +
> > +maintainers:
> > +  - Peter Griffin <peter.griffin@linaro.org>
> > +
> > +description: |
> > +  ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
> > +  devices.
> > +
> > +  Currently upstream this is devices using "gs101" SoC which is found in Pixel
> > +  6, Pixel 6 Pro and Pixel 6a.
> > +
> > +  Google have a few different names for the SoC.
> > +  - Marketing name ("Tensor")
> > +  - Codename ("Whitechapel")
> > +  - SoC ID ("gs101")
> > +  - Die ID ("S5P9845");
> > +
> > +  Likewise there are a couple of names for the actual device
> > +  - Marketing name ("Pixel 6")
> > +  - Codename ("Oriole")
> > +
> > +  Devicetrees should use the lowercased SoC ID and lowercased board codename.
> > +  e.g. gs101 and gs101-oriole
> > +
> > +properties:
> > +  $nodename:
> > +    const: '/'
> > +  compatible:
> > +    oneOf:
> > +
>
> Is that empty line is actually needed here?

Will fix in v4.

Peter

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Krzysztof Kozlowski]

On 12/10/2023 12:45, Peter Griffin wrote:
> Hi Krzysztof,
> 
> On Thu, 12 Oct 2023 at 10:36, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 12/10/2023 10:56, Peter Griffin wrote:
>>> Hi Krzysztof,
>>>
>>> On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 11/10/2023 23:48, William McVicker wrote:
>>>>> On 10/11/2023, Peter Griffin wrote:
>>>>>> Provide dt-schema documentation for Google gs101 SoC clock controller.
>>>>>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
>>>>>>
>>>>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>>>>
>>>>> Tested-by: Will McVicker <willmcvicker@google.com>
>>>>
>>>> And how do you perform testing of a binding?
>>>
>>> I guess if William is using my script to build and flash the kernel it actually
>>> runs the DTC checks as part of the build process.
>>>
>>> See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44
>>
>> So it is a build test? We do not consider building as a test procedure,
>> otherwise I should add my and robots tested-by to many other patches.
> 
> Ok so I should only add the Tested-by on the .c patches?

In my opinion, if someone performs only build testing, it is not a
testing. You cannot test the bindings other way than build testing, at
least I do not know such way. Of course other code like C or DTS affects
hardware so it can be tested.

> 
>> Shall I consider other Tested-by tags here also as build-tested only?
> 
> No. William indicated here
> https://lore.kernel.org/linux-arm-kernel/ZScZu-QB2LmB4CSM@google.com/T/#mbd96a26b725d6c85eb4193de8cd70ff277bc728e
> that he booted it on his Oriole device.


OK, I was just a bit confused.

Best regards,
Krzysztof

Re: [PATCH v3 09/20] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}

[Peter Griffin]

Hi Sam,

On Thu, 12 Oct 2023 at 00:19, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > These plls are found in the Tensor gs101 SoC found in the Pixel 6.
> >
> > pll0516x: Integer PLL with high frequency
> > pll0517x: Integer PLL with middle frequency
> > pll0518x: Integer PLL with low frequency
> >
> > PLL0516x
> > FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
> >
> > PLL0517x and PLL0518x
> > FOUT = (MDIV * FIN)/PDIV*2^SDIV)
> >
> > The PLLs are similar enough to pll_0822x that the same code can handle
> > both. The main difference is the change in the fout formula for the
> > high frequency 0516 pll.
> >
> > Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> > MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
> >
> > When defining the PLL the "con" parameter should be set to CON3
> > register, like this
> >
> > PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> >     PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> >     NULL),
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  drivers/clk/samsung/clk-pll.c | 9 ++++++++-
> >  drivers/clk/samsung/clk-pll.h | 3 +++
> >  2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> > index 74934c6182ce..4ef9fea2a425 100644
> > --- a/drivers/clk/samsung/clk-pll.c
> > +++ b/drivers/clk/samsung/clk-pll.c
> > @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
> >         pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
> >         sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
> >
> > -       fvco *= mdiv;
> > +       if (pll->type == pll_0516x)
> > +               fvco = fvco * 2 * mdiv;
> > +       else
> > +               fvco *= mdiv;
> > +
>
> Can be written like this I guess:
>
>        fvco *= mdiv;
>        if (pll->type == pll_0516x)
>               fvco *= 2;
>
> if you think it's more neat. Other than that:
>
> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

I will update like you suggest and add your Reviewed-by tag.

regards,

Peter.

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Peter Griffin]

Hi Sam,

Thanks for the review.

On Thu, 12 Oct 2023 at 01:07, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > CMU_TOP is the top level clock management unit which contains PLLs, muxes
> > and gates that feed the other clock management units.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  drivers/clk/samsung/Kconfig     |    9 +
> >  drivers/clk/samsung/Makefile    |    2 +
> >  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
> >  3 files changed, 1562 insertions(+)
> >  create mode 100644 drivers/clk/samsung/clk-gs101.c
> >
> > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> > index 76a494e95027..14362ec9c543 100644
> > --- a/drivers/clk/samsung/Kconfig
> > +++ b/drivers/clk/samsung/Kconfig
> > @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
> >         select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
> >         select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> >         select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> > +       select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
> >         select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> >
> >  config S3C64XX_COMMON_CLK
> > @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
> >           status of the certains clocks from SoC, but it could also be tied to
> >           other devices as an input clock.
> >
> > +config GOOGLE_GS101_COMMON_CLK
> > +       bool "Google gs101 clock controller support" if COMPILE_TEST
> > +       depends on COMMON_CLK_SAMSUNG
> > +       depends on EXYNOS_ARM64_COMMON_CLK
> > +       help
> > +         Support for the clock controller present on the Google gs101 SoC.
> > +         Choose Y here only if you build for this SoC.
> > +
>
> Why is that new option needed? From the look of it, it could be just a
> part of EXYNOS_ARM64_COMMON_CLK. Like clk-exynos850 or
> clk-exynosautov9. Is there any particular feature that makes it SoC
> special?

No, it could also be added to EXYNOS_ARM64_COMMON_CLK. I was following
the example set by TESLA_FSD which is another custom Exynos based chipset
that added its own config option.

Krzysztof do you have any preference on this?

>
> >  config TESLA_FSD_COMMON_CLK
> >         bool "Tesla FSD clock controller support" if COMPILE_TEST
> >         depends on COMMON_CLK_SAMSUNG
> > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> > index ebbeacabe88f..49146937d957 100644
> > --- a/drivers/clk/samsung/Makefile
> > +++ b/drivers/clk/samsung/Makefile
> > @@ -21,6 +21,8 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
> >  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynos7885.o
> >  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynos850.o
> >  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynosautov9.o
> > +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK)  += clk-gs101.o
> >  obj-$(CONFIG_S3C64XX_COMMON_CLK)       += clk-s3c64xx.o
> >  obj-$(CONFIG_S5PV210_COMMON_CLK)       += clk-s5pv210.o clk-s5pv210-audss.o
> >  obj-$(CONFIG_TESLA_FSD_COMMON_CLK)     += clk-fsd.o
> > +
> > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> > new file mode 100644
> > index 000000000000..e2c62754b1eb
> > --- /dev/null
> > +++ b/drivers/clk/samsung/clk-gs101.c
> > @@ -0,0 +1,1551 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2023 Linaro Ltd.
> > + * Author: Peter Griffin <peter.griffin@linaro.org>
> > + *
> > + * Common Clock Framework support for GS101.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include <dt-bindings/clock/google,gs101.h>
> > +
> > +#include "clk.h"
> > +#include "clk-exynos-arm64.h"
> > +
> > +/* NOTE: Must be equal to the last clock ID increased by one */
> > +#define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
>
> Please use tab for indentations like that. In this and subsequent patches.

will fix

>
> > +
> > +/* ---- CMU_TOP ------------------------------------------------------------- */
> > +
> > +/* Register Offset definitions for CMU_TOP (0x1e080000) */
> > +
> > +#define PLL_LOCKTIME_PLL_SHARED0                       0x0000
> > +#define PLL_LOCKTIME_PLL_SHARED1                       0x0004
> > +#define PLL_LOCKTIME_PLL_SHARED2                       0x0008
> > +#define PLL_LOCKTIME_PLL_SHARED3                       0x000c
> > +#define PLL_LOCKTIME_PLL_SPARE                         0x0010
> > +#define PLL_CON0_PLL_SHARED0                           0x0100
> > +#define PLL_CON1_PLL_SHARED0                           0x0104
> > +#define PLL_CON2_PLL_SHARED0                           0x0108
> > +#define PLL_CON3_PLL_SHARED0                           0x010c
> > +#define PLL_CON4_PLL_SHARED0                           0x0110
> > +#define PLL_CON0_PLL_SHARED1                           0x0140
> > +#define PLL_CON1_PLL_SHARED1                           0x0144
> > +#define PLL_CON2_PLL_SHARED1                           0x0148
> > +#define PLL_CON3_PLL_SHARED1                           0x014c
> > +#define PLL_CON4_PLL_SHARED1                           0x0150
> > +#define PLL_CON0_PLL_SHARED2                           0x0180
> > +#define PLL_CON1_PLL_SHARED2                           0x0184
> > +#define PLL_CON2_PLL_SHARED2                           0x0188
> > +#define PLL_CON3_PLL_SHARED2                           0x018c
> > +#define PLL_CON4_PLL_SHARED2                           0x0190
> > +#define PLL_CON0_PLL_SHARED3                           0x01c0
> > +#define PLL_CON1_PLL_SHARED3                           0x01c4
> > +#define PLL_CON2_PLL_SHARED3                           0x01c8
> > +#define PLL_CON3_PLL_SHARED3                           0x01cc
> > +#define PLL_CON4_PLL_SHARED3                           0x01d0
> > +#define PLL_CON0_PLL_SPARE                             0x0200
> > +#define PLL_CON1_PLL_SPARE                             0x0204
> > +#define PLL_CON2_PLL_SPARE                             0x0208
> > +#define PLL_CON3_PLL_SPARE                             0x020c
> > +#define PLL_CON4_PLL_SPARE                             0x0210
> > +#define CMU_CMU_TOP_CONTROLLER_OPTION                  0x0800
> > +#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0             0x0810
> > +#define CMU_HCHGEN_CLKMUX_CMU_BOOST                    0x0840
> > +#define CMU_HCHGEN_CLKMUX_TOP_BOOST                    0x0844
> > +#define CMU_HCHGEN_CLKMUX                              0x0850
> > +#define POWER_FAIL_DETECT_PLL                          0x0864
> > +#define EARLY_WAKEUP_FORCED_0_ENABLE                   0x0870
> > +#define EARLY_WAKEUP_FORCED_1_ENABLE                   0x0874
> > +#define EARLY_WAKEUP_APM_CTRL                          0x0878
> > +#define EARLY_WAKEUP_CLUSTER0_CTRL                     0x087c
> > +#define EARLY_WAKEUP_DPU_CTRL                          0x0880
> > +#define EARLY_WAKEUP_CSIS_CTRL                         0x0884
> > +#define EARLY_WAKEUP_APM_DEST                          0x0890
> > +#define EARLY_WAKEUP_CLUSTER0_DEST                     0x0894
> > +#define EARLY_WAKEUP_DPU_DEST                          0x0898
> > +#define EARLY_WAKEUP_CSIS_DEST                         0x089c
> > +#define EARLY_WAKEUP_SW_TRIG_APM                       0x08c0
> > +#define EARLY_WAKEUP_SW_TRIG_APM_SET                   0x08c4
> > +#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR                 0x08c8
> > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0                  0x08d0
> > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET              0x08d4
> > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR            0x08d8
> > +#define EARLY_WAKEUP_SW_TRIG_DPU                       0x08e0
> > +#define EARLY_WAKEUP_SW_TRIG_DPU_SET                   0x08e4
> > +#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR                 0x08e8
> > +#define EARLY_WAKEUP_SW_TRIG_CSIS                      0x08f0
> > +#define EARLY_WAKEUP_SW_TRIG_CSIS_SET                  0x08f4
> > +#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR                        0x08f8
> > +
> > +#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS                  0x1000
> > +#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS                        0x1004
> > +#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS                        0x1008
> > +#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS                        0x100c
> > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0                        0x1010
> > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1                        0x1014
> > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2                        0x1018
> > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3                        0x101c
> > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4                        0x1020
> > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5                        0x1024
> > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6                        0x1028
> > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7                        0x102c
> > +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST               0x1030
> > +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1       0x1034
> > +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS                        0x1038
> > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG              0x103c
> > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH           0x1040
> > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH           0x1044
> > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH           0x1048
> > +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS                        0x104c
> > +#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS                        0x1050
> > +#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS                 0x1054
> > +#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS                 0x1058
> > +#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS                  0x105c
> > +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D                 0x1060
> > +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL                        0x1064
> > +#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA               0x1068
> > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD                        0x106c
> > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB                 0x1070
> > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH              0x1074
> > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0                        0x1078
> > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1                        0x107c
> > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC                        0x1080
> > +#define CLK_CON_MUX_MUX_CLKCMU_HPM                     0x1084
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS                        0x1088
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC              0x108c
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD           0x1090
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG           0x1094
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS                        0x1098
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE               0x109c
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS                        0x10a0
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD           0x10a4
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE               0x10a8
> > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD           0x10ac
> > +#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS                 0x10b0
> > +#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS                 0x10b4
> > +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC               0x10b8
> > +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC               0x10bc
> > +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC                 0x10c0
> > +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP                        0x10c4
> > +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH              0x10c8
> > +#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS                        0x10cc
> > +#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS                        0x10d0
> > +#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS                 0x10d4
> > +#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA                 0x10d8
> > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS              0x10dc
> > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP               0x10e0
> > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS              0x10e4
> > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP               0x10e8
> > +#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS                 0x10ec
> > +#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1       0x10f0
> > +#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF              0x10f4
> > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS                 0x10f8
> > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU                 0x10fc
> > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL              0x1100
> > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART                        0x1104
> > +#define CLK_CON_MUX_MUX_CMU_CMUREF                     0x1108
> > +
> > +#define CLK_CON_DIV_CLKCMU_BO_BUS                      0x1800
> > +#define CLK_CON_DIV_CLKCMU_BUS0_BUS                    0x1804
> > +#define CLK_CON_DIV_CLKCMU_BUS1_BUS                    0x1808
> > +#define CLK_CON_DIV_CLKCMU_BUS2_BUS                    0x180c
> > +#define CLK_CON_DIV_CLKCMU_CIS_CLK0                    0x1810
> > +#define CLK_CON_DIV_CLKCMU_CIS_CLK1                    0x1814
> > +#define CLK_CON_DIV_CLKCMU_CIS_CLK2                    0x1818
> > +#define CLK_CON_DIV_CLKCMU_CIS_CLK3                    0x181c
> > +#define CLK_CON_DIV_CLKCMU_CIS_CLK4                    0x1820
> > +#define CLK_CON_DIV_CLKCMU_CIS_CLK5                    0x1824
> > +#define CLK_CON_DIV_CLKCMU_CIS_CLK6                    0x1828
> > +#define CLK_CON_DIV_CLKCMU_CIS_CLK7                    0x182c
> > +#define CLK_CON_DIV_CLKCMU_CORE_BUS                    0x1830
> > +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG                  0x1834
> > +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH               0x1838
> > +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH               0x183c
> > +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH               0x1840
> > +#define CLK_CON_DIV_CLKCMU_CSIS_BUS                    0x1844
> > +#define CLK_CON_DIV_CLKCMU_DISP_BUS                    0x1848
> > +#define CLK_CON_DIV_CLKCMU_DNS_BUS                     0x184c
> > +#define CLK_CON_DIV_CLKCMU_DPU_BUS                     0x1850
> > +#define CLK_CON_DIV_CLKCMU_EH_BUS                      0x1854
> > +#define CLK_CON_DIV_CLKCMU_G2D_G2D                     0x1858
> > +#define CLK_CON_DIV_CLKCMU_G2D_MSCL                    0x185c
> > +#define CLK_CON_DIV_CLKCMU_G3AA_G3AA                   0x1860
> > +#define CLK_CON_DIV_CLKCMU_G3D_BUSD                    0x1864
> > +#define CLK_CON_DIV_CLKCMU_G3D_GLB                     0x1868
> > +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH                  0x186c
> > +#define CLK_CON_DIV_CLKCMU_GDC_GDC0                    0x1870
> > +#define CLK_CON_DIV_CLKCMU_GDC_GDC1                    0x1874
> > +#define CLK_CON_DIV_CLKCMU_GDC_SCSC                    0x1878
> > +#define CLK_CON_DIV_CLKCMU_HPM                         0x187c
> > +#define CLK_CON_DIV_CLKCMU_HSI0_BUS                    0x1880
> > +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC                  0x1884
> > +#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD               0x1888
> > +#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG               0x188c
> > +#define CLK_CON_DIV_CLKCMU_HSI1_BUS                    0x1890
> > +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE                   0x1894
> > +#define CLK_CON_DIV_CLKCMU_HSI2_BUS                    0x1898
> > +#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD               0x189c
> > +#define CLK_CON_DIV_CLKCMU_HSI2_PCIE                   0x18a0
> > +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD               0x18a4
> > +#define CLK_CON_DIV_CLKCMU_IPP_BUS                     0x18a8
> > +#define CLK_CON_DIV_CLKCMU_ITP_BUS                     0x18ac
> > +#define CLK_CON_DIV_CLKCMU_MCSC_ITSC                   0x18b0
> > +#define CLK_CON_DIV_CLKCMU_MCSC_MCSC                   0x18b4
> > +#define CLK_CON_DIV_CLKCMU_MFC_MFC                     0x18b8
> > +#define CLK_CON_DIV_CLKCMU_MIF_BUSP                    0x18bc
> > +#define CLK_CON_DIV_CLKCMU_MISC_BUS                    0x18c0
> > +#define CLK_CON_DIV_CLKCMU_MISC_SSS                    0x18c4
> > +#define CLK_CON_DIV_CLKCMU_OTP                         0x18c8
> > +#define CLK_CON_DIV_CLKCMU_PDP_BUS                     0x18cc
> > +#define CLK_CON_DIV_CLKCMU_PDP_VRA                     0x18d0
> > +#define CLK_CON_DIV_CLKCMU_PERIC0_BUS                  0x18d4
> > +#define CLK_CON_DIV_CLKCMU_PERIC0_IP                   0x18d8
> > +#define CLK_CON_DIV_CLKCMU_PERIC1_BUS                  0x18dc
> > +#define CLK_CON_DIV_CLKCMU_PERIC1_IP                   0x18e0
> > +#define CLK_CON_DIV_CLKCMU_TNR_BUS                     0x18e4
> > +#define CLK_CON_DIV_CLKCMU_TPU_BUS                     0x18e8
> > +#define CLK_CON_DIV_CLKCMU_TPU_TPU                     0x18ec
> > +#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL                  0x18f0
> > +#define CLK_CON_DIV_CLKCMU_TPU_UART                    0x18f4
> > +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST               0x18f8
> > +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF                 0x18fc
> > +#define CLK_CON_DIV_PLL_SHARED0_DIV2                   0x1900
> > +#define CLK_CON_DIV_PLL_SHARED0_DIV3                   0x1904
> > +#define CLK_CON_DIV_PLL_SHARED0_DIV4                   0x1908
> > +#define CLK_CON_DIV_PLL_SHARED0_DIV5                   0x190c
> > +#define CLK_CON_DIV_PLL_SHARED1_DIV2                   0x1910
> > +#define CLK_CON_DIV_PLL_SHARED1_DIV3                   0x1914
> > +#define CLK_CON_DIV_PLL_SHARED1_DIV4                   0x1918
> > +#define CLK_CON_DIV_PLL_SHARED2_DIV2                   0x191c
> > +#define CLK_CON_DIV_PLL_SHARED3_DIV2                   0x1920
> > +
> > +/* CLK_CON_GAT_UPDATES */
> > +#define CLK_CON_GAT_CLKCMU_BUS0_BOOST                  0x2000
> > +#define CLK_CON_GAT_CLKCMU_BUS1_BOOST                  0x2004
> > +#define CLK_CON_GAT_CLKCMU_BUS2_BOOST                  0x2008
> > +#define CLK_CON_GAT_CLKCMU_CORE_BOOST                  0x200c
> > +#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST                        0x2010
> > +#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST                        0x2014
> > +#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST                        0x2018
> > +#define CLK_CON_GAT_CLKCMU_MIF_BOOST                   0x201c
> > +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH                  0x2020
> > +#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS                 0x2024
> > +#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS               0x2028
> > +#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS               0x202c
> > +#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS               0x2030
> > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0               0x2034
> > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1               0x2038
> > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2               0x203c
> > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3               0x2040
> > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4               0x2044
> > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5               0x2048
> > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6               0x204c
> > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7               0x2050
> > +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST              0x2054
> > +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS               0x2058
> > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS         0x205c
> > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH          0x2060
> > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH          0x2064
> > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH          0x2068
> > +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS               0x206c
> > +#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS               0x2070
> > +#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS                        0x2074
> > +#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS                        0x2078
> > +#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS                 0x207c
> > +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D                        0x2080
> > +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL               0x2084
> > +#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA              0x2088
> > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD               0x208c
> > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB                        0x2090
> > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH             0x2094
> > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0               0x2098
> > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1               0x209c
> > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC               0x20a0
> > +#define CLK_CON_GAT_GATE_CLKCMU_HPM                    0x20a4
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS               0x20a8
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC             0x20ac
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD          0x20b0
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG          0x20b4
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS               0x20b8
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE              0x20bc
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS               0x20c0
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD           0x20c4
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE              0x20c8
> > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD          0x20cc
> > +#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS                        0x20d0
> > +#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS                        0x20d4
> > +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC              0x20d8
> > +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC              0x20dc
> > +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC                        0x20e0
> > +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP               0x20e4
> > +#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS               0x20e8
> > +#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS               0x20ec
> > +#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS                        0x20f0
> > +#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA                        0x20f4
> > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS             0x20f8
> > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP              0x20fc
> > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS             0x2100
> > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP              0x2104
> > +#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS                        0x2108
> > +#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF             0x210c
> > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS                        0x2110
> > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU                        0x2114
> > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL             0x2118
> > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART               0x211c
> > +
> > +#define DMYQCH_CON_CMU_TOP_CMUREF_QCH                  0x3000
> > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0             0x3004
> > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1             0x3008
> > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2             0x300c
> > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3             0x3010
> > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4             0x3014
> > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5             0x3018
> > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6             0x301c
> > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7             0x3020
> > +#define DMYQCH_CON_OTP_QCH                             0x3024
> > +#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP                 0x3c00
> > +#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP                   0x3c10
> > +#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP                   0x3c14
> > +#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP                   0x3c18
> > +#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP                   0x3c1c
> > +#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP                   0x3c20
> > +#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP                   0x3c24
> > +#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP                   0x3c28
> > +#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP                   0x3c2c
> > +#define MIFMIRROR_QUEUE_CTRL_REG                       0x3e00
> > +#define MIFMIRROR_QUEUE_ENTRY0                         0x3e10
> > +#define MIFMIRROR_QUEUE_ENTRY1                         0x3e14
> > +#define MIFMIRROR_QUEUE_ENTRY2                         0x3e18
> > +#define MIFMIRROR_QUEUE_ENTRY3                         0x3e1c
> > +#define MIFMIRROR_QUEUE_ENTRY4                         0x3e20
> > +#define MIFMIRROR_QUEUE_ENTRY5                         0x3e24
> > +#define MIFMIRROR_QUEUE_ENTRY6                         0x3e28
> > +#define MIFMIRROR_QUEUE_ENTRY7                         0x3e2c
> > +#define MIFMIRROR_QUEUE_BUSY                           0x3e30
> > +#define GENERALIO_ACD_CHANNEL_0                                0x3f00
> > +#define GENERALIO_ACD_CHANNEL_1                                0x3f04
> > +#define GENERALIO_ACD_CHANNEL_2                                0x3f08
> > +#define GENERALIO_ACD_CHANNEL_3                                0x3f0c
> > +#define GENERALIO_ACD_MASK                             0x3f14
> > +
> > +static const unsigned long cmu_top_clk_regs[] __initconst = {
> > +       PLL_LOCKTIME_PLL_SHARED0,
> > +       PLL_LOCKTIME_PLL_SHARED1,
> > +       PLL_LOCKTIME_PLL_SHARED2,
> > +       PLL_LOCKTIME_PLL_SHARED3,
> > +       PLL_LOCKTIME_PLL_SPARE,
> > +       PLL_CON0_PLL_SHARED0,
> > +       PLL_CON1_PLL_SHARED0,
> > +       PLL_CON2_PLL_SHARED0,
> > +       PLL_CON3_PLL_SHARED0,
> > +       PLL_CON4_PLL_SHARED0,
> > +       PLL_CON0_PLL_SHARED1,
> > +       PLL_CON1_PLL_SHARED1,
> > +       PLL_CON2_PLL_SHARED1,
> > +       PLL_CON3_PLL_SHARED1,
> > +       PLL_CON4_PLL_SHARED1,
> > +       PLL_CON0_PLL_SHARED2,
> > +       PLL_CON1_PLL_SHARED2,
> > +       PLL_CON2_PLL_SHARED2,
> > +       PLL_CON3_PLL_SHARED2,
> > +       PLL_CON4_PLL_SHARED2,
> > +       PLL_CON0_PLL_SHARED3,
> > +       PLL_CON1_PLL_SHARED3,
> > +       PLL_CON2_PLL_SHARED3,
> > +       PLL_CON3_PLL_SHARED3,
> > +       PLL_CON4_PLL_SHARED3,
> > +       PLL_CON0_PLL_SPARE,
> > +       PLL_CON1_PLL_SPARE,
> > +       PLL_CON2_PLL_SPARE,
> > +       PLL_CON3_PLL_SPARE,
> > +       PLL_CON4_PLL_SPARE,
> > +       CMU_CMU_TOP_CONTROLLER_OPTION,
> > +       CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
> > +       CMU_HCHGEN_CLKMUX_CMU_BOOST,
> > +       CMU_HCHGEN_CLKMUX_TOP_BOOST,
> > +       CMU_HCHGEN_CLKMUX,
> > +       POWER_FAIL_DETECT_PLL,
> > +       EARLY_WAKEUP_FORCED_0_ENABLE,
> > +       EARLY_WAKEUP_FORCED_1_ENABLE,
> > +       EARLY_WAKEUP_APM_CTRL,
> > +       EARLY_WAKEUP_CLUSTER0_CTRL,
> > +       EARLY_WAKEUP_DPU_CTRL,
> > +       EARLY_WAKEUP_CSIS_CTRL,
> > +       EARLY_WAKEUP_APM_DEST,
> > +       EARLY_WAKEUP_CLUSTER0_DEST,
> > +       EARLY_WAKEUP_DPU_DEST,
> > +       EARLY_WAKEUP_CSIS_DEST,
> > +       EARLY_WAKEUP_SW_TRIG_APM,
> > +       EARLY_WAKEUP_SW_TRIG_APM_SET,
> > +       EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
> > +       EARLY_WAKEUP_SW_TRIG_CLUSTER0,
> > +       EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
> > +       EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
> > +       EARLY_WAKEUP_SW_TRIG_DPU,
> > +       EARLY_WAKEUP_SW_TRIG_DPU_SET,
> > +       EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
> > +       EARLY_WAKEUP_SW_TRIG_CSIS,
> > +       EARLY_WAKEUP_SW_TRIG_CSIS_SET,
> > +       EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
> > +       CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
> > +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
> > +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
> > +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
> > +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
> > +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
> > +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
> > +       CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
> > +       CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
> > +       CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
> > +       CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
> > +       CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
> > +       CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
> > +       CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
> > +       CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
> > +       CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
> > +       CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
> > +       CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
> > +       CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
> > +       CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
> > +       CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
> > +       CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
> > +       CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
> > +       CLK_CON_MUX_MUX_CLKCMU_HPM,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
> > +       CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
> > +       CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
> > +       CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
> > +       CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
> > +       CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
> > +       CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
> > +       CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
> > +       CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
> > +       CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
> > +       CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
> > +       CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
> > +       CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
> > +       CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
> > +       CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
> > +       CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
> > +       CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
> > +       CLK_CON_MUX_MUX_CMU_CMUREF,
> > +       CLK_CON_DIV_CLKCMU_BO_BUS,
> > +       CLK_CON_DIV_CLKCMU_BUS0_BUS,
> > +       CLK_CON_DIV_CLKCMU_BUS1_BUS,
> > +       CLK_CON_DIV_CLKCMU_BUS2_BUS,
> > +       CLK_CON_DIV_CLKCMU_CIS_CLK0,
> > +       CLK_CON_DIV_CLKCMU_CIS_CLK1,
> > +       CLK_CON_DIV_CLKCMU_CIS_CLK2,
> > +       CLK_CON_DIV_CLKCMU_CIS_CLK3,
> > +       CLK_CON_DIV_CLKCMU_CIS_CLK4,
> > +       CLK_CON_DIV_CLKCMU_CIS_CLK5,
> > +       CLK_CON_DIV_CLKCMU_CIS_CLK6,
> > +       CLK_CON_DIV_CLKCMU_CIS_CLK7,
> > +       CLK_CON_DIV_CLKCMU_CORE_BUS,
> > +       CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
> > +       CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
> > +       CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
> > +       CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
> > +       CLK_CON_DIV_CLKCMU_CSIS_BUS,
> > +       CLK_CON_DIV_CLKCMU_DISP_BUS,
> > +       CLK_CON_DIV_CLKCMU_DNS_BUS,
> > +       CLK_CON_DIV_CLKCMU_DPU_BUS,
> > +       CLK_CON_DIV_CLKCMU_EH_BUS,
> > +       CLK_CON_DIV_CLKCMU_G2D_G2D,
> > +       CLK_CON_DIV_CLKCMU_G2D_MSCL,
> > +       CLK_CON_DIV_CLKCMU_G3AA_G3AA,
> > +       CLK_CON_DIV_CLKCMU_G3D_BUSD,
> > +       CLK_CON_DIV_CLKCMU_G3D_GLB,
> > +       CLK_CON_DIV_CLKCMU_G3D_SWITCH,
> > +       CLK_CON_DIV_CLKCMU_GDC_GDC0,
> > +       CLK_CON_DIV_CLKCMU_GDC_GDC1,
> > +       CLK_CON_DIV_CLKCMU_GDC_SCSC,
> > +       CLK_CON_DIV_CLKCMU_HPM,
> > +       CLK_CON_DIV_CLKCMU_HSI0_BUS,
> > +       CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
> > +       CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
> > +       CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
> > +       CLK_CON_DIV_CLKCMU_HSI1_BUS,
> > +       CLK_CON_DIV_CLKCMU_HSI1_PCIE,
> > +       CLK_CON_DIV_CLKCMU_HSI2_BUS,
> > +       CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
> > +       CLK_CON_DIV_CLKCMU_HSI2_PCIE,
> > +       CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
> > +       CLK_CON_DIV_CLKCMU_IPP_BUS,
> > +       CLK_CON_DIV_CLKCMU_ITP_BUS,
> > +       CLK_CON_DIV_CLKCMU_MCSC_ITSC,
> > +       CLK_CON_DIV_CLKCMU_MCSC_MCSC,
> > +       CLK_CON_DIV_CLKCMU_MFC_MFC,
> > +       CLK_CON_DIV_CLKCMU_MIF_BUSP,
> > +       CLK_CON_DIV_CLKCMU_MISC_BUS,
> > +       CLK_CON_DIV_CLKCMU_MISC_SSS,
> > +       CLK_CON_DIV_CLKCMU_OTP,
> > +       CLK_CON_DIV_CLKCMU_PDP_BUS,
> > +       CLK_CON_DIV_CLKCMU_PDP_VRA,
> > +       CLK_CON_DIV_CLKCMU_PERIC0_BUS,
> > +       CLK_CON_DIV_CLKCMU_PERIC0_IP,
> > +       CLK_CON_DIV_CLKCMU_PERIC1_BUS,
> > +       CLK_CON_DIV_CLKCMU_PERIC1_IP,
> > +       CLK_CON_DIV_CLKCMU_TNR_BUS,
> > +       CLK_CON_DIV_CLKCMU_TPU_BUS,
> > +       CLK_CON_DIV_CLKCMU_TPU_TPU,
> > +       CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
> > +       CLK_CON_DIV_CLKCMU_TPU_UART,
> > +       CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
> > +       CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
> > +       CLK_CON_DIV_PLL_SHARED0_DIV2,
> > +       CLK_CON_DIV_PLL_SHARED0_DIV3,
> > +       CLK_CON_DIV_PLL_SHARED0_DIV4,
> > +       CLK_CON_DIV_PLL_SHARED0_DIV5,
> > +       CLK_CON_DIV_PLL_SHARED1_DIV2,
> > +       CLK_CON_DIV_PLL_SHARED1_DIV3,
> > +       CLK_CON_DIV_PLL_SHARED1_DIV4,
> > +       CLK_CON_DIV_PLL_SHARED2_DIV2,
> > +       CLK_CON_DIV_PLL_SHARED3_DIV2,
> > +       CLK_CON_GAT_CLKCMU_BUS0_BOOST,
> > +       CLK_CON_GAT_CLKCMU_BUS1_BOOST,
> > +       CLK_CON_GAT_CLKCMU_BUS2_BOOST,
> > +       CLK_CON_GAT_CLKCMU_CORE_BOOST,
> > +       CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
> > +       CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
> > +       CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
> > +       CLK_CON_GAT_CLKCMU_MIF_BOOST,
> > +       CLK_CON_GAT_CLKCMU_MIF_SWITCH,
> > +       CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
> > +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
> > +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
> > +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
> > +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
> > +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
> > +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
> > +       CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
> > +       CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
> > +       CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
> > +       CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
> > +       CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
> > +       CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
> > +       CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
> > +       CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
> > +       CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
> > +       CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
> > +       CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
> > +       CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
> > +       CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
> > +       CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
> > +       CLK_CON_GAT_GATE_CLKCMU_HPM,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
> > +       CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
> > +       CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
> > +       CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
> > +       CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
> > +       CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
> > +       CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
> > +       CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
> > +       CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
> > +       CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
> > +       CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
> > +       CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
> > +       CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
> > +       CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
> > +       CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
> > +       DMYQCH_CON_CMU_TOP_CMUREF_QCH,
> > +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
> > +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
> > +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
> > +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
> > +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
> > +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
> > +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
> > +       DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
> > +       DMYQCH_CON_OTP_QCH,
> > +       QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
> > +       QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
> > +       QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
> > +       QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
> > +       QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
> > +       QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
> > +       QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
> > +       QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
> > +       QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
> > +       MIFMIRROR_QUEUE_CTRL_REG,
> > +       MIFMIRROR_QUEUE_ENTRY0,
> > +       MIFMIRROR_QUEUE_ENTRY1,
> > +       MIFMIRROR_QUEUE_ENTRY2,
> > +       MIFMIRROR_QUEUE_ENTRY3,
> > +       MIFMIRROR_QUEUE_ENTRY4,
> > +       MIFMIRROR_QUEUE_ENTRY5,
> > +       MIFMIRROR_QUEUE_ENTRY6,
> > +       MIFMIRROR_QUEUE_ENTRY7,
> > +       MIFMIRROR_QUEUE_BUSY,
> > +       GENERALIO_ACD_CHANNEL_0,
> > +       GENERALIO_ACD_CHANNEL_1,
> > +       GENERALIO_ACD_CHANNEL_2,
> > +       GENERALIO_ACD_CHANNEL_3,
> > +       GENERALIO_ACD_MASK,
> > +};
> > +
> > +static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
> > +       /* CMU_TOP_PURECLKCOMP */
> > +       PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> > +           PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> > +           NULL),
> > +       PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
> > +           PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
> > +           NULL),
> > +       PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
> > +           PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
> > +           NULL),
> > +       PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
> > +           PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
> > +           NULL),
> > +       PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
> > +           PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
> > +           NULL),
> > +};
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP */
> > +PNAME(mout_shared0_pll_p)      = { "oscclk", "fout_shared0_pll" };
> > +PNAME(mout_shared1_pll_p)      = { "oscclk", "fout_shared1_pll" };
> > +PNAME(mout_shared2_pll_p)      = { "oscclk", "fout_shared2_pll" };
> > +PNAME(mout_shared3_pll_p)      = { "oscclk", "fout_shared3_pll" };
> > +PNAME(mout_spare_pll_p)                = { "oscclk", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */
> > +PNAME(mout_cmu_bus0_bus_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "dout_shared2_div2", "dout_shared3_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_cmu_boost_p)    = { "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "dout_shared2_div2", "dout_shared3_div2" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */
> > +PNAME(mout_cmu_bus1_bus_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */
> > +PNAME(mout_cmu_bus2_bus_p)     = { "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div3", "dout_shared1_div3",
> > +                                   "dout_shared0_div5", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
> > +PNAME(mout_cmu_core_bus_p)     = { "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div3", "dout_shared1_div3",
> > +                                   "dout_shared0_div5", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */
> > +PNAME(mout_cmu_eh_bus_p)       = { "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div3", "dout_shared1_div3",
> > +                                   "dout_shared0_div5", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */
> > +PNAME(mout_cmu_cpucl2_switch_p)        = { "fout_shared1_pll", "dout_shared0_div2",
> > +                                   "dout_shared1_div2", "fout_shared2_pll",
> > +                                   "fout_shared3_pll", "dout_shared0_div3",
> > +                                   "dout_shared1_div3", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
> > +PNAME(mout_cmu_cpucl1_switch_p)        = { "fout_shared1_pll", "dout_shared0_div2",
> > +                                   "dout_shared1_div2", "fout_shared2_pll",
> > +                                   "fout_shared3_pll", "dout_shared0_div3",
> > +                                   "dout_shared1_div3", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
> > +PNAME(mout_cmu_cpucl0_switch_p)        = { "fout_shared1_pll", "dout_shared0_div2",
> > +                                   "dout_shared1_div2", "fout_shared2_pll",
> > +                                   "fout_shared3_pll", "dout_shared0_div3",
> > +                                   "dout_shared1_div3", "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_cpucl0_dbg_p)   = { "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "dout_shared2_div2", "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_hpm_p)          = { "oscclk", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "dout_shared2_div2" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
> > +PNAME(mout_cmu_g3d_switch_p)   = { "fout_shared2_pll", "dout_shared0_div3",
> > +                                   "fout_shared3_pll", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_g3d_busd_p)     = { "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div3", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_g3d_glb_p)      = { "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div3", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
> > +PNAME(mout_cmu_dpu_p)          = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */
> > +PNAME(mout_cmu_disp_bus_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */
> > +PNAME(mout_cmu_g2d_g2d_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_g2d_mscl_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "dout_shared2_div2", "dout_shared3_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */
> > +PNAME(mout_cmu_hsi0_usb31drd_p)        = { "oscclk", "dout_shared2_div2" };
> > +
> > +PNAME(mout_cmu_hsi0_bus_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "dout_shared2_div2", "dout_shared3_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_hsi0_dpgtc_p)   = { "oscclk", "dout_shared0_div4",
> > +                                   "dout_shared2_div2", "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_hsi0_usbdpdbg_p)        = { "oscclk", "dout_shared2_div2" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */
> > +PNAME(mout_cmu_hsi1_bus_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "dout_shared2_div2", "dout_shared3_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_hsi1_pcie_p)    = { "oscclk", "dout_shared2_div2" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */
> > +PNAME(mout_cmu_hsi2_bus_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "dout_shared2_div2", "dout_shared3_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_hsi2_pcie0_p)   = { "oscclk", "dout_shared2_div2" };
> > +
> > +PNAME(mout_cmu_hsi2_ufs_embd_p)        = { "oscclk", "dout_shared0_div4",
> > +                                   "dout_shared2_div2", "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_hsi2_mmc_card_p)        = { "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div4", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */
> > +PNAME(mout_cmu_csis_bus_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */
> > +PNAME(mout_cmu_pdp_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_pdp_vra_p)      = { "fout_shared2_pll", "dout_shared0_div3",
> > +                                   "fout_shared3_pll", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */
> > +PNAME(mout_cmu_ipp_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */
> > +PNAME(mout_cmu_g3aa_p)         = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */
> > +PNAME(mout_cmu_itp_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */
> > +PNAME(mout_cmu_dns_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */
> > +PNAME(mout_cmu_tnr_bus_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */
> > +PNAME(mout_cmu_mcsc_itsc_p)    = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_mcsc_mcsc_p)    = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */
> > +PNAME(mout_cmu_gdc_scsc_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_gdc_gdc0_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_gdc_gdc1_p)     = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */
> > +PNAME(mout_cmu_mfc_mfc_p)      = { "dout_shared0_div3", "fout_shared3_pll",
> > +                                   "dout_shared1_div3", "dout_shared0_div4",
> > +                                   "dout_shared1_div4", "dout_shared2_div2",
> > +                                   "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */
> > +
> > +PNAME(mout_cmu_mif_switch_p)   = { "fout_shared0_pll", "fout_shared1_pll",
> > +                                   "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "dout_shared0_div3",
> > +                                   "fout_shared3_pll", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */
> > +PNAME(mout_cmu_mif_busp_p)     = { "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "dout_shared0_div5", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */
> > +PNAME(mout_cmu_misc_bus_p)     = { "dout_shared0_div4", "dout_shared2_div2",
> > +                                   "dout_shared3_div2", "fout_spare_pll" };
> > +PNAME(mout_cmu_misc_sss_p)     = { "dout_shared0_div4", "dout_shared2_div2",
> > +                                   "dout_shared3_div2", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */
> > +PNAME(mout_cmu_peric0_bus_p)   = { "dout_shared0_div4", "dout_shared2_div2",
> > +                                   "dout_shared3_div2", "fout_spare_pll" };
> > +PNAME(mout_cmu_peric0_ip_p)    = { "dout_shared0_div4", "dout_shared2_div2",
> > +                                   "dout_shared3_div2", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */
> > +PNAME(mout_cmu_peric1_bus_p)   = { "dout_shared0_div4", "dout_shared2_div2",
> > +                                   "dout_shared3_div2", "fout_spare_pll" };
> > +PNAME(mout_cmu_peric1_ip_p)    = { "dout_shared0_div4", "dout_shared2_div2",
> > +                                   "dout_shared3_div2", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */
> > +PNAME(mout_cmu_tpu_tpu_p)      = { "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div3", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_tpu_tpuctl_p)   = { "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div3", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_tpu_bus_p)      = { "dout_shared0_div2", "dout_shared1_div2",
> > +                                   "fout_shared2_pll", "fout_shared3_pll",
> > +                                   "dout_shared0_div3", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "fout_spare_pll" };
> > +
> > +PNAME(mout_cmu_tpu_uart_p)     = { "dout_shared0_div4", "dout_shared2_div2",
> > +                                   "dout_shared3_div2", "fout_spare_pll" };
> > +
> > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */
> > +PNAME(mout_cmu_bo_bus_p)       = { "fout_shared2_pll", "dout_shared0_div3",
> > +                                   "fout_shared3_pll", "dout_shared1_div3",
> > +                                   "dout_shared0_div4", "dout_shared1_div4",
> > +                                   "fout_spare_pll" };
> > +
> > +/* gs101 */
>
> Maybe remove this comment.

will fix
>
> > +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> > +       /* CMU_TOP_PURECLKCOMP */
> > +       MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> > +           PLL_CON0_PLL_SHARED0, 4, 1),
> > +       MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> > +           PLL_CON0_PLL_SHARED1, 4, 1),
> > +       MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> > +           PLL_CON0_PLL_SHARED2, 4, 1),
> > +       MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> > +           PLL_CON0_PLL_SHARED3, 4, 1),
> > +       MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> > +           PLL_CON0_PLL_SPARE, 4, 1),
> > +
> > +       /* BUS0 */
> > +       MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> > +       MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> > +
> > +       /* BUS1 */
> > +       MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> > +
> > +       /* BUS2 */
> > +       MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> > +
> > +       /* CORE */
> > +       MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> > +
> > +       /* EH */
> > +       MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> > +
> > +       /* CPUCL{0,1,2,} */
> > +       MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
>
> Here and further: please stick to 80 characters per line when possible.

will fix
>
> > +           CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> > +
> > +       MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> > +
> > +       MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> > +
> > +       MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> > +           CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> > +
> > +       MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
> > +
> > +       /* G3D */
> > +       MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
> > +
> > +       MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2),
> > +
> > +       MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2),
> > +       /* DPU */
> > +       MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2),
> > +
> > +       /* DISP */
> > +       MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2),
> > +
> > +       /* G2D */
> > +       MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
> > +
> > +       MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
> > +
> > +       /* HSI0 */
> > +       MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2),
> > +
> > +       MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2),
> > +
> > +       MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
> > +
> > +       MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2),
> > +
> > +       /* HSI1 */
> > +       MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2),
> > +
> > +       MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2),
> > +       /* HSI2 */
> > +       MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2),
> > +
> > +       MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2),
> > +
> > +       MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2),
> > +
> > +       MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2),
> > +
> > +       /* CSIS */
> > +       MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
> > +
> > +       /* PDP */
> > +       MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> > +
> > +       /* PDP */
> > +       MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
> > +
> > +       /* IPP */
> > +       MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> > +
> > +       /* G3AA */
> > +       MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
> > +
> > +       /* ITP */
> > +       MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2),
> > +
> > +       /* DNS */
> > +       MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2),
> > +
> > +       /* TNR */
> > +       MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2),
> > +
> > +       /* MCSC*/
> > +       MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2),
> > +
> > +       MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2),
> > +
> > +       /* GDC */
> > +       MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2),
> > +
> > +       MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2),
> > +
> > +       MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2),
> > +
> > +       /* MFC */
> > +       MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
> > +
> > +       /* DDRPHY0/1/2/3 */
> > +       MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2),
> > +
> > +       /* MIF0/1/2/3 */
> > +       MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
> > +
> > +       /* MISC */
> > +       MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
> > +       MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
> > +
> > +       /* PERI0 */
> > +       MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> > +       MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> > +       /* PERI1 */
> > +       MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
> > +       MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
> > +
> > +       /* TPU */
> > +       MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2),
> > +
> > +       MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2),
> > +
> > +       MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2),
> > +
> > +       MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
> > +
> > +       /* BO */
> > +       MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
> > +           CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2),
> > +};
> > +
> > +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
> > +       /* CMU_TOP_PURECLKCOMP */
> > +       DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
> > +           CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> > +       DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
> > +           CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> > +       DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
> > +           CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2),
> > +       DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
> > +           CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> > +
> > +       DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
> > +           CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> > +       DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
> > +           CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> > +       DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll",
> > +           CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> > +
> > +       DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
> > +           CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> > +
> > +       DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll",
> > +           CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
> > +
> > +       /* BUS0 */
> > +       DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus",
> > +           CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
> > +       DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost",
> > +           CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
> > +
> > +       /* BUS1 */
> > +       DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
> > +           CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
> > +
> > +       /* BUS2 */
> > +       DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
> > +           CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
> > +
> > +       /* CORE */
> > +       DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
> > +           CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
> > +
> > +       /* EH */
> > +       DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
> > +           CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
> > +
> > +       /* CPUCL{0,1,2,} */
> > +       DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch",
> > +           CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
> > +
> > +       DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
> > +           CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
> > +
> > +       DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch",
> > +           CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
> > +
> > +       DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
> > +           CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
> > +
> > +       DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
> > +           CLK_CON_DIV_CLKCMU_HPM, 0, 2),
> > +
> > +       /* G3D */
> > +       DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
> > +           CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
> > +
> > +       DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
> > +           CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
> > +
> > +       DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
> > +           CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
> > +
> > +       /* DPU */
> > +       DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
> > +           CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
> > +
> > +       /* DISP */
> > +       DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
> > +           CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
> > +
> > +       /* G2D */
> > +       DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
> > +           CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
> > +
> > +       DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
> > +           CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
> > +
> > +       /* HSI0 */
> > +       DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd",
> > +           CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
> > +
> > +       DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
> > +           CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
> > +
> > +       DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
> > +           CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
> > +
> > +       /* TODO register exists but all lower bits are reserved */
> > +       DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg",
> > +           CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0),
> > +
> > +       /* HSI1 */
> > +       DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
> > +           CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
> > +
> > +       DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
> > +           CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
> > +       /* HSI2 */
> > +       DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
> > +           CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
> > +
> > +       DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
> > +           CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
> > +
> > +       DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd",
> > +           CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
> > +
> > +       DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card",
> > +           CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
> > +
> > +       /* CSIS */
> > +       DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
> > +           CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
> > +
> > +       /* PDP */
> > +       DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
> > +           CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
> > +
> > +       DIV(CLK_DOUT_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",
> > +           CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
> > +
> > +       /* IPP */
> > +       DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
> > +           CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
> > +
> > +       /* G3AA */
> > +       DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa",
> > +           CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
> > +
> > +       /* ITP */
> > +       DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
> > +           CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
> > +
> > +       /* DNS */
> > +       DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
> > +           CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
> > +
> > +       /* TNR */
> > +       DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
> > +           CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
> > +
> > +       /* MCSC*/
> > +       DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
> > +           CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
> > +
> > +       DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
> > +           CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
> > +
> > +       /* GDC */
> > +       DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
> > +           CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
> > +
> > +       DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
> > +           CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
> > +
> > +       DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
> > +           CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
> > +
> > +       /* MFC */
> > +       DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
> > +           CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
> > +
> > +       /* MIF0/1/2/3 */
> > +       DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
> > +           CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
> > +
> > +       /* MISC */
> > +       DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
> > +           CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
> > +       DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
> > +           CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
> > +
> > +       /* PERI0 */
> > +       DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
> > +           CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
> > +       DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
> > +           CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
> > +
> > +       /* PERI1 */
> > +       DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
> > +           CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
> > +       DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
> > +           CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
> > +
> > +       /* TPU */
> > +       DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
> > +           CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
> > +
> > +       DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl",
> > +           CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
> > +
> > +       DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
> > +           CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
> > +
> > +       DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
> > +           CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
> > +
> > +       /* BO */
> > +       DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
> > +           CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
> > +
>
> Empty line here is unnecessary.

will fix
>
> > +};
> > +
> > +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
> > +       /* BUS0 */
> > +       GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
> > +
> > +       /* BUS1 */
> > +       GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
> > +
> > +       /* BUS2 */
> > +       GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
> > +
> > +       /* CORE */
> > +       GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
> > +
> > +       /* EH */
> > +       GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
> > +
> > +       /* CPUCL{0,1,2,} */
> > +       GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch",
> > +            CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
> > +            CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
> > +            CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
> > +            CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
> > +            CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
> > +
> > +       /* G3D */
> > +       GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
> > +            CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
> > +            CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
> > +            CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
> > +       /* DPU */
> > +       GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
> > +       /* DISP */
> > +       GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
> > +
> > +       /* G2D */
> > +       GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
> > +            CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
> > +            CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
> > +       /* HSI0 */
> > +       GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0),
> > +       /* HSI1 */
> > +       GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
> > +       /* HSI2 */
> > +       GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
> > +       GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0),
> > +       GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card",
> > +            CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0),
> > +       /* CSIS */
> > +       GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> > +       /* PDP */
> > +       GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
> > +            CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> > +
> > +       /* IPP */
> > +       GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> > +       /* G3AA */
> > +       GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> > +            CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
> > +
> > +       /* ITP */
> > +       GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
> > +
> > +       /* DNS */
> > +       GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
> > +
> > +       /* TNR */
> > +       GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
> > +
> > +       /* MCSC*/
> > +       GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
> > +            CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
> > +            CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
> > +
> > +       /* GDC */
> > +       GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
> > +            CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
> > +            CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
> > +            CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
> > +
> > +       /* MFC */
> > +       GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
> > +            CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
> > +
> > +       /* DDRPHY0/1/2/3 */
> > +       GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
> > +            CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
> > +
> > +       /* MIF0/1/2/3 */
> > +       GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
> > +            CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost",
> > +            CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
> > +
> > +       /* MISC */
> > +       GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
> > +       GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
> > +            CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
> > +
> > +       /* PERI0 */
> > +       GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
> > +       GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
> > +            CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
> > +
> > +       /* PERI1 */
> > +       GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
> > +       GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
> > +            CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
> > +
> > +       /* TPU */
> > +       GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
> > +            CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
> > +       GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
> > +            CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
> > +       GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
> > +       GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
> > +            CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
> > +
> > +       /* BO */
> > +       GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
> > +            CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
> > +
>
> Empty line here is unnecessary.

will fix

regards,

Peter

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Krzysztof Kozlowski]

On 12/10/2023 14:06, Peter Griffin wrote:
> Hi Sam,
> 
> Thanks for the review.
> 
> On Thu, 12 Oct 2023 at 01:07, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>>
>> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
>>>
>>> CMU_TOP is the top level clock management unit which contains PLLs, muxes
>>> and gates that feed the other clock management units.
>>>
>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>> ---
>>>  drivers/clk/samsung/Kconfig     |    9 +
>>>  drivers/clk/samsung/Makefile    |    2 +
>>>  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
>>>  3 files changed, 1562 insertions(+)
>>>  create mode 100644 drivers/clk/samsung/clk-gs101.c
>>>
>>> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
>>> index 76a494e95027..14362ec9c543 100644
>>> --- a/drivers/clk/samsung/Kconfig
>>> +++ b/drivers/clk/samsung/Kconfig
>>> @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
>>>         select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
>>>         select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
>>>         select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
>>> +       select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
>>>         select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
>>>
>>>  config S3C64XX_COMMON_CLK
>>> @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
>>>           status of the certains clocks from SoC, but it could also be tied to
>>>           other devices as an input clock.
>>>
>>> +config GOOGLE_GS101_COMMON_CLK
>>> +       bool "Google gs101 clock controller support" if COMPILE_TEST
>>> +       depends on COMMON_CLK_SAMSUNG
>>> +       depends on EXYNOS_ARM64_COMMON_CLK
>>> +       help
>>> +         Support for the clock controller present on the Google gs101 SoC.
>>> +         Choose Y here only if you build for this SoC.
>>> +
>>
>> Why is that new option needed? From the look of it, it could be just a
>> part of EXYNOS_ARM64_COMMON_CLK. Like clk-exynos850 or
>> clk-exynosautov9. Is there any particular feature that makes it SoC
>> special?
> 
> No, it could also be added to EXYNOS_ARM64_COMMON_CLK. I was following
> the example set by TESLA_FSD which is another custom Exynos based chipset
> that added its own config option.
> 
> Krzysztof do you have any preference on this?

Usually there is only one image for several boards so long time ago we
stopped adding per-SoC Kconfig entries. This has its own ARCH_xxx, just
like Tesla, thus having separate Kconfig for all Google Tensor clock
drivers makes sense. Maybe it should be just called a bit differently,
e.g. GOOGLE_TENSOR_COMMON_CLK



Best regards,
Krzysztof

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Peter Griffin]

Hi Krzysztof,

On Thu, 12 Oct 2023 at 13:24, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 12/10/2023 14:06, Peter Griffin wrote:
> > Hi Sam,
> >
> > Thanks for the review.
> >
> > On Thu, 12 Oct 2023 at 01:07, Sam Protsenko <semen.protsenko@linaro.org> wrote:
> >>
> >> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >>>
> >>> CMU_TOP is the top level clock management unit which contains PLLs, muxes
> >>> and gates that feed the other clock management units.
> >>>
> >>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> >>> ---
> >>>  drivers/clk/samsung/Kconfig     |    9 +
> >>>  drivers/clk/samsung/Makefile    |    2 +
> >>>  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
> >>>  3 files changed, 1562 insertions(+)
> >>>  create mode 100644 drivers/clk/samsung/clk-gs101.c
> >>>
> >>> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> >>> index 76a494e95027..14362ec9c543 100644
> >>> --- a/drivers/clk/samsung/Kconfig
> >>> +++ b/drivers/clk/samsung/Kconfig
> >>> @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
> >>>         select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
> >>>         select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> >>>         select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> >>> +       select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
> >>>         select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> >>>
> >>>  config S3C64XX_COMMON_CLK
> >>> @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
> >>>           status of the certains clocks from SoC, but it could also be tied to
> >>>           other devices as an input clock.
> >>>
> >>> +config GOOGLE_GS101_COMMON_CLK
> >>> +       bool "Google gs101 clock controller support" if COMPILE_TEST
> >>> +       depends on COMMON_CLK_SAMSUNG
> >>> +       depends on EXYNOS_ARM64_COMMON_CLK
> >>> +       help
> >>> +         Support for the clock controller present on the Google gs101 SoC.
> >>> +         Choose Y here only if you build for this SoC.
> >>> +
> >>
> >> Why is that new option needed? From the look of it, it could be just a
> >> part of EXYNOS_ARM64_COMMON_CLK. Like clk-exynos850 or
> >> clk-exynosautov9. Is there any particular feature that makes it SoC
> >> special?
> >
> > No, it could also be added to EXYNOS_ARM64_COMMON_CLK. I was following
> > the example set by TESLA_FSD which is another custom Exynos based chipset
> > that added its own config option.
> >
> > Krzysztof do you have any preference on this?
>
> Usually there is only one image for several boards so long time ago we
> stopped adding per-SoC Kconfig entries. This has its own ARCH_xxx, just
> like Tesla, thus having separate Kconfig for all Google Tensor clock
> drivers makes sense. Maybe it should be just called a bit differently,
> e.g. GOOGLE_TENSOR_COMMON_CLK

Thanks, I will update the name in v4.

Peter.

Re: [PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data

[Peter Griffin]

Hi Krzysztof,

On Thu, 12 Oct 2023 at 07:26, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 11/10/2023 20:48, Peter Griffin wrote:
> > Add serial driver data for Google Tensor gs101 SoC.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  drivers/tty/serial/samsung_tty.c | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> > index 07fb8a9dac63..26bc52e681a4 100644
> > --- a/drivers/tty/serial/samsung_tty.c
> > +++ b/drivers/tty/serial/samsung_tty.c
> > @@ -2597,14 +2597,22 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
> >       .fifosize = { 256, 64, 64, 64 },
> >  };
> >
> > +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> > +     EXYNOS_COMMON_SERIAL_DRV_DATA(),
> > +     /* rely on samsung,uart-fifosize DT property for fifosize */
>
> It's an optional property, so you cannot rely on it.

Is it possible to make it a mandatory DT property for certain SoCs?

>
> > +     .fifosize = { 0 },

I can update this to 256, and we can add more sizes as we enable other
UARTs I suppose.

What's the purpose of having fifosize specified in DT and in *_serial_drv_data?

Thanks,

Peter

Re: [PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data

[Krzysztof Kozlowski]

On 12/10/2023 16:03, Peter Griffin wrote:
> Hi Krzysztof,
> 
> On Thu, 12 Oct 2023 at 07:26, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 11/10/2023 20:48, Peter Griffin wrote:
>>> Add serial driver data for Google Tensor gs101 SoC.
>>>
>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>> ---
>>>  drivers/tty/serial/samsung_tty.c | 13 +++++++++++++
>>>  1 file changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
>>> index 07fb8a9dac63..26bc52e681a4 100644
>>> --- a/drivers/tty/serial/samsung_tty.c
>>> +++ b/drivers/tty/serial/samsung_tty.c
>>> @@ -2597,14 +2597,22 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
>>>       .fifosize = { 256, 64, 64, 64 },
>>>  };
>>>
>>> +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
>>> +     EXYNOS_COMMON_SERIAL_DRV_DATA(),
>>> +     /* rely on samsung,uart-fifosize DT property for fifosize */
>>
>> It's an optional property, so you cannot rely on it.
> 
> Is it possible to make it a mandatory DT property for certain SoCs?

Yes.

> 
>>
>>> +     .fifosize = { 0 },
> 
> I can update this to 256, and we can add more sizes as we enable other
> UARTs I suppose.

You might also want to fix Arnd's comment, but anyway drivers must be in
match with bindings.

> 
> What's the purpose of having fifosize specified in DT and in *_serial_drv_data?

I guess safe defaults?

Best regards,
Krzysztof

Re: [PATCH v3 12/20] clk: samsung: clk-gs101: Add support for CMU_MISC clock unit

[Peter Griffin]

Hi Sam,

On Thu, 12 Oct 2023 at 01:12, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > CMU Misc clocks IPs such as Watchdog. Add support for the
> > muxes, dividers and gates in this CMU.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  drivers/clk/samsung/clk-gs101.c | 312 ++++++++++++++++++++++++++++++++
> >  1 file changed, 312 insertions(+)
> >
> > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> > index 525f95e60665..bf2bd8cd39d0 100644
> > --- a/drivers/clk/samsung/clk-gs101.c
> > +++ b/drivers/clk/samsung/clk-gs101.c
> > @@ -20,6 +20,7 @@
> >  /* NOTE: Must be equal to the last clock ID increased by one */
> >  #define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
> >  #define APM_NR_CLK                     (CLK_APM_PLL_DIV16_APM + 1)
> > +#define MISC_NR_CLK                    (CLK_GOUT_MISC_WDT_CLUSTER1 + 1)
>
> Tabs for the indentation.

Thanks for the review. Will fix in v4.

Peter

>
> >
> >  /* ---- CMU_TOP ------------------------------------------------------------- */
> >
> > @@ -1815,6 +1816,314 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
> >         .nr_clk_regs            = ARRAY_SIZE(apm_clk_regs),
> >  };
> >
> > +/* ---- CMU_MISC ------------------------------------------------------------- */
> > +/* Register Offset definitions for CMU_MISC (0x10010000) */
> > +#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER      0x0600
> > +#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER      0x0604
> > +#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER      0x0610
> > +#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER      0x0614
> > +#define MISC_CMU_MISC_CONTROLLER_OPTION                0x0800
> > +#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0   0x0810
> > +#define CLK_CON_MUX_MUX_CLK_MISC_GIC           0x1000
> > +#define CLK_CON_DIV_DIV_CLK_MISC_BUSP          0x1800
> > +#define CLK_CON_DIV_DIV_CLK_MISC_GIC           0x1804
> > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK              0x2000
> > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK           0x2004
> > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK           0x2008
> > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK            0x200c
> > +#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK    0x2010
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM              0x2014
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM               0x2018
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM               0x201c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A                    0x2020
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK               0x2024
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK                     0x2028
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK                  0x202c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK       0x2030
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK            0x2034
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK            0x2038
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK           0x203c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK          0x2040
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK       0x2044
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK            0x2048
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK                       0x204c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK              0x2050
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK              0x2054
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK               0x2058
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK                      0x205c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK                  0x2060
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK                 0x2064
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK                 0x2068
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK                      0x206c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK                    0x2070
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK                    0x2074
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK                   0x2078
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK                   0x207c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK               0x2080
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK               0x2084
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK                   0x2088
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK                   0x208c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK                  0x2090
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK                  0x2094
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK                    0x2098
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK                    0x209c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK     0x20a0
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK     0x20a4
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK      0x20a8
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK      0x20ac
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK                    0x20b0
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK                    0x20b4
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK                     0x20b8
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK                  0x20bc
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK                  0x20c0
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK                 0x20c4
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK                 0x20c8
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK             0x20cc
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK             0x20d0
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK                 0x20d4
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK                 0x20d8
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK                        0x20dc
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK                        0x20e0
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK                  0x20e4
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK                  0x20e8
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK                     0x20ec
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK                     0x20f0
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2             0x20f4
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1              0x20f8
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK               0x20fc
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK                   0x2100
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK                   0x2104
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK              0x2108
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK              0x210c
> > +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK                        0x2110
> > +#define DMYQCH_CON_PPMU_DMA_QCH                        0x3000
> > +#define DMYQCH_CON_PUF_QCH                     0x3004
> > +#define PCH_CON_LHM_AXI_D_SSS_PCH              0x300c
> > +#define PCH_CON_LHM_AXI_P_GIC_PCH              0x3010
> > +#define PCH_CON_LHM_AXI_P_MISC_PCH             0x3014
> > +#define PCH_CON_LHS_ACEL_D_MISC_PCH            0x3018
> > +#define PCH_CON_LHS_AST_IRI_GICCPU_PCH         0x301c
> > +#define PCH_CON_LHS_AXI_D_SSS_PCH              0x3020
> > +#define QCH_CON_ADM_AHB_SSS_QCH                        0x3024
> > +#define QCH_CON_DIT_QCH                                0x3028
> > +#define QCH_CON_GIC_QCH                                0x3030
> > +#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH         0x3038
> > +#define QCH_CON_LHM_AXI_D_SSS_QCH              0x303c
> > +#define QCH_CON_LHM_AXI_P_GIC_QCH              0x3040
> > +#define QCH_CON_LHM_AXI_P_MISC_QCH             0x3044
> > +#define QCH_CON_LHS_ACEL_D_MISC_QCH            0x3048
> > +#define QCH_CON_LHS_AST_IRI_GICCPU_QCH         0x304c
> > +#define QCH_CON_LHS_AXI_D_SSS_QCH              0x3050
> > +#define QCH_CON_MCT_QCH                                0x3054
> > +#define QCH_CON_MISC_CMU_MISC_QCH              0x3058
> > +#define QCH_CON_OTP_CON_BIRA_QCH               0x305c
> > +#define QCH_CON_OTP_CON_BISR_QCH               0x3060
> > +#define QCH_CON_OTP_CON_TOP_QCH                        0x3064
> > +#define QCH_CON_PDMA_QCH                       0x3068
> > +#define QCH_CON_PPMU_MISC_QCH                  0x306c
> > +#define QCH_CON_QE_DIT_QCH                     0x3070
> > +#define QCH_CON_QE_PDMA_QCH                    0x3074
> > +#define QCH_CON_QE_PPMU_DMA_QCH                        0x3078
> > +#define QCH_CON_QE_RTIC_QCH                    0x307c
> > +#define QCH_CON_QE_SPDMA_QCH                   0x3080
> > +#define QCH_CON_QE_SSS_QCH                     0x3084
> > +#define QCH_CON_RTIC_QCH                       0x3088
> > +#define QCH_CON_SPDMA_QCH                      0x308c
> > +#define QCH_CON_SSMT_DIT_QCH                   0x3090
> > +#define QCH_CON_SSMT_PDMA_QCH                  0x3094
> > +#define QCH_CON_SSMT_PPMU_DMA_QCH              0x3098
> > +#define QCH_CON_SSMT_RTIC_QCH                  0x309c
> > +#define QCH_CON_SSMT_SPDMA_QCH                 0x30a0
> > +#define QCH_CON_SSMT_SSS_QCH                   0x30a4
> > +#define QCH_CON_SSS_QCH                                0x30a8
> > +#define QCH_CON_SYSMMU_MISC_QCH                        0x30ac
> > +#define QCH_CON_SYSMMU_SSS_QCH                 0x30b0
> > +#define QCH_CON_SYSREG_MISC_QCH                        0x30b4
> > +#define QCH_CON_TMU_SUB_QCH                    0x30b8
> > +#define QCH_CON_TMU_TOP_QCH                    0x30bc
> > +#define QCH_CON_WDT_CLUSTER0_QCH               0x30c0
> > +#define QCH_CON_WDT_CLUSTER1_QCH               0x30c4
> > +#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC       0x3c00
> > +
> > +static const unsigned long misc_clk_regs[] __initconst = {
> > +       PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
> > +       PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
> > +       PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
> > +       PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
> > +       MISC_CMU_MISC_CONTROLLER_OPTION,
> > +       CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
> > +       CLK_CON_MUX_MUX_CLK_MISC_GIC,
> > +       CLK_CON_DIV_DIV_CLK_MISC_BUSP,
> > +       CLK_CON_DIV_DIV_CLK_MISC_GIC,
> > +       CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
> > +       CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
> > +       CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
> > +       CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
> > +       CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
> > +       DMYQCH_CON_PPMU_DMA_QCH,
> > +       DMYQCH_CON_PUF_QCH,
> > +       PCH_CON_LHM_AXI_D_SSS_PCH,
> > +       PCH_CON_LHM_AXI_P_GIC_PCH,
> > +       PCH_CON_LHM_AXI_P_MISC_PCH,
> > +       PCH_CON_LHS_ACEL_D_MISC_PCH,
> > +       PCH_CON_LHS_AST_IRI_GICCPU_PCH,
> > +       PCH_CON_LHS_AXI_D_SSS_PCH,
> > +       QCH_CON_ADM_AHB_SSS_QCH,
> > +       QCH_CON_DIT_QCH,
> > +       QCH_CON_GIC_QCH,
> > +       QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
> > +       QCH_CON_LHM_AXI_D_SSS_QCH,
> > +       QCH_CON_LHM_AXI_P_GIC_QCH,
> > +       QCH_CON_LHM_AXI_P_MISC_QCH,
> > +       QCH_CON_LHS_ACEL_D_MISC_QCH,
> > +       QCH_CON_LHS_AST_IRI_GICCPU_QCH,
> > +       QCH_CON_LHS_AXI_D_SSS_QCH,
> > +       QCH_CON_MCT_QCH,
> > +       QCH_CON_MISC_CMU_MISC_QCH,
> > +       QCH_CON_OTP_CON_BIRA_QCH,
> > +       QCH_CON_OTP_CON_BISR_QCH,
> > +       QCH_CON_OTP_CON_TOP_QCH,
> > +       QCH_CON_PDMA_QCH,
> > +       QCH_CON_PPMU_MISC_QCH,
> > +       QCH_CON_QE_DIT_QCH,
> > +       QCH_CON_QE_PDMA_QCH,
> > +       QCH_CON_QE_PPMU_DMA_QCH,
> > +       QCH_CON_QE_RTIC_QCH,
> > +       QCH_CON_QE_SPDMA_QCH,
> > +       QCH_CON_QE_SSS_QCH,
> > +       QCH_CON_RTIC_QCH,
> > +       QCH_CON_SPDMA_QCH,
> > +       QCH_CON_SSMT_DIT_QCH,
> > +       QCH_CON_SSMT_PDMA_QCH,
> > +       QCH_CON_SSMT_PPMU_DMA_QCH,
> > +       QCH_CON_SSMT_RTIC_QCH,
> > +       QCH_CON_SSMT_SPDMA_QCH,
> > +       QCH_CON_SSMT_SSS_QCH,
> > +       QCH_CON_SSS_QCH,
> > +       QCH_CON_SYSMMU_MISC_QCH,
> > +       QCH_CON_SYSMMU_SSS_QCH,
> > +       QCH_CON_SYSREG_MISC_QCH,
> > +       QCH_CON_TMU_SUB_QCH,
> > +       QCH_CON_TMU_TOP_QCH,
> > +       QCH_CON_WDT_CLUSTER0_QCH,
> > +       QCH_CON_WDT_CLUSTER1_QCH,
> > +       QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
> > +};
> > +
> > +/* List of parent clocks for Muxes in CMU_MISC */
> > +PNAME(mout_misc_bus_user_p)            = { "oscclk", "dout_cmu_misc_bus" };
> > +PNAME(mout_misc_sss_user_p)            = { "oscclk", "dout_cmu_misc_sss" };
> > +
> > +static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
> > +       MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
> > +           PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
> > +       MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
> > +           PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
> > +};
> > +
> > +static const struct samsung_div_clock misc_div_clks[] __initconst = {
> > +       DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
> > +           CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
> > +       DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
> > +           CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
> > +};
> > +
> > +static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
> > +       GATE(CLK_GOUT_MISC_PCLK, "gout_misc_pclk", "dout_misc_busp",
> > +            CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
> > +            21, 0, 0),
> > +
>
> No need in empty lines.
>
> > +       GATE(CLK_GOUT_MISC_SYSREG_PCLK, "gout_misc_sysreg_pclk", "dout_misc_busp",
> > +            CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
> > +            21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_MISC_WDT_CLUSTER0, "gout_misc_wdt_cluster0", "dout_misc_busp",
> > +            CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
> > +            21, 0, 0),
> > +
> > +       GATE(CLK_GOUT_MISC_WDT_CLUSTER1, "gout_misc_wdt_cluster1", "dout_misc_busp",
> > +            CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
> > +            21, 0, 0),
> > +
>
> Unnecessary empty line.
>
> > +};
> > +
> > +static const struct samsung_cmu_info misc_cmu_info __initconst = {
> > +       .mux_clks               = misc_mux_clks,
> > +       .nr_mux_clks            = ARRAY_SIZE(misc_mux_clks),
> > +       .div_clks               = misc_div_clks,
> > +       .nr_div_clks            = ARRAY_SIZE(misc_div_clks),
> > +       .gate_clks              = misc_gate_clks,
> > +       .nr_gate_clks           = ARRAY_SIZE(misc_gate_clks),
> > +       .nr_clk_ids             = MISC_NR_CLK,
> > +       .clk_regs               = misc_clk_regs,
> > +       .nr_clk_regs            = ARRAY_SIZE(misc_clk_regs),
> > +       .clk_name               = "dout_misc_bus",
> > +};
> > +
> >  /* ---- platform_driver ----------------------------------------------------- */
> >
> >  static int __init gs101_cmu_probe(struct platform_device *pdev)
> > @@ -1832,6 +2141,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> >         {
> >                 .compatible = "google,gs101-cmu-apm",
> >                 .data = &apm_cmu_info,
> > +       }, {
> > +               .compatible = "google,gs101-cmu-misc",
> > +               .data = &misc_cmu_info,
> >         }, {
> >         },
> >  };
> > --
> > 2.42.0.655.g421f12c284-goog
> >

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[William McVicker]

Hi Krzysztof,

On 10/12/2023, Krzysztof Kozlowski wrote:
> On 12/10/2023 12:45, Peter Griffin wrote:
> > Hi Krzysztof,
> > 
> > On Thu, 12 Oct 2023 at 10:36, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 12/10/2023 10:56, Peter Griffin wrote:
> >>> Hi Krzysztof,
> >>>
> >>> On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 11/10/2023 23:48, William McVicker wrote:
> >>>>> On 10/11/2023, Peter Griffin wrote:
> >>>>>> Provide dt-schema documentation for Google gs101 SoC clock controller.
> >>>>>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> >>>>>>
> >>>>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> >>>>>
> >>>>> Tested-by: Will McVicker <willmcvicker@google.com>
> >>>>
> >>>> And how do you perform testing of a binding?
> >>>
> >>> I guess if William is using my script to build and flash the kernel it actually
> >>> runs the DTC checks as part of the build process.
> >>>
> >>> See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44
> >>
> >> So it is a build test? We do not consider building as a test procedure,
> >> otherwise I should add my and robots tested-by to many other patches.
> > 
> > Ok so I should only add the Tested-by on the .c patches?
> 
> In my opinion, if someone performs only build testing, it is not a
> testing. You cannot test the bindings other way than build testing, at
> least I do not know such way. Of course other code like C or DTS affects
> hardware so it can be tested.

What additional testing beside building and booting do you prefer at this
stage? I put my Tested-by for this patch because it includes the google,gs101.h
header which is used by the DT and clock controller driver during boot. Maybe
I should have been more clear on what I tested in each patch instead of only
mentioning how I tested in the cover letter?

Sorry for the confusion.

Thanks,
Will

> 
> > 
> >> Shall I consider other Tested-by tags here also as build-tested only?
> > 
> > No. William indicated here
> > https://lore.kernel.org/linux-arm-kernel/ZScZu-QB2LmB4CSM@google.com/T/#mbd96a26b725d6c85eb4193de8cd70ff277bc728e
> > that he booted it on his Oriole device.
> 
> 
> OK, I was just a bit confused.
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

[Stephen Boyd]

Quoting Peter Griffin (2023-10-11 11:48:05)
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..f74494594b3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,125 @@
[...]
> +properties:
> +  compatible:
> +    enum:
> +      - google,gs101-cmu-top
> +      - google,gs101-cmu-apm
> +      - google,gs101-cmu-misc
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2

Can you remove clock-names from the binding and simply use the index of
the clocks property? That means less string comparisons in the kernel.
I'm not sure if other samsung clk drivers are doing this though so maybe
clock-names is preferred for historical reasons.

Re: [PATCH v3 18/20] arm64: dts: google: Add initial Oriole/pixel 6 board support

[Stephen Boyd]

Quoting Peter Griffin (2023-10-11 11:48:21)
> diff --git a/arch/arm64/boot/dts/google/gs101-oriole.dts b/arch/arm64/boot/dts/google/gs101-oriole.dts
> new file mode 100644
> index 000000000000..3bebca989d34
> --- /dev/null
> +++ b/arch/arm64/boot/dts/google/gs101-oriole.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Oriole Device Tree
> + *
> + * Copyright 2021-2023 Google,LLC
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "gs101-pinctrl.h"
> +#include "gs101.dtsi"
> +
> +/ {
> +       model = "Oriole";
> +       compatible = "google,gs101-oriole", "google,gs101";
> +
> +       chosen {
> +               bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0";
> +       };
> +
> +       gpio-keys {
> +               compatible = "gpio-keys";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&key_voldown &key_volup &key_power>;

When a phandle starts an array presumably the next element after it is
some cell or "argument" for that phandle. In this case, &key_voldown
doesn't have any cells (there isn't a #pinctrl-cells property) so we
typically write it like this

		pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>;

so that the reader doesn't think the phandles are related. In the DTB
nothing is different from how you have it in this patch. This is a super
nitpick!

Re: [PATCH v3 09/20] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}

[Chanwoo Choi]

On 23. 10. 12. 03:48, Peter Griffin wrote:
> These plls are found in the Tensor gs101 SoC found in the Pixel 6.
> 
> pll0516x: Integer PLL with high frequency
> pll0517x: Integer PLL with middle frequency
> pll0518x: Integer PLL with low frequency
> 
> PLL0516x
> FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
> 
> PLL0517x and PLL0518x
> FOUT = (MDIV * FIN)/PDIV*2^SDIV)
> 
> The PLLs are similar enough to pll_0822x that the same code can handle
> both. The main difference is the change in the fout formula for the
> high frequency 0516 pll.
> 
> Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
> 
> When defining the PLL the "con" parameter should be set to CON3
> register, like this
> 
> PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
>     PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
>     NULL),
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/clk/samsung/clk-pll.c | 9 ++++++++-
>  drivers/clk/samsung/clk-pll.h | 3 +++
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 74934c6182ce..4ef9fea2a425 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
>  	pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
>  	sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
>  
> -	fvco *= mdiv;
> +	if (pll->type == pll_0516x)
> +		fvco = fvco * 2 * mdiv;
> +	else
> +		fvco *= mdiv;
> +
>  	do_div(fvco, (pdiv << sdiv));
>  
>  	return (unsigned long)fvco;
> @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>  	case pll_1417x:
>  	case pll_0818x:
>  	case pll_0822x:
> +	case pll_0516x:
> +	case pll_0517x:
> +	case pll_0518x:
>  		pll->enable_offs = PLL0822X_ENABLE_SHIFT;
>  		pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
>  		if (!pll->rate_table)
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 0725d485c6ee..ffd3d52c0dec 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -38,6 +38,9 @@ enum samsung_pll_type {
>  	pll_0822x,
>  	pll_0831x,
>  	pll_142xx,
> +	pll_0516x,
> +	pll_0517x,
> +	pll_0518x,
>  };
>  
>  #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \

I replied it with ack before. Again, reply it with ack.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi

Re: [PATCH v3 09/20] clk: samsung: clk-pll: Add support for pll_{0516,0517,518}

[Peter Griffin]

On Tue, 17 Oct 2023 at 09:52, Chanwoo Choi <chanwoo@kernel.org> wrote:
>
> On 23. 10. 12. 03:48, Peter Griffin wrote:
> > These plls are found in the Tensor gs101 SoC found in the Pixel 6.
> >
> > pll0516x: Integer PLL with high frequency
> > pll0517x: Integer PLL with middle frequency
> > pll0518x: Integer PLL with low frequency
> >
> > PLL0516x
> > FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
> >
> > PLL0517x and PLL0518x
> > FOUT = (MDIV * FIN)/PDIV*2^SDIV)
> >
> > The PLLs are similar enough to pll_0822x that the same code can handle
> > both. The main difference is the change in the fout formula for the
> > high frequency 0516 pll.
> >
> > Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
> > MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
> >
> > When defining the PLL the "con" parameter should be set to CON3
> > register, like this
> >
> > PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> >     PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
> >     NULL),
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  drivers/clk/samsung/clk-pll.c | 9 ++++++++-
> >  drivers/clk/samsung/clk-pll.h | 3 +++
> >  2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> > index 74934c6182ce..4ef9fea2a425 100644
> > --- a/drivers/clk/samsung/clk-pll.c
> > +++ b/drivers/clk/samsung/clk-pll.c
> > @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
> >       pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
> >       sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
> >
> > -     fvco *= mdiv;
> > +     if (pll->type == pll_0516x)
> > +             fvco = fvco * 2 * mdiv;
> > +     else
> > +             fvco *= mdiv;
> > +
> >       do_div(fvco, (pdiv << sdiv));
> >
> >       return (unsigned long)fvco;
> > @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> >       case pll_1417x:
> >       case pll_0818x:
> >       case pll_0822x:
> > +     case pll_0516x:
> > +     case pll_0517x:
> > +     case pll_0518x:
> >               pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> >               pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
> >               if (!pll->rate_table)
> > diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> > index 0725d485c6ee..ffd3d52c0dec 100644
> > --- a/drivers/clk/samsung/clk-pll.h
> > +++ b/drivers/clk/samsung/clk-pll.h
> > @@ -38,6 +38,9 @@ enum samsung_pll_type {
> >       pll_0822x,
> >       pll_0831x,
> >       pll_142xx,
> > +     pll_0516x,
> > +     pll_0517x,
> > +     pll_0518x,
> >  };
> >
> >  #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
>
> I replied it with ack before. Again, reply it with ack.
>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

Thanks Chanwoo. I will add that in v4

Re: [PATCH v3 15/20] watchdog: s3c2410_wdt: Add support for Google tensor SoCs

[Peter Griffin]

Hi Guenter,

Thanks for your review.

On Wed, 11 Oct 2023 at 22:20, Guenter Roeck <linux@roeck-us.net> wrote:
>
> On Wed, Oct 11, 2023 at 07:48:18PM +0100, Peter Griffin wrote:
> > This patch adds the compatibles and drvdata for the Google
> > gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> > to Exynos850 it has two watchdog instances, one for each cluster
> > and has some control bits in PMU registers.
> >
> > The watchdog IP found in gs101 SoCs also supports a few
> > additional bits/features in the WTCON register which we add
> > support for and an additional register detailed below.
> >
> > dbgack-mask - Enables masking WDT interrupt and reset request
> > according to asserted DBGACK input
> >
> > windowed-mode - Enabled Windowed watchdog mode
> >
> > Windowed watchdog mode also has an additional register WTMINCNT.
> > If windowed watchdog is enabled and you reload WTCNT when the
> > value is greater than WTMINCNT, it prompts interrupt or reset
> > request as if the watchdog time has expired.
>
> Sorry, I don't understand what the code is doing here.

No need to be sorry, I appreciate the review feedback and questions :)

>
> It looks like it enables window mode unconditionally (?). If so,
> what is the impact ? Does it mean that any code requesting multiple
> keepalives in a row on the affected hardware will now cause an
> immediate reset ? If so, what is the rationale ?

Essentially yes, it stops continual keepalives being issued as a
keepalive is only considered valid at certain times in the windowed
cycle.

By way of example, if the watchdog interval is 30s and wtmincnt is set
to *half* of wtcnt, then we would have a "closed window" for the first
15s whereby issuing a keepalive will reset the system, and a "open
window" for the second half of the interval where issuing a keepalive
would reset wtcnt (and be considered a valid service of the watchdog).

The rationale is to stop the watchdog being re-armed "too much" and
it should enable detection of abnormally early as well as abnormally
late servicing of the watchdog.

> Alternatively, if it enables window mode and configures it such
> that WTMINCNT is always equal or larger than WTCNT, what is the
> point of enabling window mode in the first place ?

I looked again, and you are indeed correct that the code currently is
essentially turning windowed mode into a no-op. This appears to be a
bug in the downstream driver as well. Setting WTMINCNT to half of
WTCNT results in a 50% closed, 50% open window, and works on the
hardware as I would expect. I guess this is a good example of why
upstreaming your code, and public code review results in better quality
drivers.

Thanks,

Peter

Re: [PATCH v3 15/20] watchdog: s3c2410_wdt: Add support for Google tensor SoCs

[Peter Griffin]

Hi Sam,

Thanks for your review.

On Thu, 12 Oct 2023 at 03:32, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > This patch adds the compatibles and drvdata for the Google
> > gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> > to Exynos850 it has two watchdog instances, one for each cluster
> > and has some control bits in PMU registers.
> >
> > The watchdog IP found in gs101 SoCs also supports a few
> > additional bits/features in the WTCON register which we add
> > support for and an additional register detailed below.
> >
> > dbgack-mask - Enables masking WDT interrupt and reset request
> > according to asserted DBGACK input
> >
> > windowed-mode - Enabled Windowed watchdog mode
> >
> > Windowed watchdog mode also has an additional register WTMINCNT.
> > If windowed watchdog is enabled and you reload WTCNT when the
> > value is greater than WTMINCNT, it prompts interrupt or reset
> > request as if the watchdog time has expired.
> >
>
> A couple of thoughts in addition to what Guenter said.
>
> From the description it looks like this patch should be split into 3 patches:
>   1. Add "dbgack" feature
>   2. Add "windowed mode" feature
>   3. Enable gsX01 support

Sure I can split it up like that in v4 if that is preferable. The most important
part atm is SoC support, as the watchdog is left enabled by the bootloader
so without this, the system resets after ~ 1 minute.

> Also, it's not clear if those features are mandatory for gsX01 wdt to
> function properly, or optional?

The features aren't mandatory, the watchdog works fine with windowed
mode disabled and the "dback" feature just affects the watchdog reset
behaviour when an external debug agent is used.

> From the code it looks like both
> dbgack and windowed mode will only affect gsX01 variants (because of
> quirk flags), but maybe the commit message should be more clear about
> that.

Sure I will be more verbose in the commit messages when I split it out into
separate patches

>
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  drivers/watchdog/s3c2410_wdt.c | 127 ++++++++++++++++++++++++++++++---
> >  1 file changed, 116 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> > index 0b4bd883ff28..36c170047180 100644
> > --- a/drivers/watchdog/s3c2410_wdt.c
> > +++ b/drivers/watchdog/s3c2410_wdt.c
> > @@ -31,12 +31,14 @@
> >  #define S3C2410_WTDAT          0x04
> >  #define S3C2410_WTCNT          0x08
> >  #define S3C2410_WTCLRINT       0x0c
> > -
> > +#define S3C2410_WTMINCNT       0x10
> >  #define S3C2410_WTCNT_MAXCNT   0xffff
> >
> > -#define S3C2410_WTCON_RSTEN    (1 << 0)
> > -#define S3C2410_WTCON_INTEN    (1 << 2)
> > -#define S3C2410_WTCON_ENABLE   (1 << 5)
> > +#define S3C2410_WTCON_RSTEN            (1 << 0)
> > +#define S3C2410_WTCON_INTEN            (1 << 2)
> > +#define S3C2410_WTCON_ENABLE           (1 << 5)
> > +#define S3C2410_WTCON_DBGACK_MASK      (1 << 16)
> > +#define S3C2410_WTCON_WINDOWED_WD      (1 << 20)
>
> Maybe use BIT() macro here?

I didn't use the BIT macro for my changes, as the rest of the driver
isn't currently using the BIT macro.

>
> >
> >  #define S3C2410_WTCON_DIV16    (0 << 3)
> >  #define S3C2410_WTCON_DIV32    (1 << 3)
> > @@ -51,6 +53,7 @@
> >
> >  #define S3C2410_WATCHDOG_ATBOOT                (0)
> >  #define S3C2410_WATCHDOG_DEFAULT_TIME  (15)
> > +#define S3C2410_WINDOW_MULTIPLIER      2
> >
> >  #define EXYNOS5_RST_STAT_REG_OFFSET            0x0404
> >  #define EXYNOS5_WDT_DISABLE_REG_OFFSET         0x0408
> > @@ -67,6 +70,13 @@
> >  #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT     25
> >  #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT     24
> >
> > +#define GS_CLUSTER0_NONCPU_OUT                 0x1220
> > +#define GS_CLUSTER1_NONCPU_OUT                 0x1420
> > +#define GS_CLUSTER0_NONCPU_INT_EN              0x1244
> > +#define GS_CLUSTER1_NONCPU_INT_EN              0x1444
> > +#define GS_CLUSTER2_NONCPU_INT_EN              0x1644
> > +#define GS_RST_STAT_REG_OFFSET                 0x3B44
>
> Please move those to the section above, where similar registers are
> described for other SoCs.

Will fix.

>
> > +
> >  /**
> >   * DOC: Quirk flags for different Samsung watchdog IP-cores
> >   *
> > @@ -106,6 +116,8 @@
> >  #define QUIRK_HAS_PMU_RST_STAT                 (1 << 2)
> >  #define QUIRK_HAS_PMU_AUTO_DISABLE             (1 << 3)
> >  #define QUIRK_HAS_PMU_CNT_EN                   (1 << 4)
> > +#define QUIRK_HAS_DBGACK_BIT                   (1 << 5)
> > +#define QUIRK_HAS_WTMINCNT_REG                 (1 << 6)
>
> Please also document those two quirks in the kernel-doc comment above.
> Btw, the comment correctness can be checked like this:
>
>     $ scripts/kernel-doc -v -none drivers/watchdog/s3c2410_wdt.c
>
> or without "-none" option to see how the comment is parsed by kernel-doc.

Will do, and thanks for the kernel-doc hint!

>
> >
> >  /* These quirks require that we have a PMU register map */
> >  #define QUIRKS_HAVE_PMUREG \
> > @@ -263,6 +275,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
> >                   QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
> >  };
> >
> > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> > +       .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> > +       .mask_bit = 2,
> > +       .mask_reset_inv = true,
> > +       .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > +       .rst_stat_bit = 0,
> > +       .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> > +       .cnt_en_bit = 8,
> > +       .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
>
> Here and further: please stick to 80 characters per line when possible.

Will fix

>
> > +                 QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> > +       .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> > +       .mask_bit = 2,
> > +       .mask_reset_inv = true,
> > +       .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > +       .rst_stat_bit = 1,
> > +       .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> > +       .cnt_en_bit = 7,
> > +       .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > +                 QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
> > +       .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> > +       .mask_bit = 2,
> > +       .mask_reset_inv = true,
> > +       .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > +       .rst_stat_bit = 0,
> > +       .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> > +       .cnt_en_bit = 8,
> > +       .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > +                 QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
> > +       .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> > +       .mask_bit = 2,
> > +       .mask_reset_inv = true,
> > +       .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > +       .rst_stat_bit = 1,
> > +       .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> > +       .cnt_en_bit = 7,
> > +       .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> > +                 QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> > +};
> > +
> >  static const struct of_device_id s3c2410_wdt_match[] = {
> >         { .compatible = "samsung,s3c2410-wdt",
> >           .data = &drv_data_s3c2410 },
> > @@ -278,6 +338,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> >           .data = &drv_data_exynos850_cl0 },
> >         { .compatible = "samsung,exynosautov9-wdt",
> >           .data = &drv_data_exynosautov9_cl0 },
> > +       { .compatible = "google,gs101-wdt",
> > +         .data = &drv_data_gs101_cl0 },
> > +       { .compatible = "google,gs201-wdt",
> > +         .data = &drv_data_gs201_cl0 },
> >         {},
> >  };
> >  MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> > @@ -375,6 +439,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
> >         return 0;
> >  }
> >
> > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
> > +{
> > +       unsigned long wtcon;
> > +
> > +       if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
> > +               return;
> > +
> > +       wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> > +       if (mask)
> > +               wtcon |= S3C2410_WTCON_DBGACK_MASK;
> > +       else
> > +               wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
> > +       writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> > +}
> > +
> >  static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
> >  {
> >         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> > @@ -410,7 +489,7 @@ static int s3c2410wdt_stop(struct watchdog_device *wdd)
> >
> >  static int s3c2410wdt_start(struct watchdog_device *wdd)
> >  {
> > -       unsigned long wtcon;
> > +       unsigned long wtcon, wtmincnt;
> >         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> >         unsigned long flags;
> >
> > @@ -432,6 +511,12 @@ static int s3c2410wdt_start(struct watchdog_device *wdd)
> >         dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
> >                 wdt->count, wtcon);
> >
> > +       if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) {
> > +               wtcon |= S3C2410_WTCON_WINDOWED_WD;
> > +               wtmincnt = wdt->count * S3C2410_WINDOW_MULTIPLIER;
> > +               writel(wtmincnt, wdt->reg_base + S3C2410_WTMINCNT);
> > +       }
> > +
> >         writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
> >         writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
> >         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> > @@ -447,7 +532,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
> >         unsigned long freq = s3c2410wdt_get_freq(wdt);
> >         unsigned int count;
> >         unsigned int divisor = 1;
> > -       unsigned long wtcon;
> > +       unsigned long wtcon, wtmincnt;
> >
> >         if (timeout < 1)
> >                 return -EINVAL;
> > @@ -478,6 +563,11 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
> >         count = DIV_ROUND_UP(count, divisor);
> >         wdt->count = count;
> >
> > +       if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG) {
> > +               wtmincnt = count * S3C2410_WINDOW_MULTIPLIER;
> > +               writel(wtmincnt, wdt->reg_base + S3C2410_WTMINCNT);
> > +       }
> > +
> >         /* update the pre-scaler */
> >         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> >         wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
> > @@ -496,14 +586,20 @@ static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
> >  {
> >         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> >         void __iomem *wdt_base = wdt->reg_base;
> > +       unsigned long wtcon;
> >
> >         /* disable watchdog, to be safe  */
> >         writel(0, wdt_base + S3C2410_WTCON);
> >
> >         /* put initial values into count and data */
> > +       if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> > +               writel(0x100, wdt_base + S3C2410_WTMINCNT);
> >         writel(0x80, wdt_base + S3C2410_WTCNT);
> >         writel(0x80, wdt_base + S3C2410_WTDAT);
> >
> > +       if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> > +               wtcon |= S3C2410_WTCON_WINDOWED_WD;
> > +
> >         /* set the watchdog to go and reset... */
> >         writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
> >                 S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
> > @@ -585,9 +681,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> >         }
> >
> >  #ifdef CONFIG_OF
> > -       /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> > +       /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
>
> Please keep 80 characters per line.

Will fix

regards,

Peter
>
> >         if (variant == &drv_data_exynos850_cl0 ||
> > -           variant == &drv_data_exynosautov9_cl0) {
> > +           variant == &drv_data_exynosautov9_cl0 ||
> > +           variant == &drv_data_gs101_cl0 ||
> > +           variant == &drv_data_gs201_cl0) {
> >                 u32 index;
> >                 int err;
> >
> > @@ -600,9 +698,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> >                 case 0:
> >                         break;
> >                 case 1:
> > -                       variant = (variant == &drv_data_exynos850_cl0) ?
> > -                               &drv_data_exynos850_cl1 :
> > -                               &drv_data_exynosautov9_cl1;
> > +                       if (variant == &drv_data_exynos850_cl0)
> > +                               variant = &drv_data_exynos850_cl1;
> > +                       else if (variant == &drv_data_exynosautov9_cl0)
> > +                               variant = &drv_data_exynosautov9_cl1;
> > +                       else if (variant == &drv_data_gs101_cl0)
> > +                               variant = &drv_data_gs101_cl1;
> > +                       else if (variant == &drv_data_gs201_cl0)
> > +                               variant = &drv_data_gs201_cl1;
> >                         break;
> >                 default:
> >                         return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> > @@ -700,6 +803,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> >         wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
> >         wdt->wdt_device.parent = dev;
> >
> > +       s3c2410wdt_mask_dbgack(wdt, true);
> > +
> >         /*
> >          * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
> >          * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
> > --
> > 2.42.0.655.g421f12c284-goog
> >

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Chanwoo Choi]

Hi Peter,

On 23. 10. 12. 03:48, Peter Griffin wrote:
> CMU_TOP is the top level clock management unit which contains PLLs, muxes
> and gates that feed the other clock management units.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/clk/samsung/Kconfig     |    9 +
>  drivers/clk/samsung/Makefile    |    2 +
>  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
>  3 files changed, 1562 insertions(+)
>  create mode 100644 drivers/clk/samsung/clk-gs101.c
> 
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..14362ec9c543 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
>  	select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
>  	select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
>  	select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> +	select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
>  	select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
>  
>  config S3C64XX_COMMON_CLK
> @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
>  	  status of the certains clocks from SoC, but it could also be tied to
>  	  other devices as an input clock.
>  
> +config GOOGLE_GS101_COMMON_CLK
> +	bool "Google gs101 clock controller support" if COMPILE_TEST
> +	depends on COMMON_CLK_SAMSUNG
> +	depends on EXYNOS_ARM64_COMMON_CLK
> +	help
> +	  Support for the clock controller present on the Google gs101 SoC.
> +	  Choose Y here only if you build for this SoC.
> +

(snip)

> +
> +/* gs101 */
> +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> +	/* CMU_TOP_PURECLKCOMP */
> +	MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> +	    PLL_CON0_PLL_SHARED0, 4, 1),
> +	MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> +	    PLL_CON0_PLL_SHARED1, 4, 1),
> +	MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> +	    PLL_CON0_PLL_SHARED2, 4, 1),
> +	MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> +	    PLL_CON0_PLL_SHARED3, 4, 1),
> +	MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> +	    PLL_CON0_PLL_SPARE, 4, 1),
> +
> +	/* BUS0 */
> +	MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> +	MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,

In order to keep the consistent naming style,
I think that need to change from 'mout_cmu_boost' to 'mout_cmu_cmu_boost'.

> +	    CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> +
> +	/* BUS1 */
> +	MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> +
> +	/* BUS2 */
> +	MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> +
> +	/* CORE */
> +	MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> +
> +	/* EH */
> +	MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),

'mout_cmu_core_bus' and 'mout_cmu_eh_bus' uses the same register/shift/width information. 
I think it should be modified by changing the regiter or changing the shift/width information.

> +
> +	/* CPUCL{0,1,2,} */
> +	MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> +
> +	MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> +
> +	MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> +
> +	MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> +	    CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> +
> +	MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
>

(snip)

> +	/* PDP */
> +	MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> +
> +	/* PDP */
> +	MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
> +
> +	/* IPP */
> +	MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> +
> +	/* G3AA */
> +	MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> +	    CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),

I think that need to change the mux name and mux parent name
because other mux name use the twice word according to the register name
even if use the same work such as 'mout_cmu_g2d_g2d', 'mout_cmu_mcsc_mcsc' and 'mout_cmu_mfc_mfc'.
- mout_cmu_g3aa -> mout_cmu_g3aa_g3aa
- mout_cmu_g3aa_p -> mount_cmu_g3aa_g3aa_p

(snip)

> +	/* CSIS */
> +	GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> +	/* PDP */
> +	GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
> +	GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
> +	     CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> +
> +	/* IPP */
> +	GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> +	     CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> +	/* G3AA */
> +	GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> +	     CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),

ditto.
gout_cmu_g3aa -> gout_cmu_g3aa_g3aa
mout_cmu_g3aa -> mout_cmu_g3aa_g3aa

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi

Re: [PATCH v3 11/20] clk: samsung: clk-gs101: add CMU_APM support

[Chanwoo Choi]

Hi,

On 23. 10. 12. 03:48, Peter Griffin wrote:
> This patch adds all the registers for the APM clock controller unit.
> 
> We register all the muxes and dividers, but only a few of the
> gates currently for PMU and GPIO.
> 
> One clock is marked CLK_IS_CRITICAL because the system
> hangs if this clock is disabled.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/clk/samsung/clk-gs101.c | 301 ++++++++++++++++++++++++++++++++
>  1 file changed, 301 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index e2c62754b1eb..525f95e60665 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -19,6 +19,7 @@
>  

Looks good to me.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi

Re: [PATCH v3 12/20] clk: samsung: clk-gs101: Add support for CMU_MISC clock unit

[Chanwoo Choi]

On 23. 10. 12. 03:48, Peter Griffin wrote:
> CMU Misc clocks IPs such as Watchdog. Add support for the
> muxes, dividers and gates in this CMU.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  drivers/clk/samsung/clk-gs101.c | 312 ++++++++++++++++++++++++++++++++
>  1 file changed, 312 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 525f95e60665..bf2bd8cd39d0 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -20,6 +20,7 @@
>  /* NOTE: Must be equal to the last clock ID increased by one */
>  #define TOP_NR_CLK                     (CLK_GOUT_CMU_BOOST + 1)
>  #define APM_NR_CLK                     (CLK_APM_PLL_DIV16_APM + 1)
> +#define MISC_NR_CLK                    (CLK_GOUT_MISC_WDT_CLUSTER1 + 1)
>  
>  /* ---- CMU_TOP ------------------------------------------------------------- */
>  
> @@ -1815,6 +1816,314 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
>  	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
>  };
>  
> +/* ---- CMU_MISC ------------------------------------------------------------- */
> +/* Register Offset definitions for CMU_MISC (0x10010000) */
> +#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER	0x0600
> +#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER	0x0604
> +#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER	0x0610
> +#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER	0x0614
> +#define MISC_CMU_MISC_CONTROLLER_OPTION		0x0800
> +#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0	0x0810
> +#define CLK_CON_MUX_MUX_CLK_MISC_GIC		0x1000
> +#define CLK_CON_DIV_DIV_CLK_MISC_BUSP		0x1800
> +#define CLK_CON_DIV_DIV_CLK_MISC_GIC		0x1804
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK		0x2000
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK		0x2004
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK		0x2008
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK		0x200c
> +#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK	0x2010
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM		0x2014
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM		0x2018
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM		0x201c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A			0x2020
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK		0x2024
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK			0x2028
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK			0x202c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK	0x2030
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK		0x2034
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK		0x2038
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK		0x203c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK		0x2040
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK	0x2044
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK		0x2048
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK			0x204c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK		0x2050
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK		0x2054
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK		0x2058
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK			0x205c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK			0x2060
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK			0x2064
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK			0x2068
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK			0x206c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK			0x2070
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK			0x2074
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK			0x2078
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK			0x207c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK		0x2080
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK		0x2084
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK			0x2088
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK			0x208c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK			0x2090
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK			0x2094
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK			0x2098
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK			0x209c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK	0x20a0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK	0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK	0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK	0x20ac
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK			0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK			0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK			0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK			0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK			0x20c0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK			0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK			0x20c8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK		0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK		0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK			0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK			0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK			0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK			0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK			0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK			0x20e8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK			0x20ec
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK			0x20f0
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2		0x20f4
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1		0x20f8
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK		0x20fc
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK			0x2100
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK			0x2104
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK		0x2108
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK		0x210c
> +#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK			0x2110
> +#define DMYQCH_CON_PPMU_DMA_QCH			0x3000
> +#define DMYQCH_CON_PUF_QCH			0x3004
> +#define PCH_CON_LHM_AXI_D_SSS_PCH		0x300c
> +#define PCH_CON_LHM_AXI_P_GIC_PCH		0x3010
> +#define PCH_CON_LHM_AXI_P_MISC_PCH		0x3014
> +#define PCH_CON_LHS_ACEL_D_MISC_PCH		0x3018
> +#define PCH_CON_LHS_AST_IRI_GICCPU_PCH		0x301c
> +#define PCH_CON_LHS_AXI_D_SSS_PCH		0x3020
> +#define QCH_CON_ADM_AHB_SSS_QCH			0x3024
> +#define QCH_CON_DIT_QCH				0x3028
> +#define QCH_CON_GIC_QCH				0x3030
> +#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH		0x3038
> +#define QCH_CON_LHM_AXI_D_SSS_QCH		0x303c
> +#define QCH_CON_LHM_AXI_P_GIC_QCH		0x3040
> +#define QCH_CON_LHM_AXI_P_MISC_QCH		0x3044
> +#define QCH_CON_LHS_ACEL_D_MISC_QCH		0x3048
> +#define QCH_CON_LHS_AST_IRI_GICCPU_QCH		0x304c
> +#define QCH_CON_LHS_AXI_D_SSS_QCH		0x3050
> +#define QCH_CON_MCT_QCH				0x3054
> +#define QCH_CON_MISC_CMU_MISC_QCH		0x3058
> +#define QCH_CON_OTP_CON_BIRA_QCH		0x305c
> +#define QCH_CON_OTP_CON_BISR_QCH		0x3060
> +#define QCH_CON_OTP_CON_TOP_QCH			0x3064
> +#define QCH_CON_PDMA_QCH			0x3068
> +#define QCH_CON_PPMU_MISC_QCH			0x306c
> +#define QCH_CON_QE_DIT_QCH			0x3070
> +#define QCH_CON_QE_PDMA_QCH			0x3074
> +#define QCH_CON_QE_PPMU_DMA_QCH			0x3078
> +#define QCH_CON_QE_RTIC_QCH			0x307c
> +#define QCH_CON_QE_SPDMA_QCH			0x3080
> +#define QCH_CON_QE_SSS_QCH			0x3084
> +#define QCH_CON_RTIC_QCH			0x3088
> +#define QCH_CON_SPDMA_QCH			0x308c
> +#define QCH_CON_SSMT_DIT_QCH			0x3090
> +#define QCH_CON_SSMT_PDMA_QCH			0x3094
> +#define QCH_CON_SSMT_PPMU_DMA_QCH		0x3098
> +#define QCH_CON_SSMT_RTIC_QCH			0x309c
> +#define QCH_CON_SSMT_SPDMA_QCH			0x30a0
> +#define QCH_CON_SSMT_SSS_QCH			0x30a4
> +#define QCH_CON_SSS_QCH				0x30a8
> +#define QCH_CON_SYSMMU_MISC_QCH			0x30ac
> +#define QCH_CON_SYSMMU_SSS_QCH			0x30b0
> +#define QCH_CON_SYSREG_MISC_QCH			0x30b4
> +#define QCH_CON_TMU_SUB_QCH			0x30b8
> +#define QCH_CON_TMU_TOP_QCH			0x30bc
> +#define QCH_CON_WDT_CLUSTER0_QCH		0x30c0
> +#define QCH_CON_WDT_CLUSTER1_QCH		0x30c4
> +#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC	0x3c00
> +
> +static const unsigned long misc_clk_regs[] __initconst = {
> +	PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
> +	PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
> +	PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
> +	PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
> +	MISC_CMU_MISC_CONTROLLER_OPTION,
> +	CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
> +	CLK_CON_MUX_MUX_CLK_MISC_GIC,
> +	CLK_CON_DIV_DIV_CLK_MISC_BUSP,
> +	CLK_CON_DIV_DIV_CLK_MISC_GIC,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
> +	CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
> +	CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
> +	DMYQCH_CON_PPMU_DMA_QCH,
> +	DMYQCH_CON_PUF_QCH,
> +	PCH_CON_LHM_AXI_D_SSS_PCH,
> +	PCH_CON_LHM_AXI_P_GIC_PCH,
> +	PCH_CON_LHM_AXI_P_MISC_PCH,
> +	PCH_CON_LHS_ACEL_D_MISC_PCH,
> +	PCH_CON_LHS_AST_IRI_GICCPU_PCH,
> +	PCH_CON_LHS_AXI_D_SSS_PCH,
> +	QCH_CON_ADM_AHB_SSS_QCH,
> +	QCH_CON_DIT_QCH,
> +	QCH_CON_GIC_QCH,
> +	QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
> +	QCH_CON_LHM_AXI_D_SSS_QCH,
> +	QCH_CON_LHM_AXI_P_GIC_QCH,
> +	QCH_CON_LHM_AXI_P_MISC_QCH,
> +	QCH_CON_LHS_ACEL_D_MISC_QCH,
> +	QCH_CON_LHS_AST_IRI_GICCPU_QCH,
> +	QCH_CON_LHS_AXI_D_SSS_QCH,
> +	QCH_CON_MCT_QCH,
> +	QCH_CON_MISC_CMU_MISC_QCH,
> +	QCH_CON_OTP_CON_BIRA_QCH,
> +	QCH_CON_OTP_CON_BISR_QCH,
> +	QCH_CON_OTP_CON_TOP_QCH,
> +	QCH_CON_PDMA_QCH,
> +	QCH_CON_PPMU_MISC_QCH,
> +	QCH_CON_QE_DIT_QCH,
> +	QCH_CON_QE_PDMA_QCH,
> +	QCH_CON_QE_PPMU_DMA_QCH,
> +	QCH_CON_QE_RTIC_QCH,
> +	QCH_CON_QE_SPDMA_QCH,
> +	QCH_CON_QE_SSS_QCH,
> +	QCH_CON_RTIC_QCH,
> +	QCH_CON_SPDMA_QCH,
> +	QCH_CON_SSMT_DIT_QCH,
> +	QCH_CON_SSMT_PDMA_QCH,
> +	QCH_CON_SSMT_PPMU_DMA_QCH,
> +	QCH_CON_SSMT_RTIC_QCH,
> +	QCH_CON_SSMT_SPDMA_QCH,
> +	QCH_CON_SSMT_SSS_QCH,
> +	QCH_CON_SSS_QCH,
> +	QCH_CON_SYSMMU_MISC_QCH,
> +	QCH_CON_SYSMMU_SSS_QCH,
> +	QCH_CON_SYSREG_MISC_QCH,
> +	QCH_CON_TMU_SUB_QCH,
> +	QCH_CON_TMU_TOP_QCH,
> +	QCH_CON_WDT_CLUSTER0_QCH,
> +	QCH_CON_WDT_CLUSTER1_QCH,
> +	QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_MISC */
> +PNAME(mout_misc_bus_user_p)		= { "oscclk", "dout_cmu_misc_bus" };
> +PNAME(mout_misc_sss_user_p)		= { "oscclk", "dout_cmu_misc_sss" };
> +
> +static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
> +	MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
> +	    PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
> +	MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
> +	    PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
> +};
> +
> +static const struct samsung_div_clock misc_div_clks[] __initconst = {
> +	DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
> +	    CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
> +	DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
> +	    CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
> +};
> +
> +static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
> +	GATE(CLK_GOUT_MISC_PCLK, "gout_misc_pclk", "dout_misc_busp",
> +	     CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +	GATE(CLK_GOUT_MISC_SYSREG_PCLK, "gout_misc_sysreg_pclk", "dout_misc_busp",
> +	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +	GATE(CLK_GOUT_MISC_WDT_CLUSTER0, "gout_misc_wdt_cluster0", "dout_misc_busp",
> +	     CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +
> +	GATE(CLK_GOUT_MISC_WDT_CLUSTER1, "gout_misc_wdt_cluster1", "dout_misc_busp",
> +	     CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
> +	     21, 0, 0),
> +

Remove unneeded blank line.

> +};
> +
> +static const struct samsung_cmu_info misc_cmu_info __initconst = {
> +	.mux_clks		= misc_mux_clks,
> +	.nr_mux_clks		= ARRAY_SIZE(misc_mux_clks),
> +	.div_clks		= misc_div_clks,
> +	.nr_div_clks		= ARRAY_SIZE(misc_div_clks),
> +	.gate_clks		= misc_gate_clks,
> +	.nr_gate_clks		= ARRAY_SIZE(misc_gate_clks),
> +	.nr_clk_ids		= MISC_NR_CLK,
> +	.clk_regs		= misc_clk_regs,
> +	.nr_clk_regs		= ARRAY_SIZE(misc_clk_regs),
> +	.clk_name		= "dout_misc_bus",
> +};
> +
>  /* ---- platform_driver ----------------------------------------------------- */
>  
>  static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -1832,6 +2141,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
>  	{
>  		.compatible = "google,gs101-cmu-apm",
>  		.data = &apm_cmu_info,
> +	}, {
> +		.compatible = "google,gs101-cmu-misc",
> +		.data = &misc_cmu_info,
>  	}, {
>  	},
>  };


Excpet for the blank line, it looks good to me.

If you fix the patch according to my comment, feel free to add my ack.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi

Re: [PATCH v3 03/20] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101

[Peter Griffin]

Hi Rob,

On Mon, 16 Oct 2023 at 14:36, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, Oct 11, 2023 at 07:48:06PM +0100, Peter Griffin wrote:
> > GS101 has three different SYSREG controllers, add dedicated
> > compatibles for them to the documentation.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  .../bindings/soc/samsung/samsung,exynos-sysreg.yaml         | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > index 163e912e9cad..dbd12a97faad 100644
> > --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> > @@ -30,6 +30,12 @@ properties:
> >                - samsung,exynos5433-fsys-sysreg
> >            - const: samsung,exynos5433-sysreg
> >            - const: syscon
> > +      - items:
> > +          - enum:
> > +              - google,gs101-peric0-sysreg
> > +              - google,gs101-peric1-sysreg
> > +              - google,gs101-apm-sysreg
>
> Alphabetical order.

Will fix

Peter

Re: [PATCH v3 13/20] pinctrl: samsung: Add filter selection support for alive banks

[Peter Griffin]

Hi Sam,

Thanks for your review feedback. See my answers inline below.

On Wed, 11 Oct 2023 at 23:47, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > Newer Exynos SoCs have a filter selection register on alive bank pins.
> > This allows the selection of a digital or delay filter for each pin. If
> > the filter selection register is not available then the default filter
> > (digital) is applied.
> >
>
> I wonder if that solves any particular issue. For Exynos850 I decided
> against adding this feature because I failed to find any benefits of
> it. Didn't even come up with the way to test it. Is it really needed
> for this SoC functioning? In case you have some more details on why
> it's needed and how it can be tested, please add that info to the
> commit message as well.

I can certainly add some more information to the commit message.

The filter determines to what extent the signal fluctuations received
through the pad on the GPIO are considered glitches. The downstream
kernel used by Pixel 6 phones in production set this filter. If you want to
test on e850 then I would issue

echo mem > /sys/power/state

And then try to wake the device using some eint gpio. The upstream
kernel gs101/Oriole isn't functional enough currently to test suspend
resume. The logic makes sense though that whilst suspended you
don't want the digital filter enabled, as it is using a clock.

Given this filter is about detecting glitches and signal fluctuations it
looks like the sort of thing that may not deterministically fail but
could lead to spurious wakeups, which is obviously not good for a
battery based device. Additionally setting this filter is what is
recommended by the SoC manufacturer, so it seems wise to set it.

>
> > On suspend we apply the analog filter to all pins in the bank, and on
> > resume the digital filter is reapplied to all pins in the bank.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
>
> Heads up: I noticed some merge warnings when applying this patch onto
> the most recent linux-next, like so:
>
> 8<---------------------------------------------------------------------->8
>     Applying: pinctrl: samsung: Add filter selection support for alive banks
>     Using index info to reconstruct a base tree...
>     M    drivers/pinctrl/samsung/pinctrl-exynos.c
>     M    drivers/pinctrl/samsung/pinctrl-exynos.h
>     M    drivers/pinctrl/samsung/pinctrl-samsung.c
>     M    drivers/pinctrl/samsung/pinctrl-samsung.h
>     Falling back to patching base and 3-way merge...
>     Auto-merging drivers/pinctrl/samsung/pinctrl-samsung.h
>     Auto-merging drivers/pinctrl/samsung/pinctrl-samsung.c
>     Auto-merging drivers/pinctrl/samsung/pinctrl-exynos.h
>     Auto-merging drivers/pinctrl/samsung/pinctrl-exynos.c
> 8<---------------------------------------------------------------------->8
>
> It was still applied, but maybe if you are going to send v4 try to
> rebase your series on top of linux-next first.
>
> Below are pretty minor comments for the code.
>
> >  drivers/pinctrl/samsung/pinctrl-exynos.c  | 82 ++++++++++++++++++++++-
> >  drivers/pinctrl/samsung/pinctrl-exynos.h  |  7 ++
> >  drivers/pinctrl/samsung/pinctrl-samsung.c |  2 +
> >  drivers/pinctrl/samsung/pinctrl-samsung.h | 23 +++++++
> >  4 files changed, 113 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> > index a8212fc126bf..800831aa8357 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> > @@ -269,6 +269,68 @@ struct exynos_eint_gpio_save {
> >         u32 eint_mask;
> >  };
> >
> > +static void exynos_eint_flt_config(struct samsung_pinctrl_drv_data *d,
> > +                                  struct samsung_pin_bank *bank, int filter)
> > +{
> > +       unsigned int flt_reg, flt_con = 0;
> > +       unsigned int val, shift;
> > +       int i;
> > +       int loop_cnt;
> > +
> > +       /*
> > +        * This function sets the desired filter (digital or delay) to
> > +        * every pin in the bank. Note the filter selection bitfield is
> > +        * only found on alive banks. The FLTCON register has the
> > +        * following layout
> > +        *
> > +        * BitfieldName[PinNum][Bit:Bit]
> > +        *
> > +        * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
> > +        * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
> > +        * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
> > +        * FLT_EN[0][7]  FLT_SEL[0][6]  FLT_WIDTH[0][5:0]
> > +        */
>
> Maybe move this comment above this function? Or split it in two parts:
> function doc, and 'flt_con' variable doc.

Ok will move/split it

>
> > +
> > +       flt_con |= EXYNOS9_FLTCON_EN;
> > +
> > +       if (filter)
>
> Different values are passed as a 'filter' param to this function. But
> here it's only used as a boolean value. Something doesn't feel right.

That was done to aid readability at the callee sites

>
> > +               flt_con |= EXYNOS9_FLTCON_SEL_DIGITAL;
> > +
> > +       flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset;
> > +
> > +       if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN)
> > +               /*
> > +                * if nr_pins > 4, we should set FLTCON0 register fully.
> > +                * (pin0 ~ 3). So loop 4 times in case of FLTCON0.
> > +                */
>
> Maybe move this comment above 'if' block? And start with capital
> letter, for consistency with other multi-line comments.

will fix

>
> > +               loop_cnt = EXYNOS9_FLTCON_NR_PIN;
> > +       else
> > +               loop_cnt = bank->nr_pins;
> > +
> > +       val = readl(d->virt_base + flt_reg);
> > +
>
> Maybe remove this empty line to make RMW block the whole?

will do
>
> > +       for (i = 0; i < loop_cnt; i++) {
> > +               shift = i * EXYNOS9_FLTCON_LEN;
> > +               val &= ~(EXYNOS9_FLTCON_MASK << shift);
> > +               val |= (flt_con << shift);
> > +       }
> > +
>
> Ditto.
>
> > +       writel(val, d->virt_base + flt_reg);
> > +
> > +       /* loop for FLTCON1 pin 4 ~ 7 */
>
> Start with a capital letter for consistency.

will fix

>
> > +       if (bank->nr_pins > EXYNOS9_FLTCON_NR_PIN) {
> > +               val = readl(d->virt_base + flt_reg + 0x4);
> > +               loop_cnt = (bank->nr_pins - EXYNOS9_FLTCON_NR_PIN);
> > +
> > +               for (i = 0; i < loop_cnt; i++) {
> > +                       shift = i * EXYNOS9_FLTCON_LEN;
> > +                       val &= ~(EXYNOS9_FLTCON_MASK << shift);
> > +                       val |= (flt_con << shift);
> > +               }
>
> Code duplication, but it's minor.
>
> > +               writel(val, d->virt_base + flt_reg + 0x4);
> > +       }
> > +}
> > +
> >  /*
> >   * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
> >   * @d: driver data of samsung pinctrl driver.
> > @@ -321,6 +383,9 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
> >                         goto err_domains;
> >                 }
> >
> > +               /* Set Delay Analog Filter */
> > +               if (bank->fltcon_type != FLT_DEFAULT)
> > +                       exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DELAY);
> >         }
> >
> >         return 0;
> > @@ -555,6 +620,10 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
> >                 if (bank->eint_type != EINT_TYPE_WKUP)
> >                         continue;
> >
> > +               /* Set Digital Filter */
> > +               if (bank->fltcon_type != FLT_DEFAULT)
> > +                       exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DIGITAL);
>
> Please stick to 80 characters per line when possible.

will fix
>
> > +
> >                 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
> >                                               GFP_KERNEL);
> >                 if (!bank->irq_chip) {
> > @@ -658,6 +727,7 @@ static void exynos_pinctrl_suspend_bank(
> >  void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> >  {
> >         struct samsung_pin_bank *bank = drvdata->pin_banks;
> > +       struct samsung_pinctrl_drv_data *d = bank->drvdata;
> >         struct exynos_irq_chip *irq_chip = NULL;
> >         int i;
> >
> > @@ -665,6 +735,9 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> >                 if (bank->eint_type == EINT_TYPE_GPIO)
> >                         exynos_pinctrl_suspend_bank(drvdata, bank);
> >                 else if (bank->eint_type == EINT_TYPE_WKUP) {
> > +                       /* Setting Delay (Analog) Filter */
> > +                       if (bank->fltcon_type != FLT_DEFAULT)
> > +                               exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DELAY);
>
> Please stick to 80 characters per line when possible.

will fix
>
> >                         if (!irq_chip) {
> >                                 irq_chip = bank->irq_chip;
> >                                 irq_chip->set_eint_wakeup_mask(drvdata,
> > @@ -707,11 +780,18 @@ static void exynos_pinctrl_resume_bank(
> >  void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
> >  {
> >         struct samsung_pin_bank *bank = drvdata->pin_banks;
> > +       struct samsung_pinctrl_drv_data *d = bank->drvdata;
> >         int i;
> >
> >         for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
> > -               if (bank->eint_type == EINT_TYPE_GPIO)
> > +               if (bank->eint_type == EINT_TYPE_GPIO) {
> >                         exynos_pinctrl_resume_bank(drvdata, bank);
> > +               } else if (bank->eint_type == EINT_TYPE_WKUP ||
> > +                       bank->eint_type == EINT_TYPE_WKUP_MUX) {
>
> Indent it to be under the open bracket on the previous line.

will fix
>
> > +                       /* Set Digital Filter */
> > +                       if (bank->fltcon_type != FLT_DEFAULT)
> > +                               exynos_eint_flt_config(d, bank, EXYNOS9_FLTCON_SEL_DIGITAL);
>
> Please stick to 80 characters per line when possible.

will fix
>
> > +               }
> >  }
> >
> >  static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> > index 7bd6d82c9f36..63b2426ad5d6 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> > @@ -50,6 +50,13 @@
> >
> >  #define EXYNOS_EINT_MAX_PER_BANK       8
> >  #define EXYNOS_EINT_NR_WKUP_EINT
> > +/* EINT filter configuration */
> > +#define EXYNOS9_FLTCON_EN              BIT(7)
> > +#define EXYNOS9_FLTCON_SEL_DIGITAL     BIT(6)
> > +#define EXYNOS9_FLTCON_SEL_DELAY       0
> > +#define EXYNOS9_FLTCON_MASK            0xff
> > +#define EXYNOS9_FLTCON_LEN             8
> > +#define EXYNOS9_FLTCON_NR_PIN          4
> >
>
> I guess we discussed using EXYNOS9 prefix during the review of
> Exynos850 initial submission, and decided against it. But in case of
> this SoC (which is obviously Exynos, but is called Google), I'm not
> even sure which name would be appropriate. I mean, if it's ok to use
> EXYNOS9 prefix, then maybe I should go ahead and rename existing
> EXYNOS850 definitions to EXYNOS9 too, as it belongs to the same
> platform family, to avoid any confusion.

If Exynos850 also has this filter selection functionality, and we want to
share the same macro names between gs101 and exynos850 then I
think EXYNOS9_ prefix makes sense. That is what they are called in
the downstream kernel IIRC

>
> Krzysztof, what's your take on this?
>
> >  #define EXYNOS_PIN_BANK_EINTN(pins, reg, id)           \
> >         {                                               \
> > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> > index e54847040b4a..449f8109d8b5 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> > @@ -1104,6 +1104,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
> >                 bank->eint_func = bdata->eint_func;
> >                 bank->eint_type = bdata->eint_type;
> >                 bank->eint_mask = bdata->eint_mask;
> > +               bank->fltcon_type = bdata->fltcon_type;
> > +               bank->fltcon_offset = bdata->fltcon_offset;
> >                 bank->eint_offset = bdata->eint_offset;
> >                 bank->name = bdata->name;
> >
> > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> > index 9af93e3d8d9f..de2ca8e8b378 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> > @@ -82,6 +82,21 @@ enum eint_type {
> >         EINT_TYPE_WKUP_MUX,
> >  };
> >
> > +/**
> > + * enum fltcon_type - filter selection
> > + * @FLT_DEFAULT: filter not selectable, default digital filter
> > + * @FLT_SELECT: filter selectable (digital or delay)
> > + *
> > + * Some banks on some SoCs (gs101 and possibly others) have a selectable
> > + * filter on alive banks of 'delay/analog' or 'digital'. If the filter
> > + * selection is not available then the default filter is used (digital).
> > + */
> > +
>
> Maybe remove this empty line?

Will fix

regards,

Peter

>
> > +enum fltcon_type {
> > +       FLT_DEFAULT,
> > +       FLT_SELECTABLE,
> > +};
> > +
> >  /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
> >  #define PIN_NAME_LENGTH        10
> >
> > @@ -122,6 +137,8 @@ struct samsung_pin_bank_type {
> >   * @eint_type: type of the external interrupt supported by the bank.
> >   * @eint_mask: bit mask of pins which support EINT function.
> >   * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
> > + * @fltcon_type: whether the filter (delay/digital) is selectable
> > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
> >   * @name: name to be prefixed for each pin in this pin bank.
> >   */
> >  struct samsung_pin_bank_data {
> > @@ -133,6 +150,8 @@ struct samsung_pin_bank_data {
> >         enum eint_type  eint_type;
> >         u32             eint_mask;
> >         u32             eint_offset;
> > +       enum fltcon_type fltcon_type;
> > +       u32             fltcon_offset;
> >         const char      *name;
> >  };
> >
> > @@ -147,6 +166,8 @@ struct samsung_pin_bank_data {
> >   * @eint_type: type of the external interrupt supported by the bank.
> >   * @eint_mask: bit mask of pins which support EINT function.
> >   * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
> > + * @fltcon_type: whether the filter (delay/digital) is selectable
> > + * @fltcon_offset: SoC-specific EINT filter control register offset of bank.
> >   * @name: name to be prefixed for each pin in this pin bank.
> >   * @pin_base: starting pin number of the bank.
> >   * @soc_priv: per-bank private data for SoC-specific code.
> > @@ -169,6 +190,8 @@ struct samsung_pin_bank {
> >         enum eint_type  eint_type;
> >         u32             eint_mask;
> >         u32             eint_offset;
> > +       enum fltcon_type fltcon_type;
> > +       u32             fltcon_offset;
> >         const char      *name;
> >
> >         u32             pin_base;
> > --
> > 2.42.0.655.g421f12c284-goog
> >

Re: [PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data

[Peter Griffin]

Hi Arnd,

On Thu, 12 Oct 2023 at 07:07, Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Wed, Oct 11, 2023, at 20:48, Peter Griffin wrote:
> > Add serial driver data for Google Tensor gs101 SoC.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>

Thanks!

>
> While the patch is now correct, I would point out a few
> improvements we could make on top:
>
> > +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> > +     EXYNOS_COMMON_SERIAL_DRV_DATA(),
> > +     /* rely on samsung,uart-fifosize DT property for fifosize */
> > +     .fifosize = { 0 },
> > +};
> > +
> >  #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
> >  #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
> >  #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
> > +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
>
> Since this is now actually correct for any Exynos variant that
> has the FIFO size listed in the DT, we could use a variable/macro
> name that leads itself to being used by future chips.

I've updated this to exynos_fifoszdt_serial_drv_data and
EXYNOS_FIFOSZDT_SERIAL_DRV_DATA in v4 and added a
comment that it is common struct for platforms that specify
uart,fifosize in DT.

I've also updated the YAML to make this a required property for
google,gs101-uart.

>
> There is also the question of whether we want to address the
> ordering bug for the other SoC types. The way I understand it,
> the .fifosize array logic is wrong because it relies on having
> a particular alias for each of the ports to match the entry in
> the array.
> For the exynosautov9, this would be trivially fixed
> by using the same data as gs101 (since it already lists the
> correct size in DT), but for the other ones we'd need a different
> logic.
>

It seems samsung,exynosautov9-uart is in the yaml bindings and
exynosautov9.dtsi but never actually made it into the driver. But
it could be added to the driver and made to use the common
exynos_fifoszdt_serial_drv_data mentioned above.

I think any new platform should specify this in DT as many of these
UARTs on newer Exynos are actually universal serial IPs which can
be UART, I2C or SPI which is board dependent. So having the fifosize
in the driver, based on a SoC compatible and relying on probe order
and DT aliases seems very prone to error.

regards,

Peter.

> > @@ -2688,6 +2696,9 @@ static const struct platform_device_id
> > s3c24xx_serial_driver_ids[] = {
> >       }, {
> >               .name           = "artpec8-uart",
> >               .driver_data    = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
> > +     }, {
> > +             .name           = "gs101-uart",
> > +             .driver_data    = (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
> >       },
> >       { },
> >  };
>
> I just noticed that the platform_device_id array is currently
> only used for mach-crag6410, since everything else uses DT
> based probing. s3c64xx is scheduled for removal in early 2024
> (though no patch has been sent), and we can probably just
> remove all the atags/platform_device based code when that happens.
>
>       Arnd

Re: [PATCH v3 06/20] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible

[Peter Griffin]

Hi Rob,

Thanks for your review.

On Mon, 16 Oct 2023 at 14:41, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, Oct 11, 2023 at 07:48:09PM +0100, Peter Griffin wrote:
> > Add the "google,gs101-pinctrl" compatible to the dt-schema bindings
> > documentation.
> >
> > Add maxItems of 50 for the interrupts property as gs101 can have
> > multiple irqs.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  .../bindings/pinctrl/samsung,pinctrl.yaml     | 22 ++++++++++++++++++-
> >  1 file changed, 21 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> > index 26614621774a..6dc648490668 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> > +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> > @@ -35,6 +35,7 @@ properties:
> >
> >    compatible:
> >      enum:
> > +      - google,gs101-pinctrl
> >        - samsung,s3c2412-pinctrl
> >        - samsung,s3c2416-pinctrl
> >        - samsung,s3c2440-pinctrl
> > @@ -58,7 +59,8 @@ properties:
> >    interrupts:
> >      description:
> >        Required for GPIO banks supporting external GPIO interrupts.
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 50
> >
> >    power-domains:
> >      maxItems: 1
> > @@ -134,6 +136,24 @@ allOf:
> >            minItems: 1
> >            maxItems: 1
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: google,gs101-pinctrl
> > +    then:
> > +      properties:
> > +        interrupts:
> > +          description:
> > +            Required for external wakeup interrupts. List all external
>
> Is it external GPIO interrupts or wakeup interrupts?

These are external wakeup interrupts.

Looking again I believe this can be dropped entirely as re-reading
samsung,pinctrl-gpio-bank.yaml we are already defining the
external wake-up interrupts on each bank in gs101-pinctrl.dtsi.

>
> > +            wakeup interrupts supported by this bank.
> > +          minItems: 1
> > +          maxItems: 50
>
> For a given SoC, I don't see how this is variable? If it is variable,
> how do you know which entry is what?

It isn't variable.

Peter.

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Peter Griffin]

Hi Chanwoo,

Thanks for your review!

On Wed, 18 Oct 2023 at 17:51, Chanwoo Choi <chanwoo@kernel.org> wrote:
>
> Hi Peter,
>
> On 23. 10. 12. 03:48, Peter Griffin wrote:
> > CMU_TOP is the top level clock management unit which contains PLLs, muxes
> > and gates that feed the other clock management units.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  drivers/clk/samsung/Kconfig     |    9 +
> >  drivers/clk/samsung/Makefile    |    2 +
> >  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
> >  3 files changed, 1562 insertions(+)
> >  create mode 100644 drivers/clk/samsung/clk-gs101.c
> >
> > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> > index 76a494e95027..14362ec9c543 100644
> > --- a/drivers/clk/samsung/Kconfig
> > +++ b/drivers/clk/samsung/Kconfig
> > @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
> >       select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
> >       select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> >       select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> > +     select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
> >       select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> >
> >  config S3C64XX_COMMON_CLK
> > @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
> >         status of the certains clocks from SoC, but it could also be tied to
> >         other devices as an input clock.
> >
> > +config GOOGLE_GS101_COMMON_CLK
> > +     bool "Google gs101 clock controller support" if COMPILE_TEST
> > +     depends on COMMON_CLK_SAMSUNG
> > +     depends on EXYNOS_ARM64_COMMON_CLK
> > +     help
> > +       Support for the clock controller present on the Google gs101 SoC.
> > +       Choose Y here only if you build for this SoC.
> > +
>
> (snip)
>
> > +
> > +/* gs101 */
> > +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> > +     /* CMU_TOP_PURECLKCOMP */
> > +     MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> > +         PLL_CON0_PLL_SHARED0, 4, 1),
> > +     MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> > +         PLL_CON0_PLL_SHARED1, 4, 1),
> > +     MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> > +         PLL_CON0_PLL_SHARED2, 4, 1),
> > +     MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> > +         PLL_CON0_PLL_SHARED3, 4, 1),
> > +     MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> > +         PLL_CON0_PLL_SPARE, 4, 1),
> > +
> > +     /* BUS0 */
> > +     MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> > +     MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
>
> In order to keep the consistent naming style,
> I think that need to change from 'mout_cmu_boost' to 'mout_cmu_cmu_boost'.

Yes, that's a good point, and a good spot! Will fix it in v4.

>
> > +         CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> > +
> > +     /* BUS1 */
> > +     MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> > +
> > +     /* BUS2 */
> > +     MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> > +
> > +     /* CORE */
> > +     MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> > +
> > +     /* EH */
> > +     MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
>
> 'mout_cmu_core_bus' and 'mout_cmu_eh_bus' uses the same register/shift/width information.
> I think it should be modified by changing the regiter or changing the shift/width information.

It should be using the CLK_CON_MUX_MUX_CLKCMU_EH_BUS register.
Will fix it in v4.

>
> > +
> > +     /* CPUCL{0,1,2,} */
> > +     MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> > +
> > +     MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> > +
> > +     MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> > +
> > +     MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> > +         CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> > +
> > +     MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
> >
>
> (snip)
>
> > +     /* PDP */
> > +     MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> > +
> > +     /* PDP */
> > +     MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
> > +
> > +     /* IPP */
> > +     MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> > +
> > +     /* G3AA */
> > +     MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> > +         CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
>
> I think that need to change the mux name and mux parent name
> because other mux name use the twice word according to the register name
> even if use the same work such as 'mout_cmu_g2d_g2d', 'mout_cmu_mcsc_mcsc' and 'mout_cmu_mfc_mfc'.
> - mout_cmu_g3aa -> mout_cmu_g3aa_g3aa
> - mout_cmu_g3aa_p -> mount_cmu_g3aa_g3aa_p

Will fix in v4

>
> (snip)
>
> > +     /* CSIS */
> > +     GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> > +          CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> > +     /* PDP */
> > +     GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> > +          CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> > +
> > +     GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
> > +          CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> > +
> > +     /* IPP */
> > +     GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> > +          CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> > +     /* G3AA */
> > +     GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> > +          CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
>
> ditto.
> gout_cmu_g3aa -> gout_cmu_g3aa_g3aa
> mout_cmu_g3aa -> mout_cmu_g3aa_g3aa

Will fix in V4

regards,

Peter.

Re: [PATCH v3 14/20] pinctrl: samsung: Add gs101 SoC pinctrl configuration

[Peter Griffin]

Hi Sam,

On Thu, 12 Oct 2023 at 07:00, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > Add support for the pin-controller found on the gs101 SoC used in
> > Pixel 6 phones.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 163 ++++++++++++++++++
> >  drivers/pinctrl/samsung/pinctrl-exynos.c      |   2 +
> >  drivers/pinctrl/samsung/pinctrl-exynos.h      |  34 ++++
> >  drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
> >  drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
> >  5 files changed, 202 insertions(+)
> >
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > index cb965cf93705..db47001d1b35 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
> >         .ctrl           = fsd_pin_ctrl,
> >         .num_ctrl       = ARRAY_SIZE(fsd_pin_ctrl),
> >  };
> > +
> > +/*
> > + * bank type for non-alive type
> > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> > + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> > + */
> > +static struct samsung_pin_bank_type gs101_bank_type_off  = {
> > +       .fld_width = { 4, 1, 4, 4, 2, 4, },
> > +       .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> > +};
> > +
> > +/*
> > + * bank type for alive type
> > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> > + */
> > +static const struct samsung_pin_bank_type gs101_bank_type_alive = {
> > +       .fld_width = { 4, 1, 4, 4, },
> > +       .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (ALIVE) */
> > +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
>
> Here and further: please keep 80 characters per line when possible.

Will fix.

>
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> > +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (GSACORE) */
> > +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (GSACTRL) */
> > +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> > +       EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (PERIC0) */
> > +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (PERIC1) */
> > +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (HSI1) */
> > +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> > +};
> > +
> > +/* pin banks of gs101 pin-controller (HSI2) */
> > +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> > +       EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> > +};
> > +
> > +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> > +       {
> > +               /* pin banks of gs101 pin-controller (ALIVE) */
> > +               .pin_banks      = gs101_pin_alive,
> > +               .nr_banks       = ARRAY_SIZE(gs101_pin_alive),
> > +               .eint_gpio_init = exynos_eint_gpio_init,
> > +               .eint_wkup_init = exynos_eint_wkup_init,
>
> Is it ok to have both .eint_gpio_init and .eint_wkup_init set here and
> further? I remember doing something like that for Exynos850 before,
> only to realize further if was a mistake. Please check commit
> 96f79935015c ("pinctrl: samsung: Remove EINT handler for Exynos850
> ALIVE and CMGP gpios"). Maybe it's ok in your case.

Thanks for the hint :) You're correct eint_gpio_init is not required on alive,
far_alive, gsacore and gsactrl banks. Will update in v4.

>
> > +               .suspend        = exynos_pinctrl_suspend,
> > +               .resume         = exynos_pinctrl_resume,
>
> Did you manage to actually test those suspend/resume callbacks
> somehow? If so, can you please share the procedure? I guess I had some
> Power Domains and clock related problems on Exynos850 when I tried
> that before, so just curious.

You can test the callbacks using
echo mem > /sys/power/state

Thanks,

Peter.




>
> > +       }, {
> > +               /* pin banks of gs101 pin-controller (FAR_ALIVE) */
> > +               .pin_banks      = gs101_pin_far_alive,
> > +               .nr_banks       = ARRAY_SIZE(gs101_pin_far_alive),
> > +               .eint_gpio_init = exynos_eint_gpio_init,
> > +               .eint_wkup_init = exynos_eint_wkup_init,
> > +               .suspend        = exynos_pinctrl_suspend,
> > +               .resume         = exynos_pinctrl_resume,
> > +       }, {
> > +               /* pin banks of gs101 pin-controller (GSACORE) */
> > +               .pin_banks      = gs101_pin_gsacore,
> > +               .nr_banks       = ARRAY_SIZE(gs101_pin_gsacore),
> > +               .eint_gpio_init = exynos_eint_gpio_init,
> > +       }, {
> > +               /* pin banks of gs101 pin-controller (GSACTRL) */
> > +               .pin_banks      = gs101_pin_gsactrl,
> > +               .nr_banks       = ARRAY_SIZE(gs101_pin_gsactrl),
> > +               .eint_gpio_init = exynos_eint_gpio_init,
> > +       }, {
> > +               /* pin banks of gs101 pin-controller (PERIC0) */
> > +               .pin_banks      = gs101_pin_peric0,
> > +               .nr_banks       = ARRAY_SIZE(gs101_pin_peric0),
> > +               .eint_gpio_init = exynos_eint_gpio_init,
> > +               .suspend        = exynos_pinctrl_suspend,
> > +               .resume         = exynos_pinctrl_resume,
> > +       }, {
> > +               /* pin banks of gs101 pin-controller (PERIC1) */
> > +               .pin_banks      = gs101_pin_peric1,
> > +               .nr_banks       = ARRAY_SIZE(gs101_pin_peric1),
> > +               .eint_gpio_init = exynos_eint_gpio_init,
> > +               .suspend        = exynos_pinctrl_suspend,
> > +               .resume = exynos_pinctrl_resume,
> > +       }, {
> > +               /* pin banks of gs101 pin-controller (HSI1) */
> > +               .pin_banks      = gs101_pin_hsi1,
> > +               .nr_banks       = ARRAY_SIZE(gs101_pin_hsi1),
> > +               .eint_gpio_init = exynos_eint_gpio_init,
> > +               .suspend        = exynos_pinctrl_suspend,
> > +               .resume         = exynos_pinctrl_resume,
> > +       }, {
> > +               /* pin banks of gs101 pin-controller (HSI2) */
> > +               .pin_banks      = gs101_pin_hsi2,
> > +               .nr_banks       = ARRAY_SIZE(gs101_pin_hsi2),
> > +               .eint_gpio_init = exynos_eint_gpio_init,
> > +               .suspend        = exynos_pinctrl_suspend,
> > +               .resume         = exynos_pinctrl_resume,
> > +       },
> > +};
> > +
> > +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> > +       .ctrl           = gs101_pin_ctrl,
> > +       .num_ctrl       = ARRAY_SIZE(gs101_pin_ctrl),
> > +};
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> > index 800831aa8357..014f0c37f97f 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> > @@ -533,6 +533,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
> >                         .data = &exynos7_wkup_irq_chip },
> >         { .compatible = "samsung,exynosautov9-wakeup-eint",
> >                         .data = &exynos7_wkup_irq_chip },
> > +       { .compatible = "google,gs101-wakeup-eint",
> > +                       .data = &exynos7_wkup_irq_chip },
> >         { }
> >  };
> >
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> > index 63b2426ad5d6..0dd013654bd2 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> > @@ -147,6 +147,40 @@
> >                 .name           = id                            \
> >         }
> >
> > +#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id)   \
> > +       {                                               \
> > +               .type           = &types,               \
> > +               .pctl_offset    = reg,                  \
> > +               .nr_pins        = pins,                 \
> > +               .eint_type      = EINT_TYPE_NONE,       \
> > +               .fltcon_type    = FLT_DEFAULT           \
> > +               .name           = id                    \
> > +       }
> > +
> > +#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> > +       {                                               \
> > +               .type           = &types,               \
> > +               .pctl_offset    = reg,                  \
> > +               .nr_pins        = pins,                 \
> > +               .eint_type      = EINT_TYPE_GPIO,       \
> > +               .eint_offset    = offs,                 \
> > +               .fltcon_type    = fltcontype,           \
> > +               .fltcon_offset  = fltcon_offs,          \
> > +               .name           = id                    \
> > +       }
> > +
> > +#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> > +       {                                               \
> > +               .type           = &types,               \
> > +               .pctl_offset    = reg,                  \
> > +               .nr_pins        = pins,                 \
> > +               .eint_type      = EINT_TYPE_WKUP,       \
> > +               .eint_offset    = offs,                 \
> > +               .fltcon_type    = fltcontype,           \
> > +               .fltcon_offset  = fltcon_offs,          \
> > +               .name           = id                    \
> > +       }
> > +
>
> Looks to me that instead of adding new macros the already existing
> EXYNOS850_PIN_BANK_* should be extended and re-used. Because those
> pinctrl IP-cores on all modern Exynos chips look very similar, even if
> you compare the downstream code. If EXYNOS850 prefix looks confusing,
> maybe it can be renamed to EXYNOS9 or something like that. Those
> filter parameters are also present in Exynos850 downstream kernel
> code. So I just feel like the proper way to add that feature would be
> to add that also for all modern ARM64 Exynos variants while at it.
>
> >  /**
> >   * struct exynos_weint_data: irq specific data for all the wakeup interrupts
> >   * generated by the external wakeup interrupt controller.
> > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> > index 449f8109d8b5..12176f98440d 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> > @@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
> >                 .data = &exynosautov9_of_data },
> >         { .compatible = "tesla,fsd-pinctrl",
> >                 .data = &fsd_of_data },
> > +       { .compatible = "google,gs101-pinctrl",
> > +               .data = &gs101_of_data },
> >  #endif
> >  #ifdef CONFIG_PINCTRL_S3C64XX
> >         { .compatible = "samsung,s3c64xx-pinctrl",
> > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> > index de2ca8e8b378..e62e909fb10d 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> > @@ -374,6 +374,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
> >  extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
> >  extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
> >  extern const struct samsung_pinctrl_of_match_data fsd_of_data;
> > +extern const struct samsung_pinctrl_of_match_data gs101_of_data;
> >  extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
> >  extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
> >  extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
> > --
> > 2.42.0.655.g421f12c284-goog
> >

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Sam Protsenko]

On Tue, Nov 7, 2023 at 7:57 AM Peter Griffin <peter.griffin@linaro.org> wrote:
>
> Hi Chanwoo,
>
> Thanks for your review!
>
> On Wed, 18 Oct 2023 at 17:51, Chanwoo Choi <chanwoo@kernel.org> wrote:
> >
> > Hi Peter,
> >
> > On 23. 10. 12. 03:48, Peter Griffin wrote:
> > > CMU_TOP is the top level clock management unit which contains PLLs, muxes
> > > and gates that feed the other clock management units.
> > >
> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > > ---
> > >  drivers/clk/samsung/Kconfig     |    9 +
> > >  drivers/clk/samsung/Makefile    |    2 +
> > >  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
> > >  3 files changed, 1562 insertions(+)
> > >  create mode 100644 drivers/clk/samsung/clk-gs101.c
> > >
> > > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> > > index 76a494e95027..14362ec9c543 100644
> > > --- a/drivers/clk/samsung/Kconfig
> > > +++ b/drivers/clk/samsung/Kconfig
> > > @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
> > >       select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
> > >       select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> > >       select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> > > +     select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
> > >       select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> > >
> > >  config S3C64XX_COMMON_CLK
> > > @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
> > >         status of the certains clocks from SoC, but it could also be tied to
> > >         other devices as an input clock.
> > >
> > > +config GOOGLE_GS101_COMMON_CLK
> > > +     bool "Google gs101 clock controller support" if COMPILE_TEST
> > > +     depends on COMMON_CLK_SAMSUNG
> > > +     depends on EXYNOS_ARM64_COMMON_CLK
> > > +     help
> > > +       Support for the clock controller present on the Google gs101 SoC.
> > > +       Choose Y here only if you build for this SoC.
> > > +
> >
> > (snip)
> >
> > > +
> > > +/* gs101 */
> > > +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> > > +     /* CMU_TOP_PURECLKCOMP */
> > > +     MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> > > +         PLL_CON0_PLL_SHARED0, 4, 1),
> > > +     MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> > > +         PLL_CON0_PLL_SHARED1, 4, 1),
> > > +     MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> > > +         PLL_CON0_PLL_SHARED2, 4, 1),
> > > +     MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> > > +         PLL_CON0_PLL_SHARED3, 4, 1),
> > > +     MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> > > +         PLL_CON0_PLL_SPARE, 4, 1),
> > > +
> > > +     /* BUS0 */
> > > +     MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> > > +     MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
> >
> > In order to keep the consistent naming style,
> > I think that need to change from 'mout_cmu_boost' to 'mout_cmu_cmu_boost'.
>
> Yes, that's a good point, and a good spot! Will fix it in v4.
>

Why do we need cmu_cmu part at all? From the look of it, renaming all
*_cmu_cmu_* clocks to just cmu wouldn't cause any naming conflicts. So
I don't see any benefit of double cmu prefix really.

> >
> > > +         CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> > > +
> > > +     /* BUS1 */
> > > +     MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> > > +
> > > +     /* BUS2 */
> > > +     MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> > > +
> > > +     /* CORE */
> > > +     MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> > > +
> > > +     /* EH */
> > > +     MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> >
> > 'mout_cmu_core_bus' and 'mout_cmu_eh_bus' uses the same register/shift/width information.
> > I think it should be modified by changing the regiter or changing the shift/width information.
>
> It should be using the CLK_CON_MUX_MUX_CLKCMU_EH_BUS register.
> Will fix it in v4.
>
> >
> > > +
> > > +     /* CPUCL{0,1,2,} */
> > > +     MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> > > +
> > > +     MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> > > +
> > > +     MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> > > +
> > > +     MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> > > +         CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> > > +
> > > +     MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
> > >
> >
> > (snip)
> >
> > > +     /* PDP */
> > > +     MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> > > +
> > > +     /* PDP */
> > > +     MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
> > > +
> > > +     /* IPP */
> > > +     MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> > > +
> > > +     /* G3AA */
> > > +     MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> > > +         CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
> >
> > I think that need to change the mux name and mux parent name
> > because other mux name use the twice word according to the register name
> > even if use the same work such as 'mout_cmu_g2d_g2d', 'mout_cmu_mcsc_mcsc' and 'mout_cmu_mfc_mfc'.
> > - mout_cmu_g3aa -> mout_cmu_g3aa_g3aa
> > - mout_cmu_g3aa_p -> mount_cmu_g3aa_g3aa_p
>
> Will fix in v4
>

That consistent name duplication, while not causing any conflicts when
being removed, looks suspicious to me. That's probably some internal
scheme which doesn't make much sense for us and doesn't bring any
value, in terms of clock drivers. Maybe it'll be better to instead get
rid of such duplication throughout the driver, at least for clock name
strings? I mention this, because that's what I did in clk-exynos850.
With the only exception being the main domain clocks, which basically
enables/disables the whole unit internally, e.g.

    GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", ...

which "G3D domain gate clock that enables/disables G3D", or something
like that. But clk-exynos850 doesn't have any duplicating bits like
"cmu_cmu" or "g3d_g3d". And the reason why I did that is I wanted
those clock names appear short and nice in device tree, as there were
no benefits in those duplicating bits.

> >
> > (snip)
> >
> > > +     /* CSIS */
> > > +     GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> > > +          CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> > > +     /* PDP */
> > > +     GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> > > +          CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> > > +
> > > +     GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
> > > +          CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> > > +
> > > +     /* IPP */
> > > +     GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> > > +          CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> > > +     /* G3AA */
> > > +     GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> > > +          CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
> >
> > ditto.
> > gout_cmu_g3aa -> gout_cmu_g3aa_g3aa
> > mout_cmu_g3aa -> mout_cmu_g3aa_g3aa
>

Ditto.

> Will fix in V4
>
> regards,
>
> Peter.

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Peter Griffin]

Hi Krzysztof,

On Thu, 12 Oct 2023 at 07:40, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 11/10/2023 20:48, Peter Griffin wrote:
>
> ...
>
> > diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> > new file mode 100644
> > index 000000000000..37fb0a4dc8d3
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> > @@ -0,0 +1,504 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * GS101 SoC
> > + *
> > + * Copyright 2019-2023 Google LLC
> > + *
> > + */
> > +
> > +#include <dt-bindings/clock/google,gs101.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +     compatible = "google,gs101";
> > +     #address-cells = <2>;
> > +     #size-cells = <1>;
> > +
> > +     interrupt-parent = <&gic>;
> > +
> > +     aliases {
> > +             pinctrl0 = &pinctrl_0;
> > +             pinctrl1 = &pinctrl_1;
> > +             pinctrl2 = &pinctrl_2;
> > +             pinctrl3 = &pinctrl_3;
> > +             pinctrl4 = &pinctrl_4;
> > +             pinctrl5 = &pinctrl_5;
> > +             pinctrl6 = &pinctrl_6;
> > +             pinctrl7 = &pinctrl_7;
> > +             serial0 = &serial_0;
> > +     };
> > +
> > +     arm-pmu {
>
> pmu-0

will fix
>
> > +             compatible = "arm,armv8-pmuv3";
> > +             interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> > +     };
> > +
> > +     dsu-pmu-0 {
>
> pmu-1

will fix

>
>
> > +             compatible = "arm,dsu-pmu";
> > +             interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
> > +             cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
> > +                    <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> > +     };
> > +
> > +     /* TODO replace with CCF clock */
> > +     dummy_clk: oscillator {
> > +             compatible = "fixed-clock";
> > +             #clock-cells = <0>;
> > +             clock-frequency = <12345>;
> > +             clock-output-names = "pclk";
> > +     };
> > +
> > +     cpus {
> > +             #address-cells = <2>;
> > +             #size-cells = <0>;
> > +
> > +             cpu-map {
> > +                     cluster0 {
> > +                             core0 {
> > +                                     cpu = <&cpu0>;
> > +                             };
> > +                             core1 {
> > +                                     cpu = <&cpu1>;
> > +                             };
> > +                             core2 {
> > +                                     cpu = <&cpu2>;
> > +                             };
> > +                             core3 {
> > +                                     cpu = <&cpu3>;
> > +                             };
> > +                     };
> > +
> > +                     cluster1 {
> > +                             core0 {
> > +                                     cpu = <&cpu4>;
> > +                             };
> > +                             core1 {
> > +                                     cpu = <&cpu5>;
> > +                             };
> > +                     };
> > +
> > +                     cluster2 {
> > +                             core0 {
> > +                                     cpu = <&cpu6>;
> > +                             };
> > +                             core1 {
> > +                                     cpu = <&cpu7>;
> > +                             };
> > +                     };
> > +             };
> > +
> > +             cpu0: cpu@0 {
> > +                     device_type = "cpu";
> > +                     compatible = "arm,armv8";
> > +                     reg = <0x0 0x0000>;
> > +                     enable-method = "psci";
> > +                     cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> > +                     capacity-dmips-mhz = <250>;
> > +                     dynamic-power-coefficient = <70>;
> > +             };
> > +
> > +             cpu1: cpu@100 {
> > +                     device_type = "cpu";
> > +                     compatible = "arm,armv8";
> > +                     reg = <0x0 0x0100>;
> > +                     enable-method = "psci";
> > +                     cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> > +                     capacity-dmips-mhz = <250>;
> > +                     dynamic-power-coefficient = <70>;
> > +             };
> > +
> > +             cpu2: cpu@200 {
> > +                     device_type = "cpu";
> > +                     compatible = "arm,armv8";
> > +                     reg = <0x0 0x0200>;
> > +                     enable-method = "psci";
> > +                     cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> > +                     capacity-dmips-mhz = <250>;
> > +                     dynamic-power-coefficient = <70>;
> > +             };
> > +
> > +             cpu3: cpu@300 {
> > +                     device_type = "cpu";
> > +                     compatible = "arm,armv8";
> > +                     reg = <0x0 0x0300>;
> > +                     enable-method = "psci";
> > +                     cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> > +                     capacity-dmips-mhz = <250>;
> > +                     dynamic-power-coefficient = <70>;
> > +             };
> > +
> > +             cpu4: cpu@400 {
> > +                     device_type = "cpu";
> > +                     compatible = "arm,armv8";
> > +                     reg = <0x0 0x0400>;
> > +                     enable-method = "psci";
> > +                     cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> > +                     capacity-dmips-mhz = <620>;
> > +                     dynamic-power-coefficient = <284>;
> > +             };
> > +
> > +             cpu5: cpu@500 {
> > +                     device_type = "cpu";
> > +                     compatible = "arm,armv8";
> > +                     reg = <0x0 0x0500>;
> > +                     enable-method = "psci";
> > +                     cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> > +                     capacity-dmips-mhz = <620>;
> > +                     dynamic-power-coefficient = <284>;
> > +             };
> > +
> > +             cpu6: cpu@600 {
> > +                     device_type = "cpu";
> > +                     compatible = "arm,armv8";
> > +                     reg = <0x0 0x0600>;
> > +                     enable-method = "psci";
> > +                     cpu-idle-states =  <&HERA_CPU_SLEEP>;
> > +                     capacity-dmips-mhz = <1024>;
> > +                     dynamic-power-coefficient = <650>;
> > +             };
> > +
> > +             cpu7: cpu@700 {
> > +                     device_type = "cpu";
> > +                     compatible = "arm,armv8";
> > +                     reg = <0x0 0x0700>;
> > +                     enable-method = "psci";
> > +                     cpu-idle-states =  <&HERA_CPU_SLEEP>;
> > +                     capacity-dmips-mhz = <1024>;
> > +                     dynamic-power-coefficient = <650>;
> > +             };
> > +
> > +             idle-states {
> > +                     entry-method = "psci";
> > +
> > +                     ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> > +                             idle-state-name = "c2";
> > +                             compatible = "arm,idle-state";
> > +                             arm,psci-suspend-param = <0x0010000>;
> > +                             entry-latency-us = <70>;
> > +                             exit-latency-us = <160>;
> > +                             min-residency-us = <2000>;
> > +                     };
> > +
> > +                     ENYO_CPU_SLEEP: cpu-enyo-sleep {
> > +                             idle-state-name = "c2";
> > +                             compatible = "arm,idle-state";
> > +                             arm,psci-suspend-param = <0x0010000>;
> > +                             entry-latency-us = <150>;
> > +                             exit-latency-us = <190>;
> > +                             min-residency-us = <2500>;
> > +                     };
> > +
> > +                     HERA_CPU_SLEEP: cpu-hera-sleep {
> > +                             idle-state-name = "c2";
> > +                             compatible = "arm,idle-state";
> > +                             arm,psci-suspend-param = <0x0010000>;
> > +                             entry-latency-us = <235>;
> > +                             exit-latency-us = <220>;
> > +                             min-residency-us = <3500>;
> > +                     };
> > +             };
> > +     };
> > +
> > +     /* bootloader requires ect node */
> > +     ect {
>
> This needs bindings.

I experimented a bit more and the minimum I need is an empty dt node
called ect, otherwise the bootloader will boot loop and we can't boot
the kernel
[   2.977870] [E] [BOOT] fdt /ect path not found -1

Apart from a comment indicating that the bootloader requires this
empty ect dt node, what other bindings documentation would you like to
see? Something in google.yaml?

>
> > +             parameter_address = <0x90000000>;
>
> No underscores in property names. Use hyphen.
>
> > +             parameter_size = <0x53000>;
>
> No underscores.

Fortunately I can remove parameter_address and parameter_size and
still boot, so I will remove these in the next version.

Thanks,

Peter.

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Peter Griffin]

Hi Krzysztof,


On Thu, 12 Oct 2023 at 07:44, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 11/10/2023 20:48, Peter Griffin wrote:
> > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> > phones. It features:
> > * 4xA55 little cluster
> > * 2xA76 Mid cluster
> > * 2xX1 Big cluster
> >
>
> ...
>
> > +     gpa10: gpa10-gpio-bank  {
> > +             gpio-controller;
> > +             #gpio-cells = <2>;
> > +             interrupt-controller;
> > +             #interrupt-cells = <2>;
> > +             interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> > +                        <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
> > +
> > +     uart15_bus: uart15-bus-pins {
> > +            samsung,pins = "gpa2-3", "gpa2-4";
> > +            samsung,pin-function = <2>;
>
> GS101_PIN_FUNC_2

will fix
>
> > +            samsung,pin-pud = <0>;
>
> GS101_PIN_PULL_NONE

will fix

>
> > +     };
> > +
> > +     uart16_bus: uart16-bus-pins {
> > +            samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> > +            samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +            samsung,pin-pud = <GS101_PIN_PULL_NONE>;
>
> But here it is correct...
>
> > +     };
> > +
> > +     uart16_bus_rts: uart1-bus-rts-pins {
> > +             samsung,pins = "gpa3-2";
> > +             samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +             samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +             samsung,pin-val = <1>;
>
> Why do you set UART RTS pin value?

It's a remnant from the downstream drivers that support rts-gpio control.
I will remove the samsung,pin-val = <1> in the next version.

Thanks,

Peter

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Krzysztof Kozlowski]

On 25/11/2023 00:22, Peter Griffin wrote:
>>> +
>>> +     /* bootloader requires ect node */
>>> +     ect {
>>
>> This needs bindings.
> 
> I experimented a bit more and the minimum I need is an empty dt node
> called ect, otherwise the bootloader will boot loop and we can't boot
> the kernel
> [   2.977870] [E] [BOOT] fdt /ect path not found -1
> 
> Apart from a comment indicating that the bootloader requires this
> empty ect dt node, what other bindings documentation would you like to
> see? Something in google.yaml?

Yes, it would be enough.


Best regards,
Krzysztof

Re: [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support

[Peter Griffin]

Hi Sam,

Thanks for your review. Apologies I missed this in v4 series. See my
comments inline below.

On Thu, 12 Oct 2023 at 08:23, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6,
> > (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
> > phones. It features:
> > * 4xA55 little cluster
> > * 2xA76 Mid cluster
> > * 2xX1 Big cluster
> >
> > This commit adds the basic device tree for gs101 (SoC).
> > Further platform support will be added over time.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  arch/arm64/Kconfig.platforms                  |    6 +
> >  arch/arm64/boot/dts/Makefile                  |    1 +
> >  arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 +++++++++++++++++
> >  arch/arm64/boot/dts/google/gs101-pinctrl.h    |   32 +
> >  arch/arm64/boot/dts/google/gs101.dtsi         |  504 +++++++
> >  5 files changed, 1818 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> >  create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h
> >  create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi
> >
> > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> > index 6069120199bb..a5ed1b719488 100644
> > --- a/arch/arm64/Kconfig.platforms
> > +++ b/arch/arm64/Kconfig.platforms
> > @@ -107,6 +107,12 @@ config ARCH_EXYNOS
> >         help
> >           This enables support for ARMv8 based Samsung Exynos SoC family.
> >
> > +config ARCH_GOOGLE_TENSOR
> > +       bool "Google Tensor SoC fmaily"
> > +       depends on ARCH_EXYNOS
> > +       help
> > +         Support for ARMv8 based Google Tensor platforms.
> > +
> >  config ARCH_SPARX5
> >         bool "Microchip Sparx5 SoC family"
> >         select PINCTRL
> > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> > index 30dd6347a929..a4ee7b628114 100644
> > --- a/arch/arm64/boot/dts/Makefile
> > +++ b/arch/arm64/boot/dts/Makefile
> > @@ -13,6 +13,7 @@ subdir-y += broadcom
> >  subdir-y += cavium
> >  subdir-y += exynos
> >  subdir-y += freescale
> > +subdir-y += google
> >  subdir-y += hisilicon
> >  subdir-y += intel
> >  subdir-y += lg
> > diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..ba88000c3ed8
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.dtsi
> > @@ -0,0 +1,1275 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * GS101 SoC pin-mux and pin-config device tree source
> > + *
> > + * Copyright 2019-2023 Google LLC
> > + *
>
> This line is not needed. Also, maybe also add Linaro copyright here?

Will fix
>
> > + */
> > +
> > +#include "gs101-pinctrl.h"
> > +
> > +/* GPIO_ALIVE */
> > +&pinctrl_0 {
>
> Why not just rename it to pinctrl_alive and remove the comment? The
> same goes for all pinctrl nodes below.

Will fix

>
> > +       gpa0: gpa0-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>
> Here and further: please align it to be at the same indentation level
> as above line.

Will fix

>
> > +                          <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa1: gpa1-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa2: gpa2-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa3: gpa3-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa4: gpa4-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa5: gpa5-gpio-bank  {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa9: gpa9-gpio-bank  {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa10: gpa10-gpio-bank  {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       uart15_bus: uart15-bus-pins {
> > +              samsung,pins = "gpa2-3", "gpa2-4";
> > +              samsung,pin-function = <2>;
> > +              samsung,pin-pud = <0>;
>
> Could above two lines be replaced with some meaningful consts? I see
> it's done below.

Will fix
>
> > +       };
> > +
> > +       uart16_bus: uart16-bus-pins {
> > +              samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
> > +              samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +              samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +       };
> > +
> > +       uart16_bus_rts: uart1-bus-rts-pins {
> > +               samsung,pins = "gpa3-2";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-val = <1>;
> > +       };
> > +
> > +       uart16_bus_tx_dat: uart1-bus-tx-dat-pins {
> > +               samsung,pins = "gpa3-1";
> > +               samsung,pin-val = <1>;
> > +       };
> > +
> > +       uart16_bus_tx_con: uart1-bus-tx-con-pins {
> > +               samsung,pins = "gpa3-1";
> > +               samsung,pin-function = <1>;
>
> Named const?

Will fix
>
> > +       };
> > +
> > +       uart17_bus: uart17-bus-pins {
> > +              samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
> > +              samsung,pin-function = <2>;
> > +              samsung,pin-pud = <0>;
>
> Here and further: if possible, try to use named constants.

Will fix throughout.

>
> > +       };
> > +
> > +       spi15_bus: spi15-bus-pins {
> > +               samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi15_cs: spi15-cs-pins {
> > +               samsung,pins = "gpa4-3";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +};
> > +
> > +/* GPIO_FAR_ALIVE */
> > +&pinctrl_1 {
> > +       gpa6: gpa6-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa7: gpa7-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa8: gpa8-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa11: gpa11-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +};
> > +
> > +/* GPIO_GSACORE */
> > +&pinctrl_2 {
> > +       gps0: gps0-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gps1: gps1-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gps2: gps2-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +};
> > +
> > +/* GPIO_GSACTRL */
> > +&pinctrl_3 {
> > +       gps3: gps3-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +};
> > +
> > +/* GPIO_HSI1 */
> > +&pinctrl_6 {
> > +       gph0: gph0-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gph1: gph1-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       pcie0_clkreq: pcie0-clkreq-pins{
> > +               samsung,pins = "gph0-1";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <3>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> > +               samsung,pin-con-pdn = <3>;
> > +               samsung,pin-pud-pdn = <3>;
>
> What are those two properties? I don't see them documented in
> dt-bindings or being mentioned in the driver.

These properties have been in the samsung pinctrl driver since it was
upstreamed by Linaro in 2012 :) They are used for pin function and
pull up/down config in power down mode. See also
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml

>
> > +       };
> > +
> > +       pcie0_perst: pcie0-perst-pins {
> > +               samsung,pins = "gph0-0";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> > +               samsung,pin-con-pdn = <3>;
> > +       };
> > +};
> > +
> > +/* GPIO_HSI2 */
> > +&pinctrl_7 {
> > +       gph2: gph2-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gph3: gph3-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gph4: gph4-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       sd2_clk: sd2-clk-pins {
> > +               samsung,pins = "gph4-0";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> > +       };
> > +
> > +       sd2_cmd: sd2-cmd-pins {
> > +               samsung,pins = "gph4-1";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <3>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> > +       };
> > +
> > +       sd2_bus1: sd2-bus-width1-pins {
> > +               samsung,pins = "gph4-2";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <3>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> > +       };
> > +
> > +       sd2_bus4: sd2-bus-width4-pins {
> > +               samsung,pins = "gph4-3", "gph4-4", "gph4-5";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <3>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> > +       };
> > +
> > +       sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
> > +               samsung,pins = "gph4-0";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
> > +               samsung,pins = "gph4-0";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
> > +               samsung,pins = "gph4-0";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
> > +       };
> > +
> > +       sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
> > +               samsung,pins = "gph4-0";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> > +       };
> > +
> > +       ufs_rst_n: ufs-rst-n-pins {
> > +               samsung,pins = "gph3-1";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-con-pdn = <3>;
> > +               samsung,pin-pud-pdn = <0>;
> > +       };
> > +
> > +       ufs_refclk_out: ufs-refclk-out-pins {
> > +               samsung,pins = "gph3-0";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-con-pdn = <3>;
> > +               samsung,pin-pud-pdn = <0>;
> > +       };
> > +
> > +       pcie1_clkreq: pcie1-clkreq-pins {
> > +               samsung,pins = "gph2-1";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <3>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> > +               samsung,pin-con-pdn = <3>;
> > +               samsung,pin-pud-pdn = <3>;
> > +       };
> > +
> > +       pcie1_perst: pcie1-perst-pins {
> > +               samsung,pins = "gph2-0";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
> > +               samsung,pin-con-pdn = <3>;
> > +       };
> > +};
> > +
> > +/* GPIO_PERIC0 */
> > +&pinctrl_4 {
> > +       gpp0: gpp0-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp1: gpp1-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp2: gpp2-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp3: gpp3-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp4: gpp4-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp5: gpp5-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp6: gpp6-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp7: gpp7-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp8: gpp8-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp9: gpp9-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp10: gpp10-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp11: gpp11-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp12: gpp12-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp13: gpp13-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp14: gpp14-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp15: gpp15-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp16: gpp16-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp17: gpp17-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp18: gpp18-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp19: gpp19-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       /* USI_PERIC0_UART_DBG */
> > +       uart0_bus: uart0-bus-pins {
> > +               samsung,pins = "gpp1-2", "gpp1-3";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       disp_te_pri_on: disp-te-pri-on-pins {
> > +               samsung,pins = "gpp0-3";
> > +               samsung,pin-function = <0xf>;
> > +       };
> > +
> > +       disp_te_pri_off: disp-te-pri-off-pins {
> > +               samsung,pins = "gpp0-3";
> > +               samsung,pin-function = <0>;
> > +       };
> > +
> > +       disp_te_sec_on: disp-te-sec-on-pins {
> > +               samsung,pins = "gpp0-4";
> > +               samsung,pin-function = <0xf>;
> > +       };
> > +
> > +       disp_te_sec_off: disp-te-sec-off-pins {
> > +               samsung,pins = "gpp0-4";
> > +               samsung,pin-function = <0>;
> > +       };
> > +
> > +       sensor_mclk1_out: sensor-mclk1-out-pins {
> > +               samsung,pins = "gpp3-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk1_fn: sensor-mclk1-fn-pins {
> > +               samsung,pins = "gpp3-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk2_out: sensor-mclk2-out-pins {
> > +               samsung,pins = "gpp5-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk2_fn: sensor-mclk2-fn-pins {
> > +               samsung,pins = "gpp5-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk3_out: sensor-mclk3-out-pins {
> > +               samsung,pins = "gpp7-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk3_fn: sensor-mclk3-fn-pins {
> > +               samsung,pins = "gpp7-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk4_out: sensor-mclk4-out-pins {
> > +               samsung,pins = "gpp9-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk4_fn: sensor-mclk4-fn-pins {
> > +               samsung,pins = "gpp9-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk5_out: sensor-mclk5-out-pins {
> > +               samsung,pins = "gpp11-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk5_fn: sensor-mclk5-fn-pins {
> > +               samsung,pins = "gpp11-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk6_out: sensor-mclk6-out-pins {
> > +               samsung,pins = "gpp13-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk6_fn: sensor-mclk6-fn-pins {
> > +               samsung,pins = "gpp13-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk7_out: sensor-mclk7-out-pins {
> > +               samsung,pins = "gpp15-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk7_fn: sensor-mclk7-fn-pins {
> > +               samsung,pins = "gpp15-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk8_out: sensor-mclk8-out-pins {
> > +               samsung,pins = "gpp17-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       sensor_mclk8_fn: sensor-mclk8-fn-pins {
> > +               samsung,pins = "gpp17-0";
> > +               samsung,pin-function = <GS101_PIN_FUNC_2>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
> > +       };
> > +
> > +       hsi2c14_bus: hsi2c14-bus-pins {
> > +               samsung,pins = "gpp18-0", "gpp18-1";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart14_bus_single: uart14-bus-pins {
> > +               samsung,pins = "gpp18-0", "gpp18-1",
> > +                              "gpp18-2", "gpp18-3";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi14_bus: spi14-bus-pins {
> > +               samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi14_cs: spi14-cs-pins {
> > +               samsung,pins = "gpp18-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi14_cs_func: spi14-cs-func-pins {
> > +               samsung,pins = "gpp18-3";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c8_bus: hsi2c8-bus-pins {
> > +               samsung,pins = "gpp16-0", "gpp16-1";
> > +               samsung,pin-function = <GS101_PIN_FUNC_3>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +               samsung,pin-pud-pdn = <GS101_PIN_PDN_OUT0>;
> > +       };
> > +
> > +       uart8_bus_single: uart8-bus-pins {
> > +               samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
> > +                              "gpp16-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi8_bus: spi8-bus-pins {
> > +               samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi8_cs: spi8-cs-pins {
> > +               samsung,pins = "gpp16-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi8_cs_func: spi8-cs-func-pins {
> > +               samsung,pins = "gpp16-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c7_bus: hsi2c7-bus-pins {
> > +               samsung,pins = "gpp14-0", "gpp14-1";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart7_bus_single: uart7-bus-pins {
> > +               samsung,pins = "gpp14-0", "gpp14-1",
> > +                              "gpp14-2", "gpp14-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi7_bus: spi7-bus-pins {
> > +               samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi7_cs: spi7-cs-pins {
> > +               samsung,pins = "gpp14-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi7_cs_func: spi7-cs-func-pins {
> > +               samsung,pins = "gpp14-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c6_bus: hsi2c6-bus-pins {
> > +               samsung,pins = "gpp12-0", "gpp12-1";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart6_bus_single: uart6-bus-pins {
> > +               samsung,pins = "gpp12-0", "gpp12-1",
> > +                              "gpp12-2", "gpp12-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi6_bus: spi6-bus-pins {
> > +               samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi6_cs: spi6-cs-pins {
> > +               samsung,pins = "gpp12-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi6_cs_func: spi6-cs-func-pins {
> > +               samsung,pins = "gpp12-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c5_bus: hsi2c5-bus-pins {
> > +               samsung,pins = "gpp10-0", "gpp10-1";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart5_bus_single: uart5-bus-pins {
> > +               samsung,pins = "gpp10-0", "gpp10-1",
> > +                              "gpp10-2", "gpp10-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi5_bus: spi5-bus-pins {
> > +               samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +               samsung,pin-function = <GS101_PIN_FUNC_3>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
> > +               samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
> > +       };
> > +
> > +       spi5_cs_func: spi5-cs-func-pins {
> > +               samsung,pins = "gpp10-3";
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +               samsung,pin-function = <GS101_PIN_FUNC_3>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
> > +               samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
> > +       };
> > +
> > +       hsi2c4_bus: hsi2c4-bus-pins {
> > +               samsung,pins = "gpp8-0", "gpp8-1";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart4_bus_single: uart4-bus-pins {
> > +               samsung,pins = "gpp8-0", "gpp8-1",
> > +                              "gpp8-2", "gpp8-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi4_bus: spi4-bus-pins {
> > +               samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi4_cs: spi4-cs-pins {
> > +               samsung,pins = "gpp8-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi4_cs_func: spi4-cs-func-pins {
> > +               samsung,pins = "gpp8-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c3_bus: hsi2c3-bus-pins {
> > +               samsung,pins = "gpp6-0", "gpp6-1";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart3_bus_single: uart3-bus-pins {
> > +               samsung,pins = "gpp6-0", "gpp6-1",
> > +                              "gpp6-2", "gpp6-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi3_bus: spi3-bus-pins {
> > +               samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi3_cs: spi3-cs-pins {
> > +               samsung,pins = "gpp6-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi3_cs_func: spi3-cs-func-pins {
> > +               samsung,pins = "gpp6-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c2_bus: hsi2c2-bus-pins {
> > +               samsung,pins = "gpp4-0", "gpp4-1";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart2_bus_single: uart2-bus-pins {
> > +               samsung,pins = "gpp4-0", "gpp4-1",
> > +                              "gpp4-2", "gpp4-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi2_bus: spi2-bus-pins {
> > +               samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi2_cs: spi2-cs-pins {
> > +               samsung,pins = "gpp4-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi2_cs_func: spi2-cs-func-pins {
> > +               samsung,pins = "gpp4-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c1_bus: hsi2c1-bus-pins {
> > +               samsung,pins = "gpp2-0", "gpp2-1";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart1_bus_single: uart1-bus-pins {
> > +               samsung,pins = "gpp2-0", "gpp2-1",
> > +                              "gpp2-2", "gpp2-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi1_bus: spi1-bus-pins {
> > +               samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi1_cs: spi1-cs-pins {
> > +               samsung,pins = "gpp2-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi1_cs_func: spi1-cs-func-pins {
> > +               samsung,pins = "gpp2-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +};
> > +
> > +/* GPIO_PERIC1 */
> > +&pinctrl_5 {
> > +       gpp20: gpp20-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp21: gpp21-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp22: gpp22-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp23: gpp23-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp24: gpp24-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp25: gpp25-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp26: gpp26-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp27: gpp27-gpio-bank {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       hsi2c13_bus: hsi2c13-bus-pins  {
> > +               samsung,pins = "gpp25-0", "gpp25-1";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart13_bus_single: uart13-bus-pins {
> > +              samsung,pins = "gpp25-0", "gpp25-1",
> > +                             "gpp25-2", "gpp25-3";
> > +              samsung,pin-function = <2>;
> > +              samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi13_bus: spi13-bus-pins {
> > +               samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi13_cs: spi13-cs-pins {
> > +               samsung,pins = "gpp25-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi13_cs_func: spi13-cs-func-pins {
> > +               samsung,pins = "gpp25-3";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c12_bus: hsi2c12-bus-pins {
> > +               samsung,pins = "gpp23-4", "gpp23-5";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart12_bus_single: uart12-bus-pins {
> > +               samsung,pins = "gpp23-4", "gpp23-5",
> > +                              "gpp23-6", "gpp23-7";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi12_bus: spi12-bus-pins {
> > +               samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi14_cs2: spi14-cs2-pins {
> > +               samsung,pins = "gpp23-6";
> > +               samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <GS101_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi12_cs: spi12-cs-pins {
> > +               samsung,pins = "gpp23-7";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi12_cs_func: spi12-cs-func-pins {
> > +               samsung,pins = "gpp23-7";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c11_bus: hsi2c11-bus-pins {
> > +               samsung,pins = "gpp23-0", "gpp23-1";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart11_bus_single: uart11-bus-pins {
> > +               samsung,pins = "gpp23-0", "gpp23-1",
> > +                              "gpp23-2", "gpp23-3";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi11_bus: spi11-bus-pins {
> > +               samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi11_cs: spi11-cs-pins {
> > +               samsung,pins = "gpp23-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi11_cs_func: spi11-cs-func-pins {
> > +               samsung,pins = "gpp23-3";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c10_bus: hsi2c10-bus-pins {
> > +               samsung,pins = "gpp21-0", "gpp21-1";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart10_bus_single: uart10-bus-pins {
> > +               samsung,pins = "gpp21-0", "gpp21-1",
> > +                              "gpp21-2", "gpp21-3";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi10_bus: spi10-bus-pins {
> > +               samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi10_cs: spi10-cs-pins {
> > +               samsung,pins = "gpp21-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi10_cs_func: spi10-cs-func-pins {
> > +               samsung,pins = "gpp21-3";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c9_bus: hsi2c9-bus-pins {
> > +               samsung,pins = "gpp20-4", "gpp20-5";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart9_bus_single: uart9-bus-pins {
> > +               samsung,pins = "gpp20-4", "gpp20-5",
> > +                              "gpp20-6", "gpp20-7";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi9_bus: spi9-bus-pins {
> > +               samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi9_cs: spi9-cs-pins {
> > +               samsung,pins = "gpp20-7";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi9_cs_func: spi9-cs-func-pins {
> > +               samsung,pins = "gpp20-7";
> > +               samsung,pin-function = <2>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       hsi2c0_bus: hsi2c0-bus-pins {
> > +               samsung,pins = "gpp20-0", "gpp20-1";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       uart0_bus_single: uart0-bus-pins {
> > +               samsung,pins = "gpp20-0", "gpp20-1",
> > +                              "gpp20-2", "gpp20-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +       };
> > +
> > +       spi0_bus: spi0-bus-pins {
> > +               samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi0_cs: spi0-cs-pins {
> > +               samsung,pins = "gpp20-3";
> > +               samsung,pin-function = <1>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +
> > +       spi0_cs_func: spi0-cs-func-pins {
> > +               samsung,pins = "gpp20-3";
> > +               samsung,pin-function = <3>;
> > +               samsung,pin-pud = <0>;
> > +               samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
> > +       };
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/google/gs101-pinctrl.h b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> > new file mode 100644
> > index 000000000000..16c54888f4bb
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/gs101-pinctrl.h
> > @@ -0,0 +1,32 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Pinctrl binding constants for GS101
> > + *
> > + * Copyright (c) 2020-2023 Google, LLC.
> > + */
> > +
> > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__
> > +#define __DT_BINDINGS_PINCTRL_GS101_H__
> > +
> > +#define GS101_PIN_PULL_NONE            0
> > +#define GS101_PIN_PULL_DOWN            1
> > +#define GS101_PIN_PULL_UP              3
> > +
> > +/* Pin function in power down mode */
> > +#define GS101_PIN_PDN_OUT0             0
> > +#define GS101_PIN_PDN_OUT1             1
> > +#define GS101_PIN_PDN_INPUT            2
> > +#define GS101_PIN_PDN_PREV             3
> > +
> > +/* GS101 drive strengths */
> > +#define GS101_PIN_DRV_2_5_MA           0
> > +#define GS101_PIN_DRV_5_MA             1
> > +#define GS101_PIN_DRV_7_5_MA           2
> > +#define GS101_PIN_DRV_10_MA            3
> > +
> > +#define GS101_PIN_FUNC_INPUT           0
> > +#define GS101_PIN_FUNC_OUTPUT          1
> > +#define GS101_PIN_FUNC_2               2
> > +#define GS101_PIN_FUNC_3               3
> > +
>
> Maybe it's possible to somehow re-use already existing values in
> arch/arm64/boot/dts/exynos/exynos-pinctrl.h?

That is actually how it was in the first submission. The review
feedback was not to do that and have a dedicated gs101 header.

>
> > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
> > diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi
> > new file mode 100644
> > index 000000000000..37fb0a4dc8d3
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/gs101.dtsi
> > @@ -0,0 +1,504 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * GS101 SoC
> > + *
> > + * Copyright 2019-2023 Google LLC
> > + *
>
> This line is not needed. Also (but not sure): maybe add the author and
> Linaro copyright?

Will fix

>
> > + */
> > +
> > +#include <dt-bindings/clock/google,gs101.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +       compatible = "google,gs101";
> > +       #address-cells = <2>;
> > +       #size-cells = <1>;
> > +
> > +       interrupt-parent = <&gic>;
> > +
> > +       aliases {
> > +               pinctrl0 = &pinctrl_0;
> > +               pinctrl1 = &pinctrl_1;
> > +               pinctrl2 = &pinctrl_2;
> > +               pinctrl3 = &pinctrl_3;
> > +               pinctrl4 = &pinctrl_4;
> > +               pinctrl5 = &pinctrl_5;
> > +               pinctrl6 = &pinctrl_6;
> > +               pinctrl7 = &pinctrl_7;
> > +               serial0 = &serial_0;
> > +       };
> > +
> > +       arm-pmu {
> > +               compatible = "arm,armv8-pmuv3";
>
> Is there any more specifi Cortex PMU compatible for this chip?

Yes will fix.

>
> > +               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>
> Please try to keep it to 80 characters per line.

Will fix

>
> > +       };
> > +
> > +       dsu-pmu-0 {
> > +               compatible = "arm,dsu-pmu";
> > +               interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
> > +               cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
> > +                      <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> > +       };
> > +
> > +       /* TODO replace with CCF clock */
> > +       dummy_clk: oscillator {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <12345>;
> > +               clock-output-names = "pclk";
> > +       };
> > +
> > +       cpus {
> > +               #address-cells = <2>;
>
> Why 2-cells is needed here? If you make it 1, all below reg properties
> can be made 1-cell, which removes not needed 0x0.

Will fix
>
> > +               #size-cells = <0>;
> > +
> > +               cpu-map {
> > +                       cluster0 {
> > +                               core0 {
> > +                                       cpu = <&cpu0>;
> > +                               };
> > +                               core1 {
> > +                                       cpu = <&cpu1>;
> > +                               };
> > +                               core2 {
> > +                                       cpu = <&cpu2>;
> > +                               };
> > +                               core3 {
> > +                                       cpu = <&cpu3>;
> > +                               };
> > +                       };
> > +
> > +                       cluster1 {
> > +                               core0 {
> > +                                       cpu = <&cpu4>;
> > +                               };
> > +                               core1 {
> > +                                       cpu = <&cpu5>;
> > +                               };
> > +                       };
> > +
> > +                       cluster2 {
> > +                               core0 {
> > +                                       cpu = <&cpu6>;
> > +                               };
> > +                               core1 {
> > +                                       cpu = <&cpu7>;
> > +                               };
> > +                       };
> > +               };
> > +
> > +               cpu0: cpu@0 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,armv8";
>
> Is there maybe any more specific Cortex compatible?

Yes, will fix

>
> > +                       reg = <0x0 0x0000>;
> > +                       enable-method = "psci";
> > +                       cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> > +                       capacity-dmips-mhz = <250>;
> > +                       dynamic-power-coefficient = <70>;
> > +               };
> > +
> > +               cpu1: cpu@100 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,armv8";
> > +                       reg = <0x0 0x0100>;
> > +                       enable-method = "psci";
> > +                       cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> > +                       capacity-dmips-mhz = <250>;
> > +                       dynamic-power-coefficient = <70>;
> > +               };
> > +
> > +               cpu2: cpu@200 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,armv8";
> > +                       reg = <0x0 0x0200>;
> > +                       enable-method = "psci";
> > +                       cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> > +                       capacity-dmips-mhz = <250>;
> > +                       dynamic-power-coefficient = <70>;
> > +               };
> > +
> > +               cpu3: cpu@300 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,armv8";
> > +                       reg = <0x0 0x0300>;
> > +                       enable-method = "psci";
> > +                       cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
> > +                       capacity-dmips-mhz = <250>;
> > +                       dynamic-power-coefficient = <70>;
> > +               };
> > +
> > +               cpu4: cpu@400 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,armv8";
> > +                       reg = <0x0 0x0400>;
> > +                       enable-method = "psci";
> > +                       cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> > +                       capacity-dmips-mhz = <620>;
> > +                       dynamic-power-coefficient = <284>;
> > +               };
> > +
> > +               cpu5: cpu@500 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,armv8";
> > +                       reg = <0x0 0x0500>;
> > +                       enable-method = "psci";
> > +                       cpu-idle-states =  <&ENYO_CPU_SLEEP>;
> > +                       capacity-dmips-mhz = <620>;
> > +                       dynamic-power-coefficient = <284>;
> > +               };
> > +
> > +               cpu6: cpu@600 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,armv8";
> > +                       reg = <0x0 0x0600>;
> > +                       enable-method = "psci";
> > +                       cpu-idle-states =  <&HERA_CPU_SLEEP>;
> > +                       capacity-dmips-mhz = <1024>;
> > +                       dynamic-power-coefficient = <650>;
> > +               };
> > +
> > +               cpu7: cpu@700 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,armv8";
> > +                       reg = <0x0 0x0700>;
> > +                       enable-method = "psci";
> > +                       cpu-idle-states =  <&HERA_CPU_SLEEP>;
> > +                       capacity-dmips-mhz = <1024>;
> > +                       dynamic-power-coefficient = <650>;
> > +               };
> > +
> > +               idle-states {
> > +                       entry-method = "psci";
> > +
> > +                       ANANKE_CPU_SLEEP: cpu-ananke-sleep {
> > +                               idle-state-name = "c2";
> > +                               compatible = "arm,idle-state";
> > +                               arm,psci-suspend-param = <0x0010000>;
> > +                               entry-latency-us = <70>;
> > +                               exit-latency-us = <160>;
> > +                               min-residency-us = <2000>;
> > +                       };
> > +
> > +                       ENYO_CPU_SLEEP: cpu-enyo-sleep {
> > +                               idle-state-name = "c2";
> > +                               compatible = "arm,idle-state";
> > +                               arm,psci-suspend-param = <0x0010000>;
> > +                               entry-latency-us = <150>;
> > +                               exit-latency-us = <190>;
> > +                               min-residency-us = <2500>;
> > +                       };
> > +
> > +                       HERA_CPU_SLEEP: cpu-hera-sleep {
> > +                               idle-state-name = "c2";
> > +                               compatible = "arm,idle-state";
> > +                               arm,psci-suspend-param = <0x0010000>;
> > +                               entry-latency-us = <235>;
> > +                               exit-latency-us = <220>;
> > +                               min-residency-us = <3500>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       /* bootloader requires ect node */
> > +       ect {
> > +               parameter_address = <0x90000000>;
> > +               parameter_size = <0x53000>;
> > +       };
>
> The bootloader doesn't work if you just remove this?

That is correct, it boot loops failing to find the ect node in the
bootloader. I did some more investigation and we can actually remove
parameter_address and  parameter_size properties but the empty ect
node needs to be present to boot the kernel.
>
> > +
> > +       ext_24_5m: clock-1 {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <24576000>;
>
> The frequency is probably should be set in board dts file. Because the
> crystal is actually soldered on the board, not in SoC.

Will move. Although Xtal can only be 24576000 for this SoC.

>
> > +               clock-output-names = "oscclk";
> > +       };
> > +
> > +       ext_200m: clock-2 {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <200000000>;
>
> Ditto.

Will fix
>
> > +               clock-output-names = "ext-200m";
> > +       };
> > +
> > +       psci {
> > +               compatible = "arm,psci-1.0";
> > +               method = "smc";
> > +       };
> > +
> > +       reserved_memory: reserved-memory {
> > +               #address-cells = <2>;
>
> Doesn't look like 2-cell address is really needed here.

It is required, there is 8Gb of RAM on the board.

>
> > +               #size-cells = <1>;
> > +               ranges;
> > +
> > +               gsa_reserved_protected: gsa@90200000 {
> > +                       reg = <0x0 0x90200000 0x400000>;
> > +                       no-map;
> > +               };
> > +
> > +               tpu_fw_reserved: tpu-fw@93000000 {
> > +                       reg = <0x0 0x93000000 0x1000000>;
> > +                       no-map;
> > +               };
> > +
> > +               aoc_reserve: aoc@94000000 {
> > +                       reg = <0x0 0x94000000 0x03000000>;
> > +                       no-map;
> > +               };
> > +
> > +               abl_reserved: abl@f8800000 {
> > +                       reg = <0x0 0xf8800000 0x02000000>;
> > +                       no-map;
> > +               };
> > +
> > +               dss_log_reserved: dss-log-reserved@fd3f0000 {
> > +                       reg = <0 0xfd3f0000 0x0000e000>;
> > +                       no-map;
> > +               };
> > +
> > +               debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
> > +                       reg = <0 0xfd3fe000 0x00001000>;
> > +                       no-map;
> > +               };
> > +
> > +               bldr_log_reserved: bldr-log-reserved@fd800000 {
> > +                       reg = <0 0xfd800000 0x00100000>;
> > +                       no-map;
> > +               };
> > +
> > +               bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
> > +                       reg = <0 0xfd900000 0x00002000>;
> > +                       no-map;
> > +               };
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> > +               clock-frequency = <24576000>;
> > +       };
> > +
> > +       soc: soc@0 {
> > +               compatible = "simple-bus";
> > +               #address-cells = <2>;
>
> Is 2 cells are really needed for the addresses in this node? I only
> see 32-bit addresses below in reg properties.

It is a 36bit address bus, but I can add a ranges property to map the
addresses and then use address-cells 1.
So will fix in v5.

>
> > +               #size-cells = <1>;
> > +               ranges;
> > +
> > +               cmu_misc: clock-controller@10010000 {
> > +                       compatible = "google,gs101-cmu-misc";
> > +                       reg = <0x0 0x10010000 0x8000>;
> > +                       #clock-cells = <1>;
> > +                       clocks =  <&ext_24_5m>, <&cmu_top CLK_DOUT_MISC_BUS>;
> > +                       clock-names = "oscclk", "dout_cmu_misc_bus";
> > +               };
> > +
> > +               watchdog_cl0: watchdog@10060000 {
> > +                       compatible = "google,gs101-wdt";
> > +                       reg = <0x0 0x10060000 0x100>;
> > +                       interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0>, <&ext_24_5m>;
> > +                       clock-names = "watchdog", "watchdog_src";
> > +                       samsung,syscon-phandle = <&pmu_system_controller>;
> > +                       samsung,cluster-index = <0>;
> > +               };
> > +
> > +               watchdog_cl1: watchdog@10070000 {
> > +                       compatible = "google,gs101-wdt";
> > +                       reg = <0x0 0x10070000 0x100>;
> > +                       interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1>, <&ext_24_5m>;
> > +                       clock-names = "watchdog", "watchdog_src";
> > +                       samsung,syscon-phandle = <&pmu_system_controller>;
> > +                       samsung,cluster-index = <1>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               gic: interrupt-controller@10400000 {
> > +                    compatible = "arm,gic-v3";
> > +                    #interrupt-cells = <3>;
> > +                    interrupt-controller;
> > +                    reg = <0x0 0x10400000 0x10000>,    /* GICD */
> > +                          <0x0 0x10440000 0x100000>;   /* GICR * 8 */
> > +                    interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               sysreg_peric0: syscon@10821000 {
> > +                       compatible = "google,gs101-peric0-sysreg", "syscon";
> > +                       reg = <0x0 0x10821000 0x40000>;
> > +               };
> > +
> > +               /* GPIO_PERIC0 */
>
> This comment won't be needed if you rename pinctrl_4 -> pinctrl_peric0 :)

Will fix

>
> > +               pinctrl_4: pinctrl@10840000 {
> > +                       compatible = "google,gs101-pinctrl";
> > +                       reg = <0x0 0x10840000 0x00001000>;
> > +                       interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               serial_0: serial@10a00000 {
> > +                       compatible = "google,gs101-uart";
> > +                       reg = <0x0 0x10a00000 0xc0>;
> > +                       reg-io-width = <4>;
> > +                       samsung,uart-fifosize = <256>;
> > +                       interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> > +                       clock-names = "uart", "clk_uart_baud0";
> > +               };
>
> Does this SoC have USI blocks? If so, maybe this node should be made a
> children of some USI node?

Yes it is part of a USI block. I will update this in v5.

>
> > +
> > +               /* GPIO_PERIC1 */
> > +               pinctrl_5: pinctrl@10c40000 {
> > +                       compatible = "google,gs101-pinctrl";
> > +                       reg = <0x0 0x10C40000 0x00001000>;
> > +                       interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               sysreg_peric1: syscon@10c21000 {
> > +                       compatible = "google,gs101-peric1-sysreg", "syscon";
> > +                       reg = <0x0 0x10C21000 0x40000>;
> > +               };
> > +
> > +               /* GPIO_HSI1 */
> > +               pinctrl_6: pinctrl@11840000 {
> > +                       compatible = "google,gs101-pinctrl";
> > +                       reg = <0x0 0x11840000 0x00001000>;
> > +                       interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               /* GPIO_HSI2 */
> > +               pinctrl_7: pinctrl@14440000 {
> > +                       compatible = "google,gs101-pinctrl";
> > +                       reg = <0x0 0x14440000 0x00001000>;
> > +                       interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               cmu_apm: clock-controller@17400000 {
> > +                       compatible = "google,gs101-cmu-apm";
> > +                       reg = <0x0 0x17400000 0x8000>;
> > +                       #clock-cells = <1>;
> > +
> > +                       clocks = <&ext_24_5m>;
> > +                       clock-names = "oscclk";
> > +               };
> > +
> > +               sysreg_apm: syscon@174204e0 {
> > +                       compatible = "google,gs101-apm-sysreg", "syscon";
> > +                       reg = <0x0 0x174204e0 0x1000>;
> > +               };
>
> Sure it doesn't need any clock? I remember having some issues until I
> declared a clock for some Exynos850 sysreg node.

I deliberately left the clocks out for now. As APM has it's own
firmware, mailbox I want to get more information on which entity is
meant to be managing these clocks.

>
> > +
> > +               pmu_system_controller: system-controller@17460000 {
> > +                       compatible = "google,gs101-pmu", "syscon";
> > +                       reg = <0x0 0x17460000 0x10000>;
> > +               };
> > +
> > +               /* GPIO_ALIVE */
> > +               pinctrl_0: pinctrl@174d0000 {
> > +                       compatible = "google,gs101-pinctrl";
> > +                       reg = <0x0 0x174d0000 0x00001000>;
> > +                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
>
> Are you sure all those interrupts are actually needed? Please check
> this patch: daeb1c2b50fb ("arm64: dts: exynos: drop incorrectly placed
> wakeup interrupts in Exynos850"). If you decide to remove those
> interrupts, then bindings doc should be changed too I guess.

You were correct. fyi I fixed this in v4.

>
> > +
> > +                       wakeup-interrupt-controller {
> > +                               compatible = "google,gs101-wakeup-eint";
> > +                       };
> > +               };
> > +
> > +               /* GPIO_FAR_ALIVE */
> > +               pinctrl_1: pinctrl@174e0000 {
> > +                       compatible = "google,gs101-pinctrl";
> > +                       reg = <0x0 0x174e0000 0x00001000>;
> > +                       interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                       wakeup-interrupt-controller {
> > +                               compatible = "google,gs101-wakeup-eint";
> > +                       };
> > +               };
> > +
> > +               /* GPIO_GSACTRL */
> > +               pinctrl_3: pinctrl@17940000 {
> > +                       compatible = "google,gs101-pinctrl";
> > +                       reg = <0x0 0x17940000 0x00001000>;
> > +               };
> > +
> > +               /* GPIO_GSACORE */
> > +               pinctrl_2: pinctrl@17a80000 {
> > +                       compatible = "google,gs101-pinctrl";
> > +                       reg = <0x0 0x17a80000 0x00001000>;
> > +               };
> > +
> > +               cmu_top: clock-controller@1e080000 {
>
> Move it up to other cmus, to make nodes under soc ordered alphabetically?

The nodes under SoC are ordered by reg address, which IIRC was
requested in earlier review feedback.

regards,

Peter.

>
> > +                       compatible = "google,gs101-cmu-top";
> > +                       reg = <0x0 0x1e080000 0x8000>;
> > +                       #clock-cells = <1>;
> > +
> > +                       clocks = <&ext_24_5m>;
> > +                       clock-names = "oscclk";
> > +               };
> > +       };
> > +};
> > +
> > +#include "gs101-pinctrl.dtsi"
> > --
> > 2.42.0.655.g421f12c284-goog
> >

Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates

[Peter Griffin]

Hi Sam,

On Wed, 8 Nov 2023 at 17:33, Sam Protsenko <semen.protsenko@linaro.org> wrote:
>
> On Tue, Nov 7, 2023 at 7:57 AM Peter Griffin <peter.griffin@linaro.org> wrote:
> >
> > Hi Chanwoo,
> >
> > Thanks for your review!
> >
> > On Wed, 18 Oct 2023 at 17:51, Chanwoo Choi <chanwoo@kernel.org> wrote:
> > >
> > > Hi Peter,
> > >
> > > On 23. 10. 12. 03:48, Peter Griffin wrote:
> > > > CMU_TOP is the top level clock management unit which contains PLLs, muxes
> > > > and gates that feed the other clock management units.
> > > >
> > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > > > ---
> > > >  drivers/clk/samsung/Kconfig     |    9 +
> > > >  drivers/clk/samsung/Makefile    |    2 +
> > > >  drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++
> > > >  3 files changed, 1562 insertions(+)
> > > >  create mode 100644 drivers/clk/samsung/clk-gs101.c
> > > >
> > > > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> > > > index 76a494e95027..14362ec9c543 100644
> > > > --- a/drivers/clk/samsung/Kconfig
> > > > +++ b/drivers/clk/samsung/Kconfig
> > > > @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG
> > > >       select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
> > > >       select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> > > >       select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> > > > +     select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR
> > > >       select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> > > >
> > > >  config S3C64XX_COMMON_CLK
> > > > @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT
> > > >         status of the certains clocks from SoC, but it could also be tied to
> > > >         other devices as an input clock.
> > > >
> > > > +config GOOGLE_GS101_COMMON_CLK
> > > > +     bool "Google gs101 clock controller support" if COMPILE_TEST
> > > > +     depends on COMMON_CLK_SAMSUNG
> > > > +     depends on EXYNOS_ARM64_COMMON_CLK
> > > > +     help
> > > > +       Support for the clock controller present on the Google gs101 SoC.
> > > > +       Choose Y here only if you build for this SoC.
> > > > +
> > >
> > > (snip)
> > >
> > > > +
> > > > +/* gs101 */
> > > > +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
> > > > +     /* CMU_TOP_PURECLKCOMP */
> > > > +     MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> > > > +         PLL_CON0_PLL_SHARED0, 4, 1),
> > > > +     MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> > > > +         PLL_CON0_PLL_SHARED1, 4, 1),
> > > > +     MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> > > > +         PLL_CON0_PLL_SHARED2, 4, 1),
> > > > +     MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> > > > +         PLL_CON0_PLL_SHARED3, 4, 1),
> > > > +     MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p,
> > > > +         PLL_CON0_PLL_SPARE, 4, 1),
> > > > +
> > > > +     /* BUS0 */
> > > > +     MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
> > > > +     MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p,
> > >
> > > In order to keep the consistent naming style,
> > > I think that need to change from 'mout_cmu_boost' to 'mout_cmu_cmu_boost'.
> >
> > Yes, that's a good point, and a good spot! Will fix it in v4.
> >
>
> Why do we need cmu_cmu part at all? From the look of it, renaming all
> *_cmu_cmu_* clocks to just cmu wouldn't cause any naming conflicts. So
> I don't see any benefit of double cmu prefix really.

The benefit is consistency, as Chanwoo pointed out.

>
> > >
> > > > +         CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
> > > > +
> > > > +     /* BUS1 */
> > > > +     MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
> > > > +
> > > > +     /* BUS2 */
> > > > +     MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2),
> > > > +
> > > > +     /* CORE */
> > > > +     MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> > > > +
> > > > +     /* EH */
> > > > +     MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> > >
> > > 'mout_cmu_core_bus' and 'mout_cmu_eh_bus' uses the same register/shift/width information.
> > > I think it should be modified by changing the regiter or changing the shift/width information.
> >
> > It should be using the CLK_CON_MUX_MUX_CLKCMU_EH_BUS register.
> > Will fix it in v4.
> >
> > >
> > > > +
> > > > +     /* CPUCL{0,1,2,} */
> > > > +     MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2),
> > > > +
> > > > +     MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
> > > > +
> > > > +     MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
> > > > +
> > > > +     MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
> > > > +         CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2),
> > > > +
> > > > +     MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
> > > >
> > >
> > > (snip)
> > >
> > > > +     /* PDP */
> > > > +     MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2),
> > > > +
> > > > +     /* PDP */
> > > > +     MUX(CLK_MOUT_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 2),
> > > > +
> > > > +     /* IPP */
> > > > +     MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2),
> > > > +
> > > > +     /* G3AA */
> > > > +     MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p,
> > > > +         CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2),
> > >
> > > I think that need to change the mux name and mux parent name
> > > because other mux name use the twice word according to the register name
> > > even if use the same work such as 'mout_cmu_g2d_g2d', 'mout_cmu_mcsc_mcsc' and 'mout_cmu_mfc_mfc'.
> > > - mout_cmu_g3aa -> mout_cmu_g3aa_g3aa
> > > - mout_cmu_g3aa_p -> mount_cmu_g3aa_g3aa_p
> >
> > Will fix in v4
> >
>
> That consistent name duplication, while not causing any conflicts when
> being removed, looks suspicious to me. That's probably some internal
> scheme which doesn't make much sense for us and doesn't bring any
> value, in terms of clock drivers. Maybe it'll be better to instead get
> rid of such duplication throughout the driver, at least for clock name
> strings? I mention this, because that's what I did in clk-exynos850.
> With the only exception being the main domain clocks, which basically
> enables/disables the whole unit internally, e.g.
>
>     GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", ...
>
> which "G3D domain gate clock that enables/disables G3D", or something
> like that. But clk-exynos850 doesn't have any duplicating bits like
> "cmu_cmu" or "g3d_g3d". And the reason why I did that is I wanted
> those clock names appear short and nice in device tree, as there were
> no benefits in those duplicating bits.

I did start out doing something similar, but decided it was a bad
idea. The value of consistent naming and being able to more easily
cross reference and verify correctness with the TRM for me far
outweighs the advantage of having a shorter name. There are literally
thousands of clocks we need to expose in this SoC to have everything
fully modelled and having these various "exceptions" where we change
the naming scheme of the clock because of a duplicated word IMO isn't
helpful.

Peter


>
> > >
> > > (snip)
> > >
> > > > +     /* CSIS */
> > > > +     GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
> > > > +          CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
> > > > +     /* PDP */
> > > > +     GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
> > > > +          CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> > > > +
> > > > +     GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
> > > > +          CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
> > > > +
> > > > +     /* IPP */
> > > > +     GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
> > > > +          CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
> > > > +     /* G3AA */
> > > > +     GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa",
> > > > +          CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
> > >
> > > ditto.
> > > gout_cmu_g3aa -> gout_cmu_g3aa_g3aa
> > > mout_cmu_g3aa -> mout_cmu_g3aa_g3aa
> >
>
> Ditto.
>
> > Will fix in V4
> >
> > regards,
> >
> > Peter.