From: Arnd Bergmann <arnd@kernel.org> To: Misono Tomohiro <misono.tomohiro@jp.fujitsu.com> Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>, SoC Team <soc@kernel.org>, Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net> Subject: Re: [PATCH 01/10] soc: fujitsu: hwb: Add hardware barrier driver init/exit code Date: Fri, 8 Jan 2021 13:41:49 +0100 [thread overview] Message-ID: <CAK8P3a15PUC5Tu+FBuyZYtyQUC_bc92zVszYeFoCU6tn05jgMA@mail.gmail.com> (raw) In-Reply-To: <20210108103227.1740865-2-misono.tomohiro@jp.fujitsu.com> On Fri, Jan 8, 2021 at 11:32 AM Misono Tomohiro <misono.tomohiro@jp.fujitsu.com> wrote: > + * > + * This hardware barrier (HWB) driver provides a set of ioctls to realize synchronization > + * by PEs in the same Come Memory Group (CMG) by using implementation defined registers. > + * On A64FX, CMG is the same as L3 cache domain. > + * > + * The main purpose of the driver is setting up registers which cannot be accessed > + * from EL0. However, after initialization, BST_SYNC/LBSY_SYNC registers which is used > + * in synchronization main logic can be accessed from EL0 (therefore it is fast). > + * > + * Simplified barrier operation flow of user application is as follows: > + * (one PE) > + * 1. Call IOC_BB_ALLOC to setup INIT_SYNC register which is shared in a CMG. > + * This specifies which PEs join synchronization > + * (on each PE joining synchronization) > + * 2. Call IOC_BW_ASSIGN to setup ASSIGN_SYNC register per PE > + * 3. Barrier main logic (all logic runs in EL0) > + * a) Write 1 to BST_SYNC register > + * b) Read LBSY_SYNC register > + * c) If LBSY_SYNC value is 1, sync is finished, otherwise go back to b > + * (If all PEs joining synchronization write 1 to BST_SYNC, LBSY_SYNC becomes 1) > + * 4. Call IOC_BW_UNASSIGN to reset ASSIGN_SYNC register > + * (one PE) > + * 5. Call IOC_BB_FREE to reset INIT_SYNC register > + */ On a very general note, I would like to see some background about how specific this functionality is to the specific design of A64fx. If there are other processors with a similar requirement, then it would be best to define a more abstract user API that can work for any such product. > +static int __init hwb_init(void) > +{ > + int ret; > + > + ret = setup_hwinfo(); > + if (ret < 0) { > + pr_err("Unsupported CPU type\n"); > + return ret; > + } Loading the module on a different machine should not print a warning: In general, we want it to be possible to have all hardware specific drivers built into the kernel, but not print any irritating messages when they are simply not used on the hardware. One way to avoid this would be to use a platform_driver() that only gets loaded when a corresponding hardware device of some sort is found, or ignored otherwise. Arnd
WARNING: multiple messages have this Message-ID (diff)
From: Arnd Bergmann <arnd@kernel.org> To: Misono Tomohiro <misono.tomohiro@jp.fujitsu.com> Cc: Arnd Bergmann <arnd@arndb.de>, Catalin Marinas <catalin.marinas@arm.com>, SoC Team <soc@kernel.org>, Olof Johansson <olof@lixom.net>, Will Deacon <will@kernel.org>, Linux ARM <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH 01/10] soc: fujitsu: hwb: Add hardware barrier driver init/exit code Date: Fri, 8 Jan 2021 13:41:49 +0100 [thread overview] Message-ID: <CAK8P3a15PUC5Tu+FBuyZYtyQUC_bc92zVszYeFoCU6tn05jgMA@mail.gmail.com> (raw) Message-ID: <20210108124149.P30VduChn6Rnq5O6uGgzLrN4yqabMqnhTdWhyGYQzH0@z> (raw) In-Reply-To: <20210108103227.1740865-2-misono.tomohiro@jp.fujitsu.com> On Fri, Jan 8, 2021 at 11:32 AM Misono Tomohiro <misono.tomohiro@jp.fujitsu.com> wrote: > + * > + * This hardware barrier (HWB) driver provides a set of ioctls to realize synchronization > + * by PEs in the same Come Memory Group (CMG) by using implementation defined registers. > + * On A64FX, CMG is the same as L3 cache domain. > + * > + * The main purpose of the driver is setting up registers which cannot be accessed > + * from EL0. However, after initialization, BST_SYNC/LBSY_SYNC registers which is used > + * in synchronization main logic can be accessed from EL0 (therefore it is fast). > + * > + * Simplified barrier operation flow of user application is as follows: > + * (one PE) > + * 1. Call IOC_BB_ALLOC to setup INIT_SYNC register which is shared in a CMG. > + * This specifies which PEs join synchronization > + * (on each PE joining synchronization) > + * 2. Call IOC_BW_ASSIGN to setup ASSIGN_SYNC register per PE > + * 3. Barrier main logic (all logic runs in EL0) > + * a) Write 1 to BST_SYNC register > + * b) Read LBSY_SYNC register > + * c) If LBSY_SYNC value is 1, sync is finished, otherwise go back to b > + * (If all PEs joining synchronization write 1 to BST_SYNC, LBSY_SYNC becomes 1) > + * 4. Call IOC_BW_UNASSIGN to reset ASSIGN_SYNC register > + * (one PE) > + * 5. Call IOC_BB_FREE to reset INIT_SYNC register > + */ On a very general note, I would like to see some background about how specific this functionality is to the specific design of A64fx. If there are other processors with a similar requirement, then it would be best to define a more abstract user API that can work for any such product. > +static int __init hwb_init(void) > +{ > + int ret; > + > + ret = setup_hwinfo(); > + if (ret < 0) { > + pr_err("Unsupported CPU type\n"); > + return ret; > + } Loading the module on a different machine should not print a warning: In general, we want it to be possible to have all hardware specific drivers built into the kernel, but not print any irritating messages when they are simply not used on the hardware. One way to avoid this would be to use a platform_driver() that only gets loaded when a corresponding hardware device of some sort is found, or ignored otherwise. Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-08 12:42 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-08 10:32 Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 01/10] soc: fujitsu: hwb: Add hardware barrier driver init/exit code Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 11:58 ` Jonathan Cameron 2021-01-08 11:58 ` Jonathan Cameron 2021-01-12 10:35 ` misono.tomohiro 2021-01-12 10:35 ` misono.tomohiro 2021-01-08 12:41 ` Arnd Bergmann [this message] 2021-01-08 12:41 ` Arnd Bergmann 2021-01-12 10:49 ` misono.tomohiro 2021-01-12 10:49 ` misono.tomohiro 2021-01-08 10:32 ` [PATCH 02/10] soc: fujtisu: hwb: Add open operation Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 03/10] soc: fujitsu: hwb: Add IOC_BB_ALLOC ioctl Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 04/10] soc: fujitsu: hwb: Add IOC_BW_ASSIGN ioctl Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 05/10] soc: fujitsu: hwb: Add IOC_BW_UNASSIGN ioctl Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 06/10] soc: fujitsu: hwb: Add IOC_BB_FREE ioctl Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 07/10] soc: fujitsu: hwb: Add IOC_GET_PE_INFO ioctl Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 08/10] soc: fujitsu: hwb: Add release operation Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 09/10] soc: fujitsu: hwb: Add sysfs entry Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 10:32 ` [PATCH 10/10] soc: fujitsu: hwb: Add Kconfig/Makefile to build fujitsu_hwb driver Misono Tomohiro 2021-01-08 10:32 ` Misono Tomohiro 2021-01-08 12:30 ` Arnd Bergmann 2021-01-08 12:30 ` Re: Arnd Bergmann 2021-01-08 10:52 [RFC PATCH 00/10] Add Fujitsu A64FX soc entry/hardware barrier driver Misono Tomohiro 2021-01-08 10:52 ` [PATCH 01/10] soc: fujitsu: hwb: Add hardware barrier driver init/exit code Misono Tomohiro 2021-01-08 10:52 ` Misono Tomohiro
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