[GIT PULL] RISC-V Devicetrees for v6.3

* [GIT PULL] RISC-V Devicetrees for v6.3
@ 2023-01-26 19:09 Conor Dooley
  2023-01-30 22:31 ` patchwork-bot+linux-soc
  0 siblings, 1 reply; 2+ messages in thread
From: Conor Dooley @ 2023-01-26 19:09 UTC (permalink / raw)
  To: arnd; +Cc: conor, palmer, linux-riscv, soc

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Hey Arnd,

DT stuff here for v6.3! I was kinda hoping to have a VisionFive 2 DT
for you, but alas no.
The changelog looks a bit odd since it's filled with un-reviewed
commits of my own, but they went as a PR to Palmer & are in riscv's
for-next too:
https://lore.kernel.org/all/167225428483.14530.3368527680488639805.b4-ty@rivosinc.com/
They might also pop up as part of the Allwinner DT PR, if the D1 stuff
lands for v6.3, which I hope does happen!

Thanks,
Conor.

The following changes since commit 1b929c02afd37871d5afb9d498426f83432e71c2:

  Linux 6.2-rc1 (2022-12-25 13:41:39 -0800)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-for-v6.3-mw0

for you to fetch changes up to d9c36d016f6112e636f18a49a5f779c7f8667deb:

  Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM" (2023-01-25 11:09:32 +0000)

----------------------------------------------------------------
RISC-V Devicetrees for v6.3-mw0

Microchip:
A vendor prefix for Aldec and both a binding and Devicetree for the
Aldec TySoM devkit for PolarFire SoC. This Devicetree corresponds to
what they are shipping in the SDK for rev2 boards.

StarFive:
Just the binding for the new StarFive JH7110 SoC and its first-party
SDC the VisionFive 2.

Other:
I was expecting the Devicetree for the aforementioned board to be ready
for this window, as the pinctrl driver had seem some review prior to
v6.2 and both it & the base clock drivers are heavily based on the
existing drivers for the JH7110.
That didn't come to be.. Christmas, the RISC-V Summit in December and
the Lunar New Year all playing a part perhaps.
Because of that, both Palmer and I have the Kconfig.socs work in our
branches, although in hindsight it probably wasn't needed here as I
only added the TySoM Devicetree & the conflict would've been trivial.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Conor Dooley (11):
      RISC-V: introduce ARCH_FOO kconfig aliases for SOC_FOO symbols
      RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN
      RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO
      RISC-V: stop selecting the PolarFire SoC clock driver
      RISC-V: stop selecting SiFive clock and serial drivers directly
      RISC-V: stop directly selecting drivers for SOC_CANAAN
      Merge tag 'soc2arch-immutable' into riscv-dt-for-next
      dt-bindings: vendor-prefixes: Add entry for Aldec
      dt-bindings: riscv: microchip: document the Aldec TySoM
      riscv: dts: microchip: add the Aldec TySoM's devicetree
      Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"

Emil Renner Berthing (1):
      dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board

 .../devicetree/bindings/riscv/microchip.yaml       |   1 +
 .../devicetree/bindings/riscv/starfive.yaml        |   6 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/riscv/Kconfig.socs                            |  39 +++--
 arch/riscv/Makefile                                |   2 +-
 arch/riscv/boot/dts/Makefile                       |   2 +-
 arch/riscv/boot/dts/canaan/Makefile                |  14 +-
 arch/riscv/boot/dts/microchip/Makefile             |   9 +-
 .../boot/dts/microchip/mpfs-tysom-m-fabric.dtsi    |  18 +++
 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts     | 165 +++++++++++++++++++++
 arch/riscv/boot/dts/sifive/Makefile                |   4 +-
 arch/riscv/boot/dts/starfive/Makefile              |   2 +-
 12 files changed, 235 insertions(+), 29 deletions(-)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts

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