* [PATCH v1 1/5] dmaengine: dw: Fix FIFO size for Intel Merrifield
@ 2018-11-30 20:36 Andy Shevchenko
2018-11-30 20:36 ` [PATCH v1 2/5] dmaengine: dw: Add missed multi-block support for iDMA 32-bit Andy Shevchenko
2018-12-04 17:03 ` [PATCH v1 1/5] dmaengine: dw: Fix FIFO size for Intel Merrifield Andy Shevchenko
0 siblings, 2 replies; 3+ messages in thread
From: Andy Shevchenko @ 2018-11-30 20:36 UTC (permalink / raw)
To: Viresh Kumar, dmaengine, Vinod Koul; +Cc: Andy Shevchenko, stable
Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller,
i.e. 512 bytes instead of 1024.
Fix this by partitioning it as 64 bytes per channel.
Note, in the future we might switch to 'fifo-size' property instead of
hard coded value.
Fixes: 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: stable@vger.kernel.org
---
drivers/dma/dw/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index d0c3e50b39fb..e85b078fc207 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1059,12 +1059,12 @@ static void dwc_issue_pending(struct dma_chan *chan)
/*
* Program FIFO size of channels.
*
- * By default full FIFO (1024 bytes) is assigned to channel 0. Here we
+ * By default full FIFO (512 bytes) is assigned to channel 0. Here we
* slice FIFO on equal parts between channels.
*/
static void idma32_fifo_partition(struct dw_dma *dw)
{
- u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) |
+ u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
IDMA32C_FP_UPDATE;
u64 fifo_partition = 0;
--
2.19.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v1 2/5] dmaengine: dw: Add missed multi-block support for iDMA 32-bit
2018-11-30 20:36 [PATCH v1 1/5] dmaengine: dw: Fix FIFO size for Intel Merrifield Andy Shevchenko
@ 2018-11-30 20:36 ` Andy Shevchenko
2018-12-04 17:03 ` [PATCH v1 1/5] dmaengine: dw: Fix FIFO size for Intel Merrifield Andy Shevchenko
1 sibling, 0 replies; 3+ messages in thread
From: Andy Shevchenko @ 2018-11-30 20:36 UTC (permalink / raw)
To: Viresh Kumar, dmaengine, Vinod Koul; +Cc: Andy Shevchenko, stable
Intel integrated DMA 32-bit support multi-block transfers.
Add missed setting to the platform data.
Fixes: f7c799e950f9 ("dmaengine: dw: we do support Merrifield SoC in PCI mode")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: stable@vger.kernel.org
---
drivers/dma/dw/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/dw/pci.c b/drivers/dma/dw/pci.c
index 7778ed705a1a..61f2274f6dd4 100644
--- a/drivers/dma/dw/pci.c
+++ b/drivers/dma/dw/pci.c
@@ -25,6 +25,7 @@ static struct dw_dma_platform_data mrfld_pdata = {
.block_size = 131071,
.nr_masters = 1,
.data_width = {4},
+ .multi_block = {true, true, true, true, true, true, true, true},
};
static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
--
2.19.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v1 1/5] dmaengine: dw: Fix FIFO size for Intel Merrifield
2018-11-30 20:36 [PATCH v1 1/5] dmaengine: dw: Fix FIFO size for Intel Merrifield Andy Shevchenko
2018-11-30 20:36 ` [PATCH v1 2/5] dmaengine: dw: Add missed multi-block support for iDMA 32-bit Andy Shevchenko
@ 2018-12-04 17:03 ` Andy Shevchenko
1 sibling, 0 replies; 3+ messages in thread
From: Andy Shevchenko @ 2018-12-04 17:03 UTC (permalink / raw)
To: Viresh Kumar, dmaengine, Vinod Koul; +Cc: stable
On Fri, Nov 30, 2018 at 10:36:42PM +0200, Andy Shevchenko wrote:
> Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller,
> i.e. 512 bytes instead of 1024.
>
> Fix this by partitioning it as 64 bytes per channel.
>
> Note, in the future we might switch to 'fifo-size' property instead of
> hard coded value.
v2 of the series is coming soon this week, so, don't consider this one.
>
> Fixes: 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: stable@vger.kernel.org
> ---
> drivers/dma/dw/core.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> index d0c3e50b39fb..e85b078fc207 100644
> --- a/drivers/dma/dw/core.c
> +++ b/drivers/dma/dw/core.c
> @@ -1059,12 +1059,12 @@ static void dwc_issue_pending(struct dma_chan *chan)
> /*
> * Program FIFO size of channels.
> *
> - * By default full FIFO (1024 bytes) is assigned to channel 0. Here we
> + * By default full FIFO (512 bytes) is assigned to channel 0. Here we
> * slice FIFO on equal parts between channels.
> */
> static void idma32_fifo_partition(struct dw_dma *dw)
> {
> - u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) |
> + u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
> IDMA32C_FP_UPDATE;
> u64 fifo_partition = 0;
>
> --
> 2.19.2
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 3+ messages in thread
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