* [PATCH v2 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB [not found] <20190903052407.16638-1-alastair@au1.ibm.com> @ 2019-09-03 5:23 ` Alastair D'Silva 2019-09-14 7:46 ` Christophe Leroy 0 siblings, 1 reply; 3+ messages in thread From: Alastair D'Silva @ 2019-09-03 5:23 UTC (permalink / raw) To: alastair Cc: stable, Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, Christophe Leroy, Greg Kroah-Hartman, Thomas Gleixner, Qian Cai, Nicholas Piggin, Allison Randal, Andrew Morton, Mike Rapoport, Michal Hocko, David Hildenbrand, linuxppc-dev, linux-kernel From: Alastair D'Silva <alastair@d-silva.org> When calling flush_icache_range with a size >4GB, we were masking off the upper 32 bits, so we would incorrectly flush a range smaller than intended. This patch replaces the 32 bit shifts with 64 bit ones, so that the full size is accounted for. Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Cc: stable@vger.kernel.org --- arch/powerpc/kernel/misc_64.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index b55a7b4cb543..9bc0aa9aeb65 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */ - srw. r8,r8,r9 /* compute line count */ + srd. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 1: dcbst 0,r6 @@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) subf r8,r6,r4 /* compute length */ add r8,r8,r5 lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */ - srw. r8,r8,r9 /* compute line count */ + srd. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 2: icbi 0,r6 -- 2.21.0 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB 2019-09-03 5:23 ` [PATCH v2 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB Alastair D'Silva @ 2019-09-14 7:46 ` Christophe Leroy 2019-09-16 3:25 ` Alastair D'Silva 0 siblings, 1 reply; 3+ messages in thread From: Christophe Leroy @ 2019-09-14 7:46 UTC (permalink / raw) To: Alastair D'Silva, alastair Cc: stable, Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, Greg Kroah-Hartman, Thomas Gleixner, Qian Cai, Nicholas Piggin, Allison Randal, Andrew Morton, Mike Rapoport, Michal Hocko, David Hildenbrand, linuxppc-dev, linux-kernel Le 03/09/2019 à 07:23, Alastair D'Silva a écrit : > From: Alastair D'Silva <alastair@d-silva.org> > > When calling flush_icache_range with a size >4GB, we were masking > off the upper 32 bits, so we would incorrectly flush a range smaller > than intended. > > This patch replaces the 32 bit shifts with 64 bit ones, so that > the full size is accounted for. Isn't there the same issue in arch/powerpc/kernel/vdso64/cacheflush.S ? Christophe > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > Cc: stable@vger.kernel.org > --- > arch/powerpc/kernel/misc_64.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S > index b55a7b4cb543..9bc0aa9aeb65 100644 > --- a/arch/powerpc/kernel/misc_64.S > +++ b/arch/powerpc/kernel/misc_64.S > @@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) > subf r8,r6,r4 /* compute length */ > add r8,r8,r5 /* ensure we get enough */ > lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */ > - srw. r8,r8,r9 /* compute line count */ > + srd. r8,r8,r9 /* compute line count */ > beqlr /* nothing to do? */ > mtctr r8 > 1: dcbst 0,r6 > @@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) > subf r8,r6,r4 /* compute length */ > add r8,r8,r5 > lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */ > - srw. r8,r8,r9 /* compute line count */ > + srd. r8,r8,r9 /* compute line count */ > beqlr /* nothing to do? */ > mtctr r8 > 2: icbi 0,r6 > ^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v2 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB 2019-09-14 7:46 ` Christophe Leroy @ 2019-09-16 3:25 ` Alastair D'Silva 0 siblings, 0 replies; 3+ messages in thread From: Alastair D'Silva @ 2019-09-16 3:25 UTC (permalink / raw) To: Christophe Leroy Cc: stable, Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, Greg Kroah-Hartman, Thomas Gleixner, Qian Cai, Nicholas Piggin, Allison Randal, Andrew Morton, Mike Rapoport, Michal Hocko, David Hildenbrand, linuxppc-dev, linux-kernel On Sat, 2019-09-14 at 09:46 +0200, Christophe Leroy wrote: > > Le 03/09/2019 à 07:23, Alastair D'Silva a écrit : > > From: Alastair D'Silva <alastair@d-silva.org> > > > > When calling flush_icache_range with a size >4GB, we were masking > > off the upper 32 bits, so we would incorrectly flush a range > > smaller > > than intended. > > > > This patch replaces the 32 bit shifts with 64 bit ones, so that > > the full size is accounted for. > > Isn't there the same issue in arch/powerpc/kernel/vdso64/cacheflush.S > ? > > Christophe Yes, there is. I'll fix it, but I wonder whether anything calls it? I asked Google, and every mention of it was in the kernel source or mailing list. Maybe BenH can chime in? -- Alastair D'Silva Open Source Developer Linux Technology Centre, IBM Australia mob: 0423 762 819 ^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-09-03 5:23 ` [PATCH v2 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB Alastair D'Silva
2019-09-14 7:46 ` Christophe Leroy
2019-09-16 3:25 ` Alastair D'Silva
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