* [PATCH v5 04/11] PCI: qcom: Add missing reset for ipq806x
[not found] <20200602115353.20143-1-ansuelsmth@gmail.com>
@ 2020-06-02 11:53 ` Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 08/11] PCI: qcom: Add support for tx term offset for rev 2.1.0 Ansuel Smith
2 siblings, 0 replies; 5+ messages in thread
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Sham Muthayyan, stable, Rob Herring, Philipp Zabel,
Andy Gross, Bjorn Andersson, Bjorn Helgaas, Mark Rutland,
Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
linux-arm-msm, linux-pci, devicetree, linux-kernel
Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4512c2c5f61c..4dab5ef630cc 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *ahb_reset;
struct reset_control *por_reset;
struct reset_control *phy_reset;
+ struct reset_control *ext_reset;
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
};
@@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->por_reset))
return PTR_ERR(res->por_reset);
+ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
+
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
@@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
+ reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
@@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_deassert_ahb;
}
+ ret = reset_control_deassert(res->ext_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert ext reset\n");
+ goto err_deassert_ahb;
+ }
+
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
val &= ~BIT(0);
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC
[not found] <20200602115353.20143-1-ansuelsmth@gmail.com>
2020-06-02 11:53 ` [PATCH v5 04/11] PCI: qcom: Add missing reset for ipq806x Ansuel Smith
@ 2020-06-02 11:53 ` Ansuel Smith
2020-06-05 14:10 ` Sasha Levin
2020-06-06 16:30 ` Stanimir Varbanov
2020-06-02 11:53 ` [PATCH v5 08/11] PCI: qcom: Add support for tx term offset for rev 2.1.0 Ansuel Smith
2 siblings, 2 replies; 5+ messages in thread
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, stable, Rob Herring, Andy Gross, Bjorn Andersson,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov,
Lorenzo Pieralisi, Andrew Murray, Philipp Zabel, linux-arm-msm,
linux-pci, devicetree, linux-kernel
Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
needed on some ipq8064 based device (Netgear R7800 for example). Without
this the system locks on kernel load.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f2ea1ab6f584..f5398b0d270c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -46,6 +46,9 @@
#define PCIE20_PARF_PHY_CTRL 0x40
#define PCIE20_PARF_PHY_REFCLK 0x4C
+#define PHY_REFCLK_SSP_EN BIT(16)
+#define PHY_REFCLK_USE_PAD BIT(12)
+
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
@@ -77,6 +80,18 @@
#define DBI_RO_WR_EN 1
#define PERST_DELAY_US 1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH 0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
+
+#define PCIE20_PARF_PCS_SWING 0x38
+#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
+#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
+
+#define PCIE20_PARF_CONFIG_BITS 0x50
+#define PHY_RX0_EQ(x) ((x) << 24)
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
@@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ struct device_node *node = dev->of_node;
u32 val;
int ret;
@@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
val &= ~BIT(0);
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
+ writel(PCS_SWING_TX_SWING_FULL(120) |
+ PCS_SWING_TX_SWING_LOW(120),
+ pcie->parf + PCIE20_PARF_PCS_SWING);
+ writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
+ }
+
/* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
val |= BIT(16);
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v5 08/11] PCI: qcom: Add support for tx term offset for rev 2.1.0
[not found] <20200602115353.20143-1-ansuelsmth@gmail.com>
2020-06-02 11:53 ` [PATCH v5 04/11] PCI: qcom: Add missing reset for ipq806x Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC Ansuel Smith
@ 2020-06-02 11:53 ` Ansuel Smith
2 siblings, 0 replies; 5+ messages in thread
From: Ansuel Smith @ 2020-06-02 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Ansuel Smith, Sham Muthayyan, stable, Andy Gross,
Bjorn Andersson, Bjorn Helgaas, Mark Rutland, Stanimir Varbanov,
Lorenzo Pieralisi, Andrew Murray, Philipp Zabel, linux-arm-msm,
linux-pci, devicetree, linux-kernel
Add tx term offset support to pcie qcom driver need in some revision of
the ipq806x SoC. Ipq8064 needs tx term offset set to 7.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
---
drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f5398b0d270c..2cd6d1456210 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -45,6 +45,9 @@
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
#define PCIE20_PARF_PHY_CTRL 0x40
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
+
#define PCIE20_PARF_PHY_REFCLK 0x4C
#define PHY_REFCLK_SSP_EN BIT(16)
#define PHY_REFCLK_USE_PAD BIT(12)
@@ -374,9 +377,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
}
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ /* set TX termination offset */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
+ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ }
+
/* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- val |= BIT(16);
+ val &= ~PHY_REFCLK_USE_PAD;
+ val |= PHY_REFCLK_SSP_EN;
writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
/* wait for clock acquisition */
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC
2020-06-02 11:53 ` [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC Ansuel Smith
@ 2020-06-05 14:10 ` Sasha Levin
2020-06-06 16:30 ` Stanimir Varbanov
1 sibling, 0 replies; 5+ messages in thread
From: Sasha Levin @ 2020-06-05 14:10 UTC (permalink / raw)
To: Sasha Levin, Ansuel Smith, Rob Herring; +Cc: Ansuel Smith, stable, stable
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver").
The bot has tested the following trees: v5.6.15, v5.4.43, v4.19.125, v4.14.182, v4.9.225.
v5.6.15: Build OK!
v5.4.43: Build OK!
v4.19.125: Build OK!
v4.14.182: Failed to apply! Possible dependencies:
Unable to calculate
v4.9.225: Failed to apply! Possible dependencies:
19ce01cc8cbc ("PCI: dwc: all: Rename cfg_read/cfg_write to read/write")
1d77040bde2d ("PCI: layerscape: Add LS1046a support")
1f6c4501c667 ("PCI: dra7xx: Group PHY API invocations")
40f67fb2c384 ("PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()")
442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures")
9bcf0a6fdc50 ("PCI: dwc: all: Use platform_set_drvdata() to save private data")
ab5fe4f4d31e ("PCI: dra7xx: Add support to force RC to work in GEN1 mode")
ad719956a848 ("PCI: hisi: Remove redundant error message from hisi_pcie_probe()")
e594233803aa ("PCI: layerscape: Remove redundant error message from ls_pcie_probe()")
ebe85a44aad4 ("PCI: dra7xx: Enable MSI and legacy interrupts simultaneously")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC
2020-06-02 11:53 ` [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC Ansuel Smith
2020-06-05 14:10 ` Sasha Levin
@ 2020-06-06 16:30 ` Stanimir Varbanov
1 sibling, 0 replies; 5+ messages in thread
From: Stanimir Varbanov @ 2020-06-06 16:30 UTC (permalink / raw)
To: Ansuel Smith, Rob Herring
Cc: stable, Rob Herring, Andy Gross, Bjorn Andersson, Bjorn Helgaas,
Mark Rutland, Lorenzo Pieralisi, Andrew Murray, Philipp Zabel,
linux-arm-msm, linux-pci, devicetree, linux-kernel
Hi,
On 6/2/20 2:53 PM, Ansuel Smith wrote:
> Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
> needed on some ipq8064 based device (Netgear R7800 for example). Without
> this the system locks on kernel load.
>
> Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Cc: stable@vger.kernel.org # v4.5+
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index f2ea1ab6f584..f5398b0d270c 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -46,6 +46,9 @@
>
> #define PCIE20_PARF_PHY_CTRL 0x40
> #define PCIE20_PARF_PHY_REFCLK 0x4C
> +#define PHY_REFCLK_SSP_EN BIT(16)
> +#define PHY_REFCLK_USE_PAD BIT(12)
These two are not used in the patch, please move it in 08/11.
> +
> #define PCIE20_PARF_DBI_BASE_ADDR 0x168
> #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
> #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
> @@ -77,6 +80,18 @@
> #define DBI_RO_WR_EN 1
>
> #define PERST_DELAY_US 1000
> +/* PARF registers */
> +#define PCIE20_PARF_PCS_DEEMPH 0x34
> +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
> +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
> +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
> +
> +#define PCIE20_PARF_PCS_SWING 0x38
> +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
> +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
> +
> +#define PCIE20_PARF_CONFIG_BITS 0x50
> +#define PHY_RX0_EQ(x) ((x) << 24)
>
> #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> #define SLV_ADDR_SPACE_SZ 0x10000000
> @@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
> struct dw_pcie *pci = pcie->pci;
> struct device *dev = pci->dev;
> + struct device_node *node = dev->of_node;
> u32 val;
> int ret;
>
> @@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> val &= ~BIT(0);
> writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>
> + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
> + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
> + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
> + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
> + pcie->parf + PCIE20_PARF_PCS_DEEMPH);
> + writel(PCS_SWING_TX_SWING_FULL(120) |
> + PCS_SWING_TX_SWING_LOW(120),
> + pcie->parf + PCIE20_PARF_PCS_SWING);
Please fix the indentations above.
> + writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
> + }
> +
> /* enable external reference clock */
> val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
> val |= BIT(16);
>
--
regards,
Stan
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-06-06 16:30 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <20200602115353.20143-1-ansuelsmth@gmail.com>
2020-06-02 11:53 ` [PATCH v5 04/11] PCI: qcom: Add missing reset for ipq806x Ansuel Smith
2020-06-02 11:53 ` [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC Ansuel Smith
2020-06-05 14:10 ` Sasha Levin
2020-06-06 16:30 ` Stanimir Varbanov
2020-06-02 11:53 ` [PATCH v5 08/11] PCI: qcom: Add support for tx term offset for rev 2.1.0 Ansuel Smith
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