* [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states
@ 2021-08-26 1:09 Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 2/4] drm/amd/display: Update bounding box states (v2) Aurabindo Pillai
2021-08-26 2:00 ` [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Alex Deucher
0 siblings, 2 replies; 4+ messages in thread
From: Aurabindo Pillai @ 2021-08-26 1:09 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, nicholas.kazlauskas, alexander.deucher,
aurabindo.pillai, stable
[Why & How]
The DCN3 SoC parameter num_states was calculated but not saved into the
object.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 1333f0541f1b..43ac6f42dd80 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
+ dcn3_0_soc.num_states = num_states;
for (i = 0; i < dcn3_0_soc.num_states; i++) {
dcn3_0_soc.clock_limits[i].state = i;
dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/4] drm/amd/display: Update bounding box states (v2)
2021-08-26 1:09 [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Aurabindo Pillai
@ 2021-08-26 1:10 ` Aurabindo Pillai
2021-08-26 2:00 ` [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Alex Deucher
1 sibling, 0 replies; 4+ messages in thread
From: Aurabindo Pillai @ 2021-08-26 1:10 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, nicholas.kazlauskas, alexander.deucher,
aurabindo.pillai, Jerry (Fangzhi) Zuo, stable
From: "Jerry (Fangzhi) Zuo" <Jerry.Zuo@amd.com>
[Why]
Drop hardcoded dispclk, dppclk, phyclk
[How]
Read the corresponding values from clock table entries already populated.
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: stable@vger.kernel.org
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 41 ++++++++++++++-----
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 43ac6f42dd80..3d2443328345 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2398,16 +2398,37 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
if (bw_params->clk_table.entries[0].memclk_mhz) {
+ int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+
+ for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
+ if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
+ max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+ if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
+ max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
+ if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
+ max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
+ if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
+ max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
+ }
+
+ if (!max_dcfclk_mhz)
+ max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;
+ if (!max_dispclk_mhz)
+ max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz;
+ if (!max_dppclk_mhz)
+ max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz;
+ if (!max_phyclk_mhz)
+ max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz;
- if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+ if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
- dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz;
+ dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
num_dcfclk_sta_targets++;
- } else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+ } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
for (i = 0; i < num_dcfclk_sta_targets; i++) {
- if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) {
- dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz;
+ if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
+ dcfclk_sta_targets[i] = max_dcfclk_mhz;
break;
}
}
@@ -2447,7 +2468,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
} else {
- if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
+ if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} else {
@@ -2462,7 +2483,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
}
while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
- optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
+ optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
@@ -2475,9 +2496,9 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
/* Fill all states with max values of all other clocks */
- dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz;
- dcn3_0_soc.clock_limits[i].dppclk_mhz = bw_params->clk_table.entries[1].dppclk_mhz;
- dcn3_0_soc.clock_limits[i].phyclk_mhz = bw_params->clk_table.entries[1].phyclk_mhz;
+ dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
+ dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
+ dcn3_0_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
/* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states
2021-08-26 1:09 [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 2/4] drm/amd/display: Update bounding box states (v2) Aurabindo Pillai
@ 2021-08-26 2:00 ` Alex Deucher
2021-08-26 13:34 ` Aurabindo Pillai
1 sibling, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2021-08-26 2:00 UTC (permalink / raw)
To: Aurabindo Pillai
Cc: amd-gfx list, Wentland, Harry, Kazlauskas, Nicholas, Deucher,
Alexander, for 3.8
On Wed, Aug 25, 2021 at 9:10 PM Aurabindo Pillai
<aurabindo.pillai@amd.com> wrote:
>
> [Why & How]
> The DCN3 SoC parameter num_states was calculated but not saved into the
> object.
>
> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Cc: stable@vger.kernel.org
Please add:
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
to the series. With that fixed, series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> index 1333f0541f1b..43ac6f42dd80 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> @@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
> dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
> }
>
> + dcn3_0_soc.num_states = num_states;
> for (i = 0; i < dcn3_0_soc.num_states; i++) {
> dcn3_0_soc.clock_limits[i].state = i;
> dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states
2021-08-26 2:00 ` [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Alex Deucher
@ 2021-08-26 13:34 ` Aurabindo Pillai
0 siblings, 0 replies; 4+ messages in thread
From: Aurabindo Pillai @ 2021-08-26 13:34 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx list, Wentland, Harry, Kazlauskas, Nicholas, Deucher,
Alexander, for 3.8
Bug info added and applied, thanks!
On 8/25/21 10:00 PM, Alex Deucher wrote:
> On Wed, Aug 25, 2021 at 9:10 PM Aurabindo Pillai
> <aurabindo.pillai@amd.com> wrote:
>>
>> [Why & How]
>> The DCN3 SoC parameter num_states was calculated but not saved into the
>> object.
>>
>> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
>> Cc: stable@vger.kernel.org
>
> Please add:
> Bug: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1403&data=04%7C01%7Caurabindo.pillai%40amd.com%7C13083d4cd17f491b251608d968355aa9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637655400644887757%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=5OBOO0C%2FszESMd5QEjmRKKRsOM4KiMKFNWz6IdLOipM%3D&reserved=0
> to the series. With that fixed, series is:
> Acked-by: Alex Deucher <alexander.deucher@amd.com>zz
>
>> ---
>> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> index 1333f0541f1b..43ac6f42dd80 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> @@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
>> dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
>> }
>>
>> + dcn3_0_soc.num_states = num_states;
>> for (i = 0; i < dcn3_0_soc.num_states; i++) {
>> dcn3_0_soc.clock_limits[i].state = i;
>> dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
>> --
>> 2.30.2
>>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2021-08-26 1:09 [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 2/4] drm/amd/display: Update bounding box states (v2) Aurabindo Pillai
2021-08-26 2:00 ` [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Alex Deucher
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