* [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs
2021-06-04 5:51 [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
@ 2021-06-04 5:51 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8768@ATCPCS12.andestech.com>
2021-06-15 15:58 ` Leo Liang
2021-06-04 5:51 ` [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes Bin Meng
` (5 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Bin Meng @ 2021-06-04 5:51 UTC (permalink / raw)
To: Rick Chen, Leo, U-Boot Mailing List
There are two spaces before "debug' in bootargs. Drop one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/ae350_32.dts | 2 +-
arch/riscv/dts/ae350_64.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index ef110c54ae..b90351e87b 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -16,7 +16,7 @@
};
chosen {
- bootargs = "console=ttyS0,38400n8 debug loglevel=7";
+ bootargs = "console=ttyS0,38400n8 debug loglevel=7";
stdout-path = "uart0:38400n8";
};
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 6abf42e904..27ac21c716 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -16,7 +16,7 @@
};
chosen {
- bootargs = "console=ttyS0,38400n8 debug loglevel=7";
+ bootargs = "console=ttyS0,38400n8 debug loglevel=7";
stdout-path = "uart0:38400n8";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
[parent not found: <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8768@ATCPCS12.andestech.com>]
* Re: [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8768@ATCPCS12.andestech.com>
@ 2021-06-09 6:56 ` Rick Chen
0 siblings, 0 replies; 19+ messages in thread
From: Rick Chen @ 2021-06-09 6:56 UTC (permalink / raw)
To: Bin Meng; +Cc: U-Boot Mailing List, rick, Leo Liang
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs
>
> There are two spaces before "debug' in bootargs. Drop one.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> arch/riscv/dts/ae350_64.dts | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs
2021-06-04 5:51 ` [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8768@ATCPCS12.andestech.com>
@ 2021-06-15 15:58 ` Leo Liang
1 sibling, 0 replies; 19+ messages in thread
From: Leo Liang @ 2021-06-15 15:58 UTC (permalink / raw)
To: Bin Meng; +Cc: u-boot
On Fri, Jun 04, 2021 at 01:51:10PM +0800, Bin Meng wrote:
> There are two spaces before "debug' in bootargs. Drop one.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> arch/riscv/dts/ae350_64.dts | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
2021-06-04 5:51 [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
2021-06-04 5:51 ` [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs Bin Meng
@ 2021-06-04 5:51 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B61@ATCPCS12.andestech.com>
2021-06-15 15:59 ` Leo Liang
2021-06-04 5:51 ` [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit Bin Meng
` (4 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Bin Meng @ 2021-06-04 5:51 UTC (permalink / raw)
To: Rick Chen, Leo, U-Boot Mailing List
PLIC nodes don't have child nodes, so #address-cells is not needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/ae350_32.dts | 2 --
arch/riscv/dts/ae350_64.dts | 2 --
2 files changed, 4 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index b90351e87b..0917b83108 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -135,7 +135,6 @@
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
- #address-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe4000000 0x2000000>;
@@ -148,7 +147,6 @@
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
- #address-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe6400000 0x400000>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 27ac21c716..564e94a1db 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -135,7 +135,6 @@
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
- #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe4000000 0x0 0x2000000>;
@@ -148,7 +147,6 @@
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
- #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe6400000 0x0 0x400000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
[parent not found: <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B61@ATCPCS12.andestech.com>]
* Re: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B61@ATCPCS12.andestech.com>
@ 2021-06-15 5:32 ` Rick Chen
0 siblings, 0 replies; 19+ messages in thread
From: Rick Chen @ 2021-06-15 5:32 UTC (permalink / raw)
To: Bin Meng; +Cc: U-Boot Mailing List, Leo Liang, rick
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
>
> PLIC nodes don't have child nodes, so #address-cells is not needed.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 --
> arch/riscv/dts/ae350_64.dts | 2 --
> 2 files changed, 4 deletions(-)
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
2021-06-04 5:51 ` [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B61@ATCPCS12.andestech.com>
@ 2021-06-15 15:59 ` Leo Liang
1 sibling, 0 replies; 19+ messages in thread
From: Leo Liang @ 2021-06-15 15:59 UTC (permalink / raw)
To: Bin Meng; +Cc: u-boot
On Fri, Jun 04, 2021 at 01:51:11PM +0800, Bin Meng wrote:
> PLIC nodes don't have child nodes, so #address-cells is not needed.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 --
> arch/riscv/dts/ae350_64.dts | 2 --
> 2 files changed, 4 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
2021-06-04 5:51 [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
2021-06-04 5:51 ` [PATCH 2/5] riscv: ae350: dts: Remove the unnecessary space in bootargs Bin Meng
2021-06-04 5:51 ` [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes Bin Meng
@ 2021-06-04 5:51 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B6E@ATCPCS12.andestech.com>
2021-06-15 16:00 ` Leo Liang
2021-06-04 5:51 ` [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config Bin Meng
` (3 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: Bin Meng @ 2021-06-04 5:51 UTC (permalink / raw)
To: Rick Chen, Leo, U-Boot Mailing List
All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/ae350_32.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0917b83108..70576846f2 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -135,7 +135,7 @@
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
interrupt-controller;
reg = <0xe4000000 0x2000000>;
riscv,ndev=<71>;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
[parent not found: <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B6E@ATCPCS12.andestech.com>]
* Re: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B6E@ATCPCS12.andestech.com>
@ 2021-06-15 5:33 ` Rick Chen
0 siblings, 0 replies; 19+ messages in thread
From: Rick Chen @ 2021-06-15 5:33 UTC (permalink / raw)
To: Bin Meng; +Cc: U-Boot Mailing List, Leo Liang, rick
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
>
> All the device nodes that refer to plic0 as their interrupt parent have 2 cells encoded in their interrupts property, but plic0 only provides 1 cell in #interrupt-cells which is incorrect.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
2021-06-04 5:51 ` [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA9B6E@ATCPCS12.andestech.com>
@ 2021-06-15 16:00 ` Leo Liang
1 sibling, 0 replies; 19+ messages in thread
From: Leo Liang @ 2021-06-15 16:00 UTC (permalink / raw)
To: Bin Meng; +Cc: u-boot
On Fri, Jun 04, 2021 at 01:51:12PM +0800, Bin Meng wrote:
> All the device nodes that refer to plic0 as their interrupt parent
> have 2 cells encoded in their interrupts property, but plic0 only
> provides 1 cell in #interrupt-cells which is incorrect.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
2021-06-04 5:51 [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
` (2 preceding siblings ...)
2021-06-04 5:51 ` [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit Bin Meng
@ 2021-06-04 5:51 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA8783@ATCPCS12.andestech.com>
2021-06-08 8:41 ` [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
` (2 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Bin Meng @ 2021-06-04 5:51 UTC (permalink / raw)
To: Rick Chen, Leo, U-Boot Mailing List
At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The
intention was to use gdb to load device tree before running U-Boot
SPL/proper from RAM. When we switch to OF_SEPARATE we will have to
use our own DT but without "u-boot,dm-spl" in several essential
nodes, SPL does not boot.
Let's add all the required "u-boot,dm-spl" for SPL config.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/dts/ae350-u-boot.dtsi | 52 ++++++++++++++++++++++++++++++++
arch/riscv/dts/ae350_32.dts | 1 +
arch/riscv/dts/ae350_64.dts | 1 +
3 files changed, 54 insertions(+)
create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
new file mode 100644
index 0000000000..0d4201cfae
--- /dev/null
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+ cpus {
+ u-boot,dm-spl;
+ CPU0: cpu@0 {
+ u-boot,dm-spl;
+ CPU0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ CPU1: cpu@1 {
+ u-boot,dm-spl;
+ CPU1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ CPU2: cpu@2 {
+ u-boot,dm-spl;
+ CPU2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ CPU3: cpu@3 {
+ u-boot,dm-spl;
+ CPU3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+ memory@0 {
+ u-boot,dm-spl;
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ plic1: interrupt-controller@e6400000 {
+ u-boot,dm-spl;
+ };
+
+ plmt0@e6000000 {
+ u-boot,dm-spl;
+ };
+ };
+
+ serial0: serial@f0300000 {
+ u-boot,dm-spl;
+ };
+
+};
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 70576846f2..083f676333 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include "binman.dtsi"
+#include "ae350-u-boot.dtsi"
/ {
#address-cells = <1>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 564e94a1db..74cff9122d 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include "binman.dtsi"
+#include "ae350-u-boot.dtsi"
/ {
#address-cells = <2>;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header
2021-06-04 5:51 [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
` (3 preceding siblings ...)
2021-06-04 5:51 ` [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config Bin Meng
@ 2021-06-08 8:41 ` Bin Meng
2021-06-11 3:30 ` Leo Liang
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA7FD5@ATCPCS12.andestech.com>
6 siblings, 0 replies; 19+ messages in thread
From: Bin Meng @ 2021-06-08 8:41 UTC (permalink / raw)
To: Rick Chen, Leo, U-Boot Mailing List
On Fri, Jun 4, 2021 at 1:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The SPDX license header is currently missing. Add one.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 ++
> arch/riscv/dts/ae350_64.dts | 2 ++
> 2 files changed, 4 insertions(+)
>
Ping for this series?
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header
2021-06-04 5:51 [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
` (4 preceding siblings ...)
2021-06-08 8:41 ` [PATCH 1/5] riscv: ae350: dts: Add SPDX license header Bin Meng
@ 2021-06-11 3:30 ` Leo Liang
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA7FD5@ATCPCS12.andestech.com>
6 siblings, 0 replies; 19+ messages in thread
From: Leo Liang @ 2021-06-11 3:30 UTC (permalink / raw)
To: Bin Meng; +Cc: u-boot, rick
On Fri, Jun 04, 2021 at 01:51:09PM +0800, Bin Meng wrote:
> The SPDX license header is currently missing. Add one.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 ++
> arch/riscv/dts/ae350_64.dts | 2 ++
> 2 files changed, 4 insertions(+)
>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <752D002CFF5D0F4FA35C0100F1D73F3FE5EA7FD5@ATCPCS12.andestech.com>]
* Re: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA7FD5@ATCPCS12.andestech.com>
@ 2021-06-15 3:33 ` Rick Chen
0 siblings, 0 replies; 19+ messages in thread
From: Rick Chen @ 2021-06-15 3:33 UTC (permalink / raw)
To: Bin Meng; +Cc: U-Boot Mailing List, Leo Liang, rick
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de>
> Subject: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header
>
> The SPDX license header is currently missing. Add one.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 ++
> arch/riscv/dts/ae350_64.dts | 2 ++
> 2 files changed, 4 insertions(+)
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 19+ messages in thread