u-boot.lists.denx.de archive mirror
 help / color / mirror / Atom feed
From: Yifan Gu <me@yifangu.com>
To: u-boot@lists.denx.de
Cc: Yifan Gu <me@yifangu.com>,
	Jagan Teki <jagan@amarulasolutions.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Icenowy Zheng <icenowy@aosc.io>,
	George Hilliard <thirtythreeforty@gmail.com>
Subject: [PATCH 18/27] sunxi: suniv: add device tree nodes for f1c100s MMC controllers
Date: Sun, 25 Jul 2021 19:16:27 -0400	[thread overview]
Message-ID: <20210725231636.879913-19-me@yifangu.com> (raw)
In-Reply-To: <20210725231636.879913-1-me@yifangu.com>

From: George Hilliard <thirtythreeforty@gmail.com>

The f1c100s has two MMC controllers.  Add device tree nodes for them.

Signed-off-by: George Hilliard <thirtythreeforty@gmail.com>
Signed-off-by: Yifan Gu <me@yifangu.com>
---
 arch/arm/dts/suniv.dtsi | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
index b11d9eb57a..bea7c08e7d 100644
--- a/arch/arm/dts/suniv.dtsi
+++ b/arch/arm/dts/suniv.dtsi
@@ -125,6 +125,11 @@
 				pins = "PE0", "PE1";
 				function = "uart0";
 			};
+
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+				function = "mmc0";
+			};
 		};
 
 		timer@1c20c00 {
@@ -197,5 +202,47 @@
 			#phy-cells = <1>;
 			status = "disabled";
 		};
+
+		mmc0: mmc@1c0f000 {
+			compatible = "allwinner,suniv-f1c100s-mmc",
+			             "allwinner,sun7i-a20-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>,
+			         <&ccu CLK_MMC0>,
+			         <&ccu CLK_MMC0_OUTPUT>,
+			         <&ccu CLK_MMC0_SAMPLE>;
+			clock-names = "ahb",
+			              "mmc",
+			              "output",
+			              "sample";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			interrupts = <23>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@1c10000 {
+			compatible = "allwinner,suniv-f1c100s-mmc",
+			             "allwinner,sun7i-a20-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC1>,
+			         <&ccu CLK_MMC1>,
+			         <&ccu CLK_MMC1_OUTPUT>,
+			         <&ccu CLK_MMC1_SAMPLE>;
+			clock-names = "ahb",
+			              "mmc",
+			              "output",
+			              "sample";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			interrupts = <24>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
-- 
2.25.1


  parent reply	other threads:[~2021-07-25 23:37 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-25 23:16 [PATCH 00/27] Add F1C100s based PocketGo handheld support Yifan Gu
2021-07-25 23:16 ` [PATCH 01/27] arm: arm926ejs: start.S: port save_boot_params support from armv7 code Yifan Gu
2021-07-25 23:16 ` [PATCH 02/27] arm: arm926ej-s: add sunxi code Yifan Gu
2021-07-25 23:16 ` [PATCH 03/27] sunxi: add support for suniv architecture Yifan Gu
2021-07-25 23:16 ` [PATCH 04/27] sunxi: suniv: add support for Lichee Pi Nano Yifan Gu
2021-07-25 23:16 ` [PATCH 05/27] sunxi: suniv: add boot sequence for SPL to try Yifan Gu
2021-07-25 23:16 ` [PATCH 06/27] sunxi: spi-spl: add support for SUNIV Yifan Gu
2021-07-25 23:16 ` [PATCH 07/27] sunxi: add SPI0 node for suniv Yifan Gu
2021-07-25 23:16 ` [PATCH 08/27] sunxi: enable SPI NOR on Lichee Pi Nano Yifan Gu
2021-07-25 23:16 ` [PATCH 09/27] sunxi: add defconfig for Lichee Pi Nano with SPI Flash support Yifan Gu
2021-07-25 23:16 ` [PATCH 10/27] sunxi: add support for UART at PF for suniv Yifan Gu
2021-07-25 23:16 ` [PATCH 11/27] sunxi: do not set PF MMC0 pinmux when PF uart is used Yifan Gu
2021-07-25 23:16 ` [PATCH 12/27] sunxi: allow to enable MMC driver when using PF UART0 Yifan Gu
2021-07-25 23:16 ` [PATCH 13/27] sunxi: Don't provide enable_cache() on suniv Yifan Gu
2021-07-25 23:16 ` [PATCH 14/27] sunxi: implement clock driver for suniv f1c100s Yifan Gu
2022-01-20  0:38   ` Sean Anderson
2021-07-25 23:16 ` [PATCH 15/27] sunxi: gpio: Add support for suniv-f1c100s Yifan Gu
2021-07-25 23:16 ` [PATCH 16/27] sunxi: spi: restore bus speed and mode after reset Yifan Gu
2021-07-25 23:16 ` [PATCH 17/27] sunxi: spi: Add suniv pin controller support Yifan Gu
2021-07-25 23:16 ` Yifan Gu [this message]
2021-07-25 23:16 ` [PATCH 19/27] arm: dts: sunxi: do not renumber if mmc2 does not exist Yifan Gu
2021-07-26  1:01   ` Icenowy Zheng
2021-07-25 23:16 ` [PATCH 20/27] board: licheepi_nano: set CONFIG_MMC_SUNXI_SLOT_EXTRA Yifan Gu
2021-07-25 23:16 ` [PATCH 21/27] sunxi: suniv: add missing header include for udelay Yifan Gu
2021-07-25 23:16 ` [PATCH 22/27] sunxi: suniv: allow serial connection on uart1 Yifan Gu
2021-07-25 23:16 ` [PATCH 23/27] sunxi: suniv: do not detect boot sector on suniv Yifan Gu
2021-07-25 23:16 ` [PATCH 24/27] sunxi: suniv: set SYS_TEXT_BASE default Yifan Gu
2021-07-25 23:16 ` [PATCH 25/27] sunxi: suniv: disable mmc optimization for suniv Yifan Gu
2021-07-25 23:16 ` [PATCH 26/27] arm: dts: suniv: define uart1 pins Yifan Gu
2021-07-25 23:16 ` [PATCH 27/27] arm: dts: add pocketgo handheld support Yifan Gu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210725231636.879913-19-me@yifangu.com \
    --to=me@yifangu.com \
    --cc=andre.przywara@arm.com \
    --cc=icenowy@aosc.io \
    --cc=jagan@amarulasolutions.com \
    --cc=thirtythreeforty@gmail.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).