* [PATCH] net: phy: mscc: add support for VSC8502 in dual RGMII mode
@ 2021-09-27 23:13 Vladimir Oltean
2021-09-28 13:34 ` Ramon Fried
0 siblings, 1 reply; 3+ messages in thread
From: Vladimir Oltean @ 2021-09-27 23:13 UTC (permalink / raw)
To: u-boot; +Cc: Joe Hershberger, Ramon Fried
The VSC8502 is a Microchip (formerly Microsemi, formerly Vitesse)
dual port, gigabit Ethernet copper PHY which supports the MII, GMII and
RGMII MAC-side interfaces.
Of these, I could only test RGMII, and my board needed RGMII delays to
be applied by software, so I am able to confirm that this patch handles
that properly.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/phy/mscc.c | 56 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index d1a643cf5a0c..f9482b21a010 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -19,6 +19,7 @@
/* Microsemi PHY ID's */
#define PHY_ID_VSC8530 0x00070560
#define PHY_ID_VSC8531 0x00070570
+#define PHY_ID_VSC8502 0x00070630
#define PHY_ID_VSC8540 0x00070760
#define PHY_ID_VSC8541 0x00070770
#define PHY_ID_VSC8574 0x000704a0
@@ -1513,6 +1514,50 @@ static int vsc8584_config(struct phy_device *phydev)
return vsc8584_config_init(phydev);
}
+static int vsc8502_config(struct phy_device *phydev)
+{
+ bool rgmii_rx_delay = false, rgmii_tx_delay = false;
+ u16 reg = 0;
+ int ret;
+
+ /* Assume nothing needs to be done for the default GMII/MII mode */
+ if (!phy_interface_is_rgmii(phydev))
+ return 0;
+
+ /* Set Extended PHY Control 1 register to RGMII */
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_1_REG,
+ BIT(13) | BIT(12));
+
+ /* Soft reset required after changing PHY mode from the default
+ * of GMII/MII
+ */
+ ret = mscc_phy_soft_reset(phydev);
+ if (ret)
+ return ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ rgmii_rx_delay = true;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ rgmii_tx_delay = true;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT2);
+
+ if (rgmii_rx_delay)
+ reg |= VSC_PHY_RGMII_DELAY_2000_PS << RGMII_RX_CLK_DELAY_POS;
+ if (rgmii_tx_delay)
+ reg |= VSC_PHY_RGMII_DELAY_2000_PS << RGMII_TX_CLK_DELAY_POS;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return 0;
+}
+
static struct phy_driver VSC8530_driver = {
.name = "Microsemi VSC8530",
.uid = PHY_ID_VSC8530,
@@ -1533,6 +1578,16 @@ static struct phy_driver VSC8531_driver = {
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8502_driver = {
+ .name = "Microsemi VSC8502",
+ .uid = PHY_ID_VSC8502,
+ .mask = 0x000ffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8502_config,
+ .startup = &mscc_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static struct phy_driver VSC8540_driver = {
.name = "Microsemi VSC8540",
.uid = PHY_ID_VSC8540,
@@ -1577,6 +1632,7 @@ int phy_mscc_init(void)
{
phy_register(&VSC8530_driver);
phy_register(&VSC8531_driver);
+ phy_register(&VSC8502_driver);
phy_register(&VSC8540_driver);
phy_register(&VSC8541_driver);
phy_register(&VSC8574_driver);
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] net: phy: mscc: add support for VSC8502 in dual RGMII mode
2021-09-27 23:13 [PATCH] net: phy: mscc: add support for VSC8502 in dual RGMII mode Vladimir Oltean
@ 2021-09-28 13:34 ` Ramon Fried
2021-10-28 18:37 ` Ramon Fried
0 siblings, 1 reply; 3+ messages in thread
From: Ramon Fried @ 2021-09-28 13:34 UTC (permalink / raw)
To: Vladimir Oltean; +Cc: U-Boot Mailing List, Joe Hershberger
On Tue, Sep 28, 2021 at 2:13 AM Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
>
> The VSC8502 is a Microchip (formerly Microsemi, formerly Vitesse)
> dual port, gigabit Ethernet copper PHY which supports the MII, GMII and
> RGMII MAC-side interfaces.
>
> Of these, I could only test RGMII, and my board needed RGMII delays to
> be applied by software, so I am able to confirm that this patch handles
> that properly.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> drivers/net/phy/mscc.c | 56 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
> index d1a643cf5a0c..f9482b21a010 100644
> --- a/drivers/net/phy/mscc.c
> +++ b/drivers/net/phy/mscc.c
> @@ -19,6 +19,7 @@
> /* Microsemi PHY ID's */
> #define PHY_ID_VSC8530 0x00070560
> #define PHY_ID_VSC8531 0x00070570
> +#define PHY_ID_VSC8502 0x00070630
> #define PHY_ID_VSC8540 0x00070760
> #define PHY_ID_VSC8541 0x00070770
> #define PHY_ID_VSC8574 0x000704a0
> @@ -1513,6 +1514,50 @@ static int vsc8584_config(struct phy_device *phydev)
> return vsc8584_config_init(phydev);
> }
>
> +static int vsc8502_config(struct phy_device *phydev)
> +{
> + bool rgmii_rx_delay = false, rgmii_tx_delay = false;
> + u16 reg = 0;
> + int ret;
> +
> + /* Assume nothing needs to be done for the default GMII/MII mode */
> + if (!phy_interface_is_rgmii(phydev))
> + return 0;
> +
> + /* Set Extended PHY Control 1 register to RGMII */
> + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_1_REG,
> + BIT(13) | BIT(12));
> +
> + /* Soft reset required after changing PHY mode from the default
> + * of GMII/MII
> + */
> + ret = mscc_phy_soft_reset(phydev);
> + if (ret)
> + return ret;
> +
> + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
> + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
> + rgmii_rx_delay = true;
> + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
> + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
> + rgmii_tx_delay = true;
> +
> + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
> + MSCC_PHY_PAGE_EXT2);
> +
> + if (rgmii_rx_delay)
> + reg |= VSC_PHY_RGMII_DELAY_2000_PS << RGMII_RX_CLK_DELAY_POS;
> + if (rgmii_tx_delay)
> + reg |= VSC_PHY_RGMII_DELAY_2000_PS << RGMII_TX_CLK_DELAY_POS;
> +
> + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg);
> +
> + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
> + MSCC_PHY_PAGE_STD);
> +
> + return 0;
> +}
> +
> static struct phy_driver VSC8530_driver = {
> .name = "Microsemi VSC8530",
> .uid = PHY_ID_VSC8530,
> @@ -1533,6 +1578,16 @@ static struct phy_driver VSC8531_driver = {
> .shutdown = &genphy_shutdown,
> };
>
> +static struct phy_driver VSC8502_driver = {
> + .name = "Microsemi VSC8502",
> + .uid = PHY_ID_VSC8502,
> + .mask = 0x000ffff0,
> + .features = PHY_GBIT_FEATURES,
> + .config = &vsc8502_config,
> + .startup = &mscc_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +
> static struct phy_driver VSC8540_driver = {
> .name = "Microsemi VSC8540",
> .uid = PHY_ID_VSC8540,
> @@ -1577,6 +1632,7 @@ int phy_mscc_init(void)
> {
> phy_register(&VSC8530_driver);
> phy_register(&VSC8531_driver);
> + phy_register(&VSC8502_driver);
> phy_register(&VSC8540_driver);
> phy_register(&VSC8541_driver);
> phy_register(&VSC8574_driver);
> --
> 2.25.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] net: phy: mscc: add support for VSC8502 in dual RGMII mode
2021-09-28 13:34 ` Ramon Fried
@ 2021-10-28 18:37 ` Ramon Fried
0 siblings, 0 replies; 3+ messages in thread
From: Ramon Fried @ 2021-10-28 18:37 UTC (permalink / raw)
To: Vladimir Oltean; +Cc: U-Boot Mailing List, Joe Hershberger
On Tue, Sep 28, 2021 at 4:34 PM Ramon Fried <rfried.dev@gmail.com> wrote:
>
> On Tue, Sep 28, 2021 at 2:13 AM Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
> >
> > The VSC8502 is a Microchip (formerly Microsemi, formerly Vitesse)
> > dual port, gigabit Ethernet copper PHY which supports the MII, GMII and
> > RGMII MAC-side interfaces.
> >
> > Of these, I could only test RGMII, and my board needed RGMII delays to
> > be applied by software, so I am able to confirm that this patch handles
> > that properly.
> >
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > ---
> > drivers/net/phy/mscc.c | 56 ++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 56 insertions(+)
> >
> > diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
> > index d1a643cf5a0c..f9482b21a010 100644
> > --- a/drivers/net/phy/mscc.c
> > +++ b/drivers/net/phy/mscc.c
> > @@ -19,6 +19,7 @@
> > /* Microsemi PHY ID's */
> > #define PHY_ID_VSC8530 0x00070560
> > #define PHY_ID_VSC8531 0x00070570
> > +#define PHY_ID_VSC8502 0x00070630
> > #define PHY_ID_VSC8540 0x00070760
> > #define PHY_ID_VSC8541 0x00070770
> > #define PHY_ID_VSC8574 0x000704a0
> > @@ -1513,6 +1514,50 @@ static int vsc8584_config(struct phy_device *phydev)
> > return vsc8584_config_init(phydev);
> > }
> >
> > +static int vsc8502_config(struct phy_device *phydev)
> > +{
> > + bool rgmii_rx_delay = false, rgmii_tx_delay = false;
> > + u16 reg = 0;
> > + int ret;
> > +
> > + /* Assume nothing needs to be done for the default GMII/MII mode */
> > + if (!phy_interface_is_rgmii(phydev))
> > + return 0;
> > +
> > + /* Set Extended PHY Control 1 register to RGMII */
> > + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_1_REG,
> > + BIT(13) | BIT(12));
> > +
> > + /* Soft reset required after changing PHY mode from the default
> > + * of GMII/MII
> > + */
> > + ret = mscc_phy_soft_reset(phydev);
> > + if (ret)
> > + return ret;
> > +
> > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
> > + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
> > + rgmii_rx_delay = true;
> > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
> > + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
> > + rgmii_tx_delay = true;
> > +
> > + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
> > + MSCC_PHY_PAGE_EXT2);
> > +
> > + if (rgmii_rx_delay)
> > + reg |= VSC_PHY_RGMII_DELAY_2000_PS << RGMII_RX_CLK_DELAY_POS;
> > + if (rgmii_tx_delay)
> > + reg |= VSC_PHY_RGMII_DELAY_2000_PS << RGMII_TX_CLK_DELAY_POS;
> > +
> > + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg);
> > +
> > + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
> > + MSCC_PHY_PAGE_STD);
> > +
> > + return 0;
> > +}
> > +
> > static struct phy_driver VSC8530_driver = {
> > .name = "Microsemi VSC8530",
> > .uid = PHY_ID_VSC8530,
> > @@ -1533,6 +1578,16 @@ static struct phy_driver VSC8531_driver = {
> > .shutdown = &genphy_shutdown,
> > };
> >
> > +static struct phy_driver VSC8502_driver = {
> > + .name = "Microsemi VSC8502",
> > + .uid = PHY_ID_VSC8502,
> > + .mask = 0x000ffff0,
> > + .features = PHY_GBIT_FEATURES,
> > + .config = &vsc8502_config,
> > + .startup = &mscc_startup,
> > + .shutdown = &genphy_shutdown,
> > +};
> > +
> > static struct phy_driver VSC8540_driver = {
> > .name = "Microsemi VSC8540",
> > .uid = PHY_ID_VSC8540,
> > @@ -1577,6 +1632,7 @@ int phy_mscc_init(void)
> > {
> > phy_register(&VSC8530_driver);
> > phy_register(&VSC8531_driver);
> > + phy_register(&VSC8502_driver);
> > phy_register(&VSC8540_driver);
> > phy_register(&VSC8541_driver);
> > phy_register(&VSC8574_driver);
> > --
> > 2.25.1
> >
> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Applied to u-boot-net/next
Thanks,
Ramon.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-09-27 23:13 [PATCH] net: phy: mscc: add support for VSC8502 in dual RGMII mode Vladimir Oltean
2021-09-28 13:34 ` Ramon Fried
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