* [PATCH] drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issue
@ 2021-10-10 16:12 Maninder Singh
0 siblings, 0 replies; 2+ messages in thread
From: Maninder Singh @ 2021-10-10 16:12 UTC (permalink / raw)
To: u-boot, Priyanka Jain; +Cc: Maninder Singh
Adds check for memory clock variable before calculating caslat_actual.
Set mclk_ps to slowest DIMM supported if mclk_ps is found zero.
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
---
drivers/ddr/fsl/lc_common_dimm_params.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index d299d763db..d738ae3a7c 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008-2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP Semiconductor
+ * Copyright 2017-2021 NXP Semiconductor
*/
#include <common.h>
@@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num,
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp = ~0;
- const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
+ unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#ifdef CONFIG_SYS_FSL_DDR3
const unsigned int taamax = 20000;
#else
@@ -37,6 +37,12 @@ compute_cas_latency(const unsigned int ctrl_num,
}
common_caslat = tmp;
+ if (!mclk_ps) {
+ printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n",
+ outpdimm->tckmin_x_ps);
+ mclk_ps = outpdimm->tckmin_x_ps;
+ }
+
/* validate if the memory clk is in the range of dimms */
if (mclk_ps < outpdimm->tckmin_x_ps) {
printf("DDR clock (MCLK cycle %u ps) is faster than "
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH] drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issue
@ 2021-09-27 16:17 Maninder Singh
0 siblings, 0 replies; 2+ messages in thread
From: Maninder Singh @ 2021-09-27 16:17 UTC (permalink / raw)
To: u-boot, Priyanka Jain; +Cc: Maninder Singh
Adds check for mclk_ps variable before calculating caslat_actual.
Verified changes on lx2160ardb board.
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
---
drivers/ddr/fsl/lc_common_dimm_params.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index d299d763db..062eadcbd4 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008-2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP Semiconductor
+ * Copyright 2017-2018, 2021 NXP Semiconductor
*/
#include <common.h>
@@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num,
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp = ~0;
- const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
+ unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#ifdef CONFIG_SYS_FSL_DDR3
const unsigned int taamax = 20000;
#else
@@ -37,6 +37,10 @@ compute_cas_latency(const unsigned int ctrl_num,
}
common_caslat = tmp;
+ if (!mclk_ps) {
+ mclk_ps = outpdimm->tckmin_x_ps;
+ }
+
/* validate if the memory clk is in the range of dimms */
if (mclk_ps < outpdimm->tckmin_x_ps) {
printf("DDR clock (MCLK cycle %u ps) is faster than "
--
2.17.1
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