From: "Pali Rohár" <pali@kernel.org>
To: Stefan Roese <sr@denx.de>, Simon Glass <sjg@chromium.org>,
Bin Meng <bmeng.cn@gmail.com>, Ryder Lee <ryder.lee@mediatek.com>,
Weijie Gao <weijie.gao@mediatek.com>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
Cc: u-boot@lists.denx.de
Subject: [PATCH u-boot-next 08/12] pci: mediatek: Use PCI_CONF1_EXT_ADDRESS() macro
Date: Fri, 26 Nov 2021 11:42:48 +0100 [thread overview]
Message-ID: <20211126104252.5443-9-pali@kernel.org> (raw)
In-Reply-To: <20211126104252.5443-1-pali@kernel.org>
PCI mediatek driver uses extended format of Config Address for PCI
Configuration Mechanism #1 but with cleared Enable bit.
So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing
PCI_CONF1_ENABLE bit and remove old custom driver address macros.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/pcie_mediatek.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c
index f5556713878f..051a3bc96935 100644
--- a/drivers/pci/pcie_mediatek.c
+++ b/drivers/pci/pcie_mediatek.c
@@ -41,10 +41,6 @@
#define PCIE_BAR_ENABLE BIT(0)
#define PCIE_REVISION_ID BIT(0)
#define PCIE_CLASS_CODE (0x60400 << 8)
-#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
- ((((regn) >> 8) & GENMASK(3, 0)) << 24))
-#define PCIE_CONF_ADDR(regn, bdf) \
- (PCIE_CONF_REG(regn) | (bdf))
/* MediaTek specific configuration registers */
#define PCIE_FTS_NUM 0x70c
@@ -147,8 +143,11 @@ static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf,
uint offset, void **paddress)
{
struct mtk_pcie *pcie = dev_get_priv(udev);
+ u32 val;
- writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
+ val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf),
+ PCI_FUNC(bdf), offset) & ~PCI_CONF1_ENABLE;
+ writel(val, pcie->base + PCIE_CFG_ADDR);
*paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
return 0;
@@ -330,7 +329,6 @@ static void mtk_pcie_port_free(struct mtk_pcie_port *port)
static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
{
struct mtk_pcie *pcie = port->pcie;
- u32 slot = PCI_DEV(port->slot << 11);
u32 val;
int err;
@@ -357,13 +355,14 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
/* configure FC credit */
- writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
- pcie->base + PCIE_CFG_ADDR);
+ val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FC_CREDIT) & ~PCI_CONF1_ENABLE;
+ writel(val, pcie->base + PCIE_CFG_ADDR);
clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
PCIE_FC_CREDIT_VAL(0x806c));
/* configure RC FTS number to 250 when it leaves L0s */
- writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
+ val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FTS_NUM) & ~PCI_CONF1_ENABLE;
+ writel(val, pcie->base + PCIE_CFG_ADDR);
clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
PCIE_FTS_NUM_L0(0x50));
--
2.20.1
next prev parent reply other threads:[~2021-11-26 10:45 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 10:42 [PATCH u-boot-next 00/12] Common U-Boot macros for PCI Configuration Mechanism #1 Pali Rohár
2021-11-26 10:42 ` [PATCH u-boot-next 01/12] pci: Add standard PCI Config Address macros Pali Rohár
2021-12-28 8:32 ` Simon Glass
2021-12-28 13:34 ` Pali Rohár
2022-01-13 1:51 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 02/12] pci: gt64120: Use PCI_CONF1_ADDRESS() macro Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:51 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 03/12] pci: mpc85xx: Use PCI_CONF1_EXT_ADDRESS() macro Pali Rohár
2021-12-28 8:32 ` Simon Glass
2021-12-28 13:47 ` Pali Rohár
2022-01-13 1:51 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 04/12] pci: msc01: Use PCI_CONF1_ADDRESS() macro Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:51 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 05/12] pci: mvebu: Use PCI_CONF1_EXT_ADDRESS() macro Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:51 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 06/12] pci: tegra: " Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:51 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 07/12] pci: fsl: " Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:52 ` Tom Rini
2021-11-26 10:42 ` Pali Rohár [this message]
2021-12-28 8:32 ` [PATCH u-boot-next 08/12] pci: mediatek: " Simon Glass
2022-01-13 1:52 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 09/12] pci: sh7780: Use PCI_CONF1_ADDRESS() macro Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:52 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 10/12] x86: pci: " Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:52 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 11/12] m68k: mcf5445x: " Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:52 ` Tom Rini
2021-11-26 10:42 ` [PATCH u-boot-next 12/12] pci: sh7751: Fix access to config space via " Pali Rohár
2021-12-28 8:32 ` Simon Glass
2022-01-13 1:52 ` Tom Rini
2021-12-17 17:35 ` [PATCH u-boot-next 00/12] Common U-Boot macros for PCI Configuration Mechanism #1 Pali Rohár
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