* [PATCH v8 01/32] arm: qemu: Mention -nographic in the docs
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-24 14:34 ` Tom Rini
2021-12-17 3:59 ` [PATCH v8 02/32] arm: riscv: qemu: Explain how to extract the generated dt Simon Glass
` (30 subsequent siblings)
31 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud
Without this option QEMU appears to hang. Add it to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
(no changes since v1)
doc/board/emulation/qemu-arm.rst | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst
index 584ef0a7e15..8bd7b60cdb4 100644
--- a/doc/board/emulation/qemu-arm.rst
+++ b/doc/board/emulation/qemu-arm.rst
@@ -41,14 +41,15 @@ The minimal QEMU command line to get U-Boot up and running is:
- For ARM::
- qemu-system-arm -machine virt -bios u-boot.bin
+ qemu-system-arm -machine virt -nographic -bios u-boot.bin
- For AArch64::
- qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin
+ qemu-system-aarch64 -machine virt -nographic -cpu cortex-a57 -bios u-boot.bin
Note that for some odd reason qemu-system-aarch64 needs to be explicitly
-told to use a 64-bit CPU or it will boot in 32-bit mode.
+told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument
+ensures that output appears on the terminal. Use Ctrl-A X to quit.
Additional persistent U-boot environment support can be added as follows:
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v8 01/32] arm: qemu: Mention -nographic in the docs
2021-12-17 3:59 ` [PATCH v8 01/32] arm: qemu: Mention -nographic in the docs Simon Glass
@ 2021-12-24 14:34 ` Tom Rini
0 siblings, 0 replies; 36+ messages in thread
From: Tom Rini @ 2021-12-24 14:34 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Ilias Apalodimas, Sean Anderson,
Heinrich Schuchardt, Mark Kettenis, François Ozog,
Albert Aribaud
[-- Attachment #1: Type: text/plain, Size: 309 bytes --]
On Thu, Dec 16, 2021 at 08:59:08PM -0700, Simon Glass wrote:
> Without this option QEMU appears to hang. Add it to avoid confusion.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
For the series, applied to u-boot/next, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v8 02/32] arm: riscv: qemu: Explain how to extract the generated dt
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
2021-12-17 3:59 ` [PATCH v8 01/32] arm: qemu: Mention -nographic in the docs Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 03/32] arm: qemu: Add a devicetree file for qemu_arm Simon Glass
` (29 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud
QEMU currently generates a devicetree for use with U-Boot. Explain how to
obtain it.
Also explain how to merge it to produce a devicetree with the U-Boot
features included.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Rebase patch
Changes in v5:
- Merge RISC-V and ARM patches since they are similar
doc/board/emulation/qemu-arm.rst | 3 ++
doc/board/emulation/qemu-riscv.rst | 3 ++
doc/develop/devicetree/dt_qemu.rst | 48 ++++++++++++++++++++++++++++++
doc/develop/devicetree/index.rst | 1 +
4 files changed, 55 insertions(+)
create mode 100644 doc/develop/devicetree/dt_qemu.rst
diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst
index 8bd7b60cdb4..ff64ec08c3e 100644
--- a/doc/board/emulation/qemu-arm.rst
+++ b/doc/board/emulation/qemu-arm.rst
@@ -21,6 +21,9 @@ The 'virt' platform provides the following as the basic functionality:
Additionally, a number of optional peripherals can be added to the PCI bus.
+See :doc:`../../develop/devicetree/dt_qemu` for information on how to see
+the devicetree actually generated by QEMU.
+
Building U-Boot
---------------
Set the CROSS_COMPILE environment variable as usual, and run:
diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst
index 4b8e104a215..3409fff8117 100644
--- a/doc/board/emulation/qemu-riscv.rst
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -13,6 +13,9 @@ The QEMU virt machine models a generic RISC-V virtual machine with support for
the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
16550A UART devices in addition to VirtIO and it also uses device-tree to pass
configuration information to guest software. It implements RISC-V privileged
+
+See :doc:`../../develop/devicetree/dt_qemu` for information on how to see
+the devicetree actually generated by QEMU.
architecture spec v1.10.
Building U-Boot
diff --git a/doc/develop/devicetree/dt_qemu.rst b/doc/develop/devicetree/dt_qemu.rst
new file mode 100644
index 00000000000..c25c4fb053d
--- /dev/null
+++ b/doc/develop/devicetree/dt_qemu.rst
@@ -0,0 +1,48 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Devicetree in QEMU
+==================
+
+For QEMU on ARM, RISC-V and one PPC target, the devicetree is created on-the-fly
+by QEMU. It is intended for use in Linux but can be used by U-Boot also, so long
+as any nodes/properties needed by U-Boot are merged in.
+
+When `CONFIG_OF_BOARD` is enabled
+
+
+Obtaining the QEMU devicetree
+-----------------------------
+
+Where QEMU generates its own devicetree to pass to U-Boot tou can use
+`-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version.
+
+To obtain the devicetree that qemu generates, add `-machine dumpdtb=qemu.dtb`,
+e.g.::
+
+ qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb
+
+ qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb
+
+ qemu-system-riscv64 -machine virt -machine dumpdtb=qemu.dtb
+
+
+Merging in U-Boot nodes/properties
+----------------------------------
+
+Various U-Boot features require nodes and properties in the U-Boot devicetree
+and at present QEMU is unaware of these. To use these you must manually merge
+in the appropriate pieces.
+
+One way to do this is with dtc. This command runs dtc on each .dtb file in turn,
+to produce a text file. It drops the duplicate header on the qemu one. Then it
+joins them up and runs them through dtc to compile the output::
+
+ qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb
+ cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb u-boot.dtb |grep -v /dts-v1/) |dtc - -o merged.dtb
+
+You can then run qemu with the merged devicetree, e.g.::
+
+ qemu-system-arm -machine virt -nographic -bios u-boot.bin -dtb merged.dtb
+
+Note that there seems to be a bug in some versions of qemu where the output of
+dumpdtb does not quite match what is provided to U-Boot.
diff --git a/doc/develop/devicetree/index.rst b/doc/develop/devicetree/index.rst
index fa5db3eb76e..2edb69572dd 100644
--- a/doc/develop/devicetree/index.rst
+++ b/doc/develop/devicetree/index.rst
@@ -11,3 +11,4 @@ build-time and runtime configuration.
intro
control
+ dt_qemu
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 03/32] arm: qemu: Add a devicetree file for qemu_arm
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
2021-12-17 3:59 ` [PATCH v8 01/32] arm: qemu: Mention -nographic in the docs Simon Glass
2021-12-17 3:59 ` [PATCH v8 02/32] arm: riscv: qemu: Explain how to extract the generated dt Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 04/32] arm: qemu: Add a devicetree file for qemu_arm64 virt Simon Glass
` (28 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass,
Heinrich Schuchardt, Albert Aribaud, Tuomas Tynkkynen
This uses QEMU virt which creates its own devicetree.
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Switch to using an empty file for qemu virt
Changes in v6:
- Expand the commit message based on comments
arch/arm/dts/Makefile | 2 ++
arch/arm/dts/qemu-arm.dts | 11 +++++++++++
configs/qemu_arm_defconfig | 1 +
3 files changed, 14 insertions(+)
create mode 100644 arch/arm/dts/qemu-arm.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7f622fedbda..eaad3b679cc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1162,6 +1162,8 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
+dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/qemu-arm.dts b/arch/arm/dts/qemu-arm.dts
new file mode 100644
index 00000000000..230c630f04f
--- /dev/null
+++ b/arch/arm/dts/qemu-arm.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Empty device tree for qemu_arm
+
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+
+/ {
+};
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index d4f6d0b4373..a644a5f3e79 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-arm"
CONFIG_TARGET_QEMU_ARM_32BIT=y
CONFIG_DEBUG_UART_BASE=0x9000000
CONFIG_DEBUG_UART_CLOCK=0
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 04/32] arm: qemu: Add a devicetree file for qemu_arm64 virt
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (2 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 03/32] arm: qemu: Add a devicetree file for qemu_arm Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 05/32] riscv: qemu: Split devicetree files for qemu_riscv32/64 Simon Glass
` (27 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass,
Heinrich Schuchardt, Albert Aribaud, Tuomas Tynkkynen
This uses QEMU virt which creates its own devicetree.
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Switch to using an empty file for qemu virt
Changes in v6:
- Expand the commit message based on comments
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/qemu-arm64.dts | 11 +++++++++++
configs/qemu_arm64_defconfig | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/qemu-arm64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eaad3b679cc..2d92b2f940d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1162,7 +1162,7 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
-dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb
+dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/qemu-arm64.dts b/arch/arm/dts/qemu-arm64.dts
new file mode 100644
index 00000000000..096b3910728
--- /dev/null
+++ b/arch/arm/dts/qemu-arm64.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Empty device tree for qemu_arm64
+
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+
+/ {
+};
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 02a5e940c41..3c75fb71828 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-arm64"
CONFIG_DEBUG_UART_BASE=0x9000000
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_DEBUG_UART=y
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 05/32] riscv: qemu: Split devicetree files for qemu_riscv32/64
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (3 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 04/32] arm: qemu: Add a devicetree file for qemu_arm64 virt Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 06/32] arm: rpi: Sync rpi dts files from Linux Simon Glass
` (26 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass,
Heinrich Schuchardt, Bin Meng
This uses QEMU virt which creates its own devicetree.
Copy the existing empty version of this file, so splitting the existing
qemu-virt into two, since anyone actually trying to use this will need a
different devicetree for 32- and 64-bit machines.
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Reword commit message
- Switch to using an empty file for qemu virt
arch/riscv/dts/Makefile | 2 +-
arch/riscv/dts/{qemu-virt.dts => qemu-virt32.dts} | 3 +++
arch/riscv/dts/qemu-virt64.dts | 11 +++++++++++
configs/qemu-riscv32_defconfig | 1 +
configs/qemu-riscv32_smode_defconfig | 1 +
configs/qemu-riscv32_spl_defconfig | 2 +-
configs/qemu-riscv64_defconfig | 1 +
configs/qemu-riscv64_smode_defconfig | 1 +
configs/qemu-riscv64_spl_defconfig | 2 +-
9 files changed, 21 insertions(+), 3 deletions(-)
rename arch/riscv/dts/{qemu-virt.dts => qemu-virt32.dts} (94%)
create mode 100644 arch/riscv/dts/qemu-virt64.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b6e9166767b..90d3f35e6e3 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,7 +2,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
-dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
+dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
diff --git a/arch/riscv/dts/qemu-virt.dts b/arch/riscv/dts/qemu-virt32.dts
similarity index 94%
rename from arch/riscv/dts/qemu-virt.dts
rename to arch/riscv/dts/qemu-virt32.dts
index fecff542b91..17e2f0dea41 100644
--- a/arch/riscv/dts/qemu-virt.dts
+++ b/arch/riscv/dts/qemu-virt32.dts
@@ -6,3 +6,6 @@
/dts-v1/;
#include "binman.dtsi"
+
+/ {
+};
diff --git a/arch/riscv/dts/qemu-virt64.dts b/arch/riscv/dts/qemu-virt64.dts
new file mode 100644
index 00000000000..17e2f0dea41
--- /dev/null
+++ b/arch/riscv/dts/qemu-virt64.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
+
+/ {
+};
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index 0b8cd191618..4c0f51bd2aa 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80200000
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index 4d65104f7b4..19406080100 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index eb64c51a214..c4422969c61 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -2,7 +2,7 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index 4faa6dad8d6..cba975d703d 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index f575c127b7c..6b7771488fe 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 0fbdb7564c6..e02ca3a1465 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -2,7 +2,7 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 06/32] arm: rpi: Sync rpi dts files from Linux
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (4 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 05/32] riscv: qemu: Split devicetree files for qemu_riscv32/64 Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 07/32] arm: vexpress: Add a devicetree files for juno Simon Glass
` (25 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud,
Matthias Brugger, Stephen Warren, Stephen Warren
Sync these files, obtained from Linux v5.15.
This adds a devicetree file for rpi_4 which was not there before.
Testing shows no change so far as I can see:
- boots to U-Boot prompt on rpi0, rpi2
- boots to distro on rpi3
- boots to distro on rpi4
I am assuming that syncing with Linux is safe, but the maintainer should
know for sure.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Bring in files from Linux instead
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/bcm2711-rpi-4-b.dts | 262 +++++
arch/arm/dts/bcm2711-rpi.dtsi | 74 ++
arch/arm/dts/bcm2711.dtsi | 1100 ++++++++++++++++++
arch/arm/dts/bcm2835-common.dtsi | 207 ++++
arch/arm/dts/bcm2835-rpi-a-plus.dts | 18 +-
arch/arm/dts/bcm2835-rpi-a.dts | 16 +-
arch/arm/dts/bcm2835-rpi-b-plus.dts | 18 +-
arch/arm/dts/bcm2835-rpi-b-rev2.dts | 16 +-
arch/arm/dts/bcm2835-rpi-b.dts | 16 +-
arch/arm/dts/bcm2835-rpi-cm1-io1.dts | 9 +
arch/arm/dts/bcm2835-rpi-cm1.dtsi | 7 +-
arch/arm/dts/bcm2835-rpi-common.dtsi | 12 +
arch/arm/dts/bcm2835-rpi-zero-w.dts | 20 +-
arch/arm/dts/bcm2835-rpi-zero.dts | 16 +-
arch/arm/dts/bcm2835-rpi.dtsi | 35 +-
arch/arm/dts/bcm2835.dtsi | 2 +
arch/arm/dts/bcm2836-rpi-2-b.dts | 14 +-
arch/arm/dts/bcm2836.dtsi | 2 +
arch/arm/dts/bcm2837-rpi-3-a-plus.dts | 9 +-
arch/arm/dts/bcm2837-rpi-3-b-plus.dts | 9 +-
arch/arm/dts/bcm2837-rpi-3-b.dts | 5 +-
arch/arm/dts/bcm2837-rpi-cm3-io3.dts | 9 +
arch/arm/dts/bcm2837-rpi-cm3.dtsi | 9 +
arch/arm/dts/bcm2837.dtsi | 2 +
arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi | 7 +
arch/arm/dts/bcm283x.dtsi | 224 +---
configs/rpi_4_32b_defconfig | 1 +
configs/rpi_4_defconfig | 1 +
configs/rpi_arm64_defconfig | 1 +
include/dt-bindings/clock/bcm2835.h | 2 +
31 files changed, 1878 insertions(+), 248 deletions(-)
create mode 100644 arch/arm/dts/bcm2711-rpi-4-b.dts
create mode 100644 arch/arm/dts/bcm2711-rpi.dtsi
create mode 100644 arch/arm/dts/bcm2711.dtsi
create mode 100644 arch/arm/dts/bcm2835-common.dtsi
create mode 100644 arch/arm/dts/bcm2835-rpi-common.dtsi
create mode 100644 arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2d92b2f940d..9cddab37207 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1077,7 +1077,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
- bcm2837-rpi-cm3-io3.dtb
+ bcm2837-rpi-cm3-io3.dtb \
+ bcm2711-rpi-4-b.dtb
dtb-$(CONFIG_ARCH_BCM63158) += \
bcm963158.dtb
diff --git a/arch/arm/dts/bcm2711-rpi-4-b.dts b/arch/arm/dts/bcm2711-rpi-4-b.dts
new file mode 100644
index 00000000000..72ce80fbf26
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi-4-b.dts
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711.dtsi"
+#include "bcm2711-rpi.dtsi"
+#include "bcm283x-rpi-usb-peripheral.dtsi"
+
+/ {
+ compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
+ model = "Raspberry Pi 4 Model B";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ leds {
+ led-act {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ sd_io_1v8_reg: sd_io_1v8_reg {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-sd-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-settling-time-us = <5000>;
+ gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ status = "okay";
+ };
+
+ sd_vcc_reg: sd_vcc_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ddc0 {
+ status = "okay";
+};
+
+&ddc1 {
+ status = "okay";
+};
+
+&expgpio {
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "PWR_LED_OFF",
+ "GLOBAL_RESET",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "SD_PWR_ON",
+ "";
+};
+
+&gpio {
+ /*
+ * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
+ * the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD1",
+ "RXD1",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "RGMII_MDIO",
+ "RGMIO_MDC",
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
+ /* Shared with SPI flash */
+ "PWM0_MISO",
+ "PWM1_MOSI",
+ "STATUS_LED_G_CLK",
+ "SPIFLASH_CE_N",
+ "SDA0",
+ "SCL0",
+ "RGMII_RXCLK",
+ "RGMII_RXCTL",
+ "RGMII_RXD0",
+ "RGMII_RXD1",
+ "RGMII_RXD2",
+ "RGMII_RXD3",
+ "RGMII_TXCLK",
+ "RGMII_TXCTL",
+ "RGMII_TXD0",
+ "RGMII_TXD1",
+ "RGMII_TXD2",
+ "RGMII_TXD3";
+};
+
+&hdmi0 {
+ status = "okay";
+};
+
+&hdmi1 {
+ status = "okay";
+};
+
+&pixelvalve0 {
+ status = "okay";
+};
+
+&pixelvalve1 {
+ status = "okay";
+};
+
+&pixelvalve2 {
+ status = "okay";
+};
+
+&pixelvalve4 {
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
+ status = "okay";
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* EMMC2 is used to drive the SD card */
+&emmc2 {
+ vqmmc-supply = <&sd_io_1v8_reg>;
+ vmmc-supply = <&sd_vcc_reg>;
+ broken-cd;
+ status = "okay";
+};
+
+&genet {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-rxid";
+ status = "okay";
+};
+
+&genet_mdio {
+ phy1: ethernet-phy@1 {
+ /* No PHY interrupt */
+ reg = <0x1>;
+ };
+};
+
+&pcie0 {
+ pci@0,0 {
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ reg = <0 0 0 0 0>;
+
+ usb@0,0 {
+ reg = <0 0 0 0 0>;
+ resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
+ };
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
+
+&vc4 {
+ status = "okay";
+};
+
+&vec {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/bcm2711-rpi.dtsi b/arch/arm/dts/bcm2711-rpi.dtsi
new file mode 100644
index 00000000000..ca266c5d9f9
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm2835-rpi.dtsi"
+
+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
+
+/ {
+ /* Will be filled by the bootloader */
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0>;
+ };
+
+ aliases {
+ emmc2bus = &emmc2bus;
+ ethernet0 = &genet;
+ pcie0 = &pcie0;
+ blconfig = &blconfig;
+ };
+};
+
+&firmware {
+ firmware_clocks: clocks {
+ compatible = "raspberrypi,firmware-clocks";
+ #clock-cells = <1>;
+ };
+
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "okay";
+ };
+
+ reset: reset {
+ compatible = "raspberrypi,firmware-reset";
+ #reset-cells = <1>;
+ };
+};
+
+&hdmi0 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ wifi-2.4ghz-coexistence;
+};
+
+&hdmi1 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ wifi-2.4ghz-coexistence;
+};
+
+&hvs {
+ clocks = <&firmware_clocks 4>;
+};
+
+&rmem {
+ /*
+ * RPi4's co-processor will copy the board's bootloader configuration
+ * into memory for the OS to consume. It'll also update this node with
+ * its placement information.
+ */
+ blconfig: nvram@0 {
+ compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x0>;
+ no-map;
+ status = "disabled";
+ };
+};
+
+&vchiq {
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/dts/bcm2711.dtsi b/arch/arm/dts/bcm2711.dtsi
new file mode 100644
index 00000000000..3b60297af7f
--- /dev/null
+++ b/arch/arm/dts/bcm2711.dtsi
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm283x.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/bcm2835-pm.h>
+
+/ {
+ compatible = "brcm,bcm2711";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gicv2>;
+
+ vc4: gpu {
+ compatible = "brcm,bcm2711-vc5";
+ status = "disabled";
+ };
+
+ clk_27MHz: clk-27M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ clock-output-names = "27MHz-clock";
+ };
+
+ clk_108MHz: clk-108M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <108000000>;
+ clock-output-names = "108MHz-clock";
+ };
+
+ soc {
+ /*
+ * Defined ranges:
+ * Common BCM283x peripherals
+ * BCM2711-specific peripherals
+ * ARM-local peripherals
+ */
+ ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
+ <0x7c000000 0x0 0xfc000000 0x02000000>,
+ <0x40000000 0x0 0xff800000 0x00800000>;
+ /* Emulate a contiguous 30-bit address range for DMA */
+ dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
+
+ /*
+ * This node is the provider for the enable-method for
+ * bringing up secondary cores.
+ */
+ local_intc: local_intc@40000000 {
+ compatible = "brcm,bcm2836-l1-intc";
+ reg = <0x40000000 0x100>;
+ };
+
+ gicv2: interrupt-controller@40041000 {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "arm,gic-400";
+ reg = <0x40041000 0x1000>,
+ <0x40042000 0x2000>,
+ <0x40044000 0x2000>,
+ <0x40046000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ avs_monitor: avs-monitor@7d5d2000 {
+ compatible = "brcm,bcm2711-avs-monitor",
+ "syscon", "simple-mfd";
+ reg = <0x7d5d2000 0xf00>;
+
+ thermal: thermal {
+ compatible = "brcm,bcm2711-thermal";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xb00>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ /* DMA lite 7 - 10 */
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x07f5>;
+ };
+
+ pm: watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x7e100000 0x114>,
+ <0x7e00a000 0x24>,
+ <0x7ec11000 0x20>;
+ clocks = <&clocks BCM2835_CLOCK_V3D>,
+ <&clocks BCM2835_CLOCK_PERI_IMAGE>,
+ <&clocks BCM2835_CLOCK_H264>,
+ <&clocks BCM2835_CLOCK_ISP>;
+ clock-names = "v3d", "peri_image", "h264", "isp";
+ system-power-controller;
+ };
+
+ rng@7e104000 {
+ compatible = "brcm,bcm2711-rng200";
+ reg = <0x7e104000 0x28>;
+ };
+
+ uart2: serial@7e201400 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201400 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart3: serial@7e201600 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201600 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart4: serial@7e201800 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201800 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart5: serial@7e201a00 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201a00 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ spi3: spi@7e204600 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204600 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@7e204800 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204800 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@7e204a00 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204a00 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@7e204c00 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204c00 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@7e205600 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205600 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@7e205800 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205800 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@7e205a00 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205a00 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@7e205c00 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205c00 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pixelvalve0: pixelvalve@7e206000 {
+ compatible = "brcm,bcm2711-pixelvalve0";
+ reg = <0x7e206000 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pixelvalve1: pixelvalve@7e207000 {
+ compatible = "brcm,bcm2711-pixelvalve1";
+ reg = <0x7e207000 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pixelvalve2: pixelvalve@7e20a000 {
+ compatible = "brcm,bcm2711-pixelvalve2";
+ reg = <0x7e20a000 0x100>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@7e20c800 {
+ compatible = "brcm,bcm2835-pwm";
+ reg = <0x7e20c800 0x28>;
+ clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clock-rates = <10000000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pixelvalve4: pixelvalve@7e216000 {
+ compatible = "brcm,bcm2711-pixelvalve4";
+ reg = <0x7e216000 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ hvs: hvs@7e400000 {
+ compatible = "brcm,bcm2711-hvs";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pixelvalve3: pixelvalve@7ec12000 {
+ compatible = "brcm,bcm2711-pixelvalve3";
+ reg = <0x7ec12000 0x100>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ vec: vec@7ec13000 {
+ compatible = "brcm,bcm2711-vec";
+ reg = <0x7ec13000 0x1000>;
+ clocks = <&clocks BCM2835_CLOCK_VEC>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ dvp: clock@7ef00000 {
+ compatible = "brcm,brcm2711-dvp";
+ reg = <0x7ef00000 0x10>;
+ clocks = <&clk_108MHz>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ aon_intr: interrupt-controller@7ef00100 {
+ compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
+ reg = <0x7ef00100 0x30>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ hdmi0: hdmi@7ef00700 {
+ compatible = "brcm,bcm2711-hdmi0";
+ reg = <0x7ef00700 0x300>,
+ <0x7ef00300 0x200>,
+ <0x7ef00f00 0x80>,
+ <0x7ef00f80 0x80>,
+ <0x7ef01b00 0x200>,
+ <0x7ef01f00 0x400>,
+ <0x7ef00200 0x80>,
+ <0x7ef04300 0x100>,
+ <0x7ef20000 0x100>;
+ reg-names = "hdmi",
+ "dvp",
+ "phy",
+ "rm",
+ "packet",
+ "metadata",
+ "csc",
+ "cec",
+ "hd";
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ resets = <&dvp 0>;
+ interrupt-parent = <&aon_intr>;
+ interrupts = <0>, <1>, <2>,
+ <3>, <4>, <5>;
+ interrupt-names = "cec-tx", "cec-rx", "cec-low",
+ "wakeup", "hpd-connected", "hpd-removed";
+ ddc = <&ddc0>;
+ dmas = <&dma 10>;
+ dma-names = "audio-rx";
+ status = "disabled";
+ };
+
+ ddc0: i2c@7ef04500 {
+ compatible = "brcm,bcm2711-hdmi-i2c";
+ reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
+ reg-names = "bsc", "auto-i2c";
+ clock-frequency = <97500>;
+ status = "disabled";
+ };
+
+ hdmi1: hdmi@7ef05700 {
+ compatible = "brcm,bcm2711-hdmi1";
+ reg = <0x7ef05700 0x300>,
+ <0x7ef05300 0x200>,
+ <0x7ef05f00 0x80>,
+ <0x7ef05f80 0x80>,
+ <0x7ef06b00 0x200>,
+ <0x7ef06f00 0x400>,
+ <0x7ef00280 0x80>,
+ <0x7ef09300 0x100>,
+ <0x7ef20000 0x100>;
+ reg-names = "hdmi",
+ "dvp",
+ "phy",
+ "rm",
+ "packet",
+ "metadata",
+ "csc",
+ "cec",
+ "hd";
+ ddc = <&ddc1>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ resets = <&dvp 1>;
+ interrupt-parent = <&aon_intr>;
+ interrupts = <8>, <7>, <6>,
+ <9>, <10>, <11>;
+ interrupt-names = "cec-tx", "cec-rx", "cec-low",
+ "wakeup", "hpd-connected", "hpd-removed";
+ dmas = <&dma 17>;
+ dma-names = "audio-rx";
+ status = "disabled";
+ };
+
+ ddc1: i2c@7ef09500 {
+ compatible = "brcm,bcm2711-hdmi-i2c";
+ reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
+ reg-names = "bsc", "auto-i2c";
+ clock-frequency = <97500>;
+ status = "disabled";
+ };
+ };
+
+ /*
+ * emmc2 has different DMA constraints based on SoC revisions. It was
+ * moved into its own bus, so as for RPi4's firmware to update them.
+ * The firmware will find whether the emmc2bus alias is defined, and if
+ * so, it'll edit the dma-ranges property below accordingly.
+ */
+ emmc2bus: emmc2bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
+ dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
+
+ emmc2: mmc@7e340000 {
+ compatible = "brcm,bcm2711-emmc2";
+ reg = <0x0 0x7e340000 0x100>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2711_CLOCK_EMMC2>;
+ status = "disabled";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ /* This only applies to the ARMv7 stub */
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000d8>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e8>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000f0>;
+ };
+ };
+
+ scb {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
+ <0x6 0x00000000 0x6 0x00000000 0x40000000>;
+
+ pcie0: pcie@7d500000 {
+ compatible = "brcm,bcm2711-pcie";
+ reg = <0x0 0x7d500000 0x9310>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
+ IRQ_TYPE_LEVEL_HIGH>;
+ msi-controller;
+ msi-parent = <&pcie0>;
+
+ ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
+ 0x0 0x04000000>;
+ /*
+ * The wrapper around the PCIe block has a bug
+ * preventing it from accessing beyond the first 3GB of
+ * memory.
+ */
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
+ 0x0 0xc0000000>;
+ brcm,enable-ssc;
+ };
+
+ genet: ethernet@7d580000 {
+ compatible = "brcm,bcm2711-genet-v5";
+ reg = <0x0 0x7d580000 0x10000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ genet_mdio: mdio@e14 {
+ compatible = "brcm,genet-mdio-v5";
+ reg = <0xe14 0x8>;
+ reg-names = "mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+ };
+ };
+};
+
+&clk_osc {
+ clock-frequency = <54000000>;
+};
+
+&clocks {
+ compatible = "brcm,bcm2711-cprman";
+};
+
+&cpu_thermal {
+ coefficients = <(-487) 410040>;
+ thermal-sensors = <&thermal>;
+};
+
+&dsi0 {
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&dsi1 {
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ compatible = "brcm,bcm2711-dsi1";
+};
+
+&gpio {
+ compatible = "brcm,bcm2711-gpio";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpclk0_gpio49: gpclk0_gpio49 {
+ pin-gpclk {
+ pins = "gpio49";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ gpclk1_gpio50: gpclk1_gpio50 {
+ pin-gpclk {
+ pins = "gpio50";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ gpclk2_gpio51: gpclk2_gpio51 {
+ pin-gpclk {
+ pins = "gpio51";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+
+ i2c0_gpio46: i2c0_gpio46 {
+ pin-sda {
+ function = "alt0";
+ pins = "gpio46";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt0";
+ pins = "gpio47";
+ bias-disable;
+ };
+ };
+ i2c1_gpio46: i2c1_gpio46 {
+ pin-sda {
+ function = "alt1";
+ pins = "gpio46";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt1";
+ pins = "gpio47";
+ bias-disable;
+ };
+ };
+ i2c3_gpio2: i2c3_gpio2 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio2";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio3";
+ bias-disable;
+ };
+ };
+ i2c3_gpio4: i2c3_gpio4 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio4";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio5";
+ bias-disable;
+ };
+ };
+ i2c4_gpio6: i2c4_gpio6 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio6";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio7";
+ bias-disable;
+ };
+ };
+ i2c4_gpio8: i2c4_gpio8 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio8";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio9";
+ bias-disable;
+ };
+ };
+ i2c5_gpio10: i2c5_gpio10 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio10";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio11";
+ bias-disable;
+ };
+ };
+ i2c5_gpio12: i2c5_gpio12 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio12";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio13";
+ bias-disable;
+ };
+ };
+ i2c6_gpio0: i2c6_gpio0 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio0";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio1";
+ bias-disable;
+ };
+ };
+ i2c6_gpio22: i2c6_gpio22 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio22";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio23";
+ bias-disable;
+ };
+ };
+ i2c_slave_gpio8: i2c_slave_gpio8 {
+ pins-i2c-slave {
+ pins = "gpio8",
+ "gpio9",
+ "gpio10",
+ "gpio11";
+ function = "alt3";
+ };
+ };
+
+ jtag_gpio48: jtag_gpio48 {
+ pins-jtag {
+ pins = "gpio48",
+ "gpio49",
+ "gpio50",
+ "gpio51",
+ "gpio52",
+ "gpio53";
+ function = "alt4";
+ };
+ };
+
+ mii_gpio28: mii_gpio28 {
+ pins-mii {
+ pins = "gpio28",
+ "gpio29",
+ "gpio30",
+ "gpio31";
+ function = "alt4";
+ };
+ };
+ mii_gpio36: mii_gpio36 {
+ pins-mii {
+ pins = "gpio36",
+ "gpio37",
+ "gpio38",
+ "gpio39";
+ function = "alt5";
+ };
+ };
+
+ pcm_gpio50: pcm_gpio50 {
+ pins-pcm {
+ pins = "gpio50",
+ "gpio51",
+ "gpio52",
+ "gpio53";
+ function = "alt2";
+ };
+ };
+
+ pwm0_0_gpio12: pwm0_0_gpio12 {
+ pin-pwm {
+ pins = "gpio12";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_0_gpio18: pwm0_0_gpio18 {
+ pin-pwm {
+ pins = "gpio18";
+ function = "alt5";
+ bias-disable;
+ };
+ };
+ pwm1_0_gpio40: pwm1_0_gpio40 {
+ pin-pwm {
+ pins = "gpio40";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio13: pwm0_1_gpio13 {
+ pin-pwm {
+ pins = "gpio13";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio19: pwm0_1_gpio19 {
+ pin-pwm {
+ pins = "gpio19";
+ function = "alt5";
+ bias-disable;
+ };
+ };
+ pwm1_1_gpio41: pwm1_1_gpio41 {
+ pin-pwm {
+ pins = "gpio41";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio45: pwm0_1_gpio45 {
+ pin-pwm {
+ pins = "gpio45";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_0_gpio52: pwm0_0_gpio52 {
+ pin-pwm {
+ pins = "gpio52";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio53: pwm0_1_gpio53 {
+ pin-pwm {
+ pins = "gpio53";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+
+ rgmii_gpio35: rgmii_gpio35 {
+ pin-start-stop {
+ pins = "gpio35";
+ function = "alt4";
+ };
+ pin-rx-ok {
+ pins = "gpio36";
+ function = "alt4";
+ };
+ };
+ rgmii_irq_gpio34: rgmii_irq_gpio34 {
+ pin-irq {
+ pins = "gpio34";
+ function = "alt5";
+ };
+ };
+ rgmii_irq_gpio39: rgmii_irq_gpio39 {
+ pin-irq {
+ pins = "gpio39";
+ function = "alt4";
+ };
+ };
+ rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
+ pins-mdio {
+ pins = "gpio28",
+ "gpio29";
+ function = "alt5";
+ };
+ };
+ rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
+ pins-mdio {
+ pins = "gpio37",
+ "gpio38";
+ function = "alt4";
+ };
+ };
+
+ spi0_gpio46: spi0_gpio46 {
+ pins-spi {
+ pins = "gpio46",
+ "gpio47",
+ "gpio48",
+ "gpio49";
+ function = "alt2";
+ };
+ };
+ spi2_gpio46: spi2_gpio46 {
+ pins-spi {
+ pins = "gpio46",
+ "gpio47",
+ "gpio48",
+ "gpio49",
+ "gpio50";
+ function = "alt5";
+ };
+ };
+ spi3_gpio0: spi3_gpio0 {
+ pins-spi {
+ pins = "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3";
+ function = "alt3";
+ };
+ };
+ spi4_gpio4: spi4_gpio4 {
+ pins-spi {
+ pins = "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7";
+ function = "alt3";
+ };
+ };
+ spi5_gpio12: spi5_gpio12 {
+ pins-spi {
+ pins = "gpio12",
+ "gpio13",
+ "gpio14",
+ "gpio15";
+ function = "alt3";
+ };
+ };
+ spi6_gpio18: spi6_gpio18 {
+ pins-spi {
+ pins = "gpio18",
+ "gpio19",
+ "gpio20",
+ "gpio21";
+ function = "alt3";
+ };
+ };
+
+ uart2_gpio0: uart2_gpio0 {
+ pin-tx {
+ pins = "gpio0";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio1";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
+ pin-cts {
+ pins = "gpio2";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio3";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart3_gpio4: uart3_gpio4 {
+ pin-tx {
+ pins = "gpio4";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio5";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
+ pin-cts {
+ pins = "gpio6";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio7";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart4_gpio8: uart4_gpio8 {
+ pin-tx {
+ pins = "gpio8";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio9";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
+ pin-cts {
+ pins = "gpio10";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio11";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart5_gpio12: uart5_gpio12 {
+ pin-tx {
+ pins = "gpio12";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio13";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
+ pin-cts {
+ pins = "gpio14";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio15";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+};
+
+&rmem {
+ #address-cells = <2>;
+};
+
+&cma {
+ /*
+ * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
+ * that's not good enough for the BCM2711 as some devices can
+ * only address the lower 1G of memory (ZONE_DMA).
+ */
+ alloc-ranges = <0x0 0x00000000 0x40000000>;
+};
+
+&i2c0 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mailbox {
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhci {
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhost {
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi {
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi1 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi2 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&system_timer {
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&txp {
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart0 {
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart1 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&vec {
+ compatible = "brcm,bcm2711-vec";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/dts/bcm2835-common.dtsi b/arch/arm/dts/bcm2835-common.dtsi
new file mode 100644
index 00000000000..c25e797b906
--- /dev/null
+++ b/arch/arm/dts/bcm2835-common.dtsi
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* This include file covers the common peripherals and configuration between
+ * bcm2835, bcm2836 and bcm2837 implementations.
+ */
+
+/ {
+ interrupt-parent = <&intc>;
+
+ soc {
+ dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xf00>;
+ interrupts = <1 16>,
+ <1 17>,
+ <1 18>,
+ <1 19>,
+ <1 20>,
+ <1 21>,
+ <1 22>,
+ <1 23>,
+ <1 24>,
+ <1 25>,
+ <1 26>,
+ /* dma channel 11-14 share one irq */
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ /* unused shared irq for all channels */
+ <1 28>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10",
+ "dma11",
+ "dma12",
+ "dma13",
+ "dma14",
+ "dma-shared-all";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x7f35>;
+ };
+
+ intc: interrupt-controller@7e00b200 {
+ compatible = "brcm,bcm2835-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pm: watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x7e100000 0x114>,
+ <0x7e00a000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_V3D>,
+ <&clocks BCM2835_CLOCK_PERI_IMAGE>,
+ <&clocks BCM2835_CLOCK_H264>,
+ <&clocks BCM2835_CLOCK_ISP>;
+ clock-names = "v3d", "peri_image", "h264", "isp";
+ system-power-controller;
+ };
+
+ rng@7e104000 {
+ compatible = "brcm,bcm2835-rng";
+ reg = <0x7e104000 0x10>;
+ interrupts = <2 29>;
+ };
+
+ pixelvalve@7e206000 {
+ compatible = "brcm,bcm2835-pixelvalve0";
+ reg = <0x7e206000 0x100>;
+ interrupts = <2 13>; /* pwa0 */
+ };
+
+ pixelvalve@7e207000 {
+ compatible = "brcm,bcm2835-pixelvalve1";
+ reg = <0x7e207000 0x100>;
+ interrupts = <2 14>; /* pwa1 */
+ };
+
+ thermal: thermal@7e212000 {
+ compatible = "brcm,bcm2835-thermal";
+ reg = <0x7e212000 0x8>;
+ clocks = <&clocks BCM2835_CLOCK_TSENS>;
+ #thermal-sensor-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@7e805000 {
+ compatible = "brcm,bcm2835-i2c";
+ reg = <0x7e805000 0x1000>;
+ interrupts = <2 21>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+
+ vec: vec@7e806000 {
+ compatible = "brcm,bcm2835-vec";
+ reg = <0x7e806000 0x1000>;
+ clocks = <&clocks BCM2835_CLOCK_VEC>;
+ interrupts = <2 27>;
+ status = "disabled";
+ };
+
+ pixelvalve@7e807000 {
+ compatible = "brcm,bcm2835-pixelvalve2";
+ reg = <0x7e807000 0x100>;
+ interrupts = <2 10>; /* pixelvalve */
+ };
+
+ hdmi: hdmi@7e902000 {
+ compatible = "brcm,bcm2835-hdmi";
+ reg = <0x7e902000 0x600>,
+ <0x7e808000 0x100>;
+ interrupts = <2 8>, <2 9>;
+ ddc = <&i2c2>;
+ clocks = <&clocks BCM2835_PLLH_PIX>,
+ <&clocks BCM2835_CLOCK_HSM>;
+ clock-names = "pixel", "hdmi";
+ dmas = <&dma 17>;
+ dma-names = "audio-rx";
+ status = "disabled";
+ };
+
+ v3d: v3d@7ec00000 {
+ compatible = "brcm,bcm2835-v3d";
+ reg = <0x7ec00000 0x1000>;
+ interrupts = <1 10>;
+ };
+
+ vc4: gpu {
+ compatible = "brcm,bcm2835-vc4";
+ };
+ };
+};
+
+&cpu_thermal {
+ thermal-sensors = <&thermal>;
+};
+
+&gpio {
+ i2c_slave_gpio18: i2c_slave_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ jtag_gpio4: jtag_gpio4 {
+ brcm,pins = <4 5 6 12 13>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+
+ pwm0_gpio12: pwm0_gpio12 {
+ brcm,pins = <12>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm0_gpio18: pwm0_gpio18 {
+ brcm,pins = <18>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm0_gpio40: pwm0_gpio40 {
+ brcm,pins = <40>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio13: pwm1_gpio13 {
+ brcm,pins = <13>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio19: pwm1_gpio19 {
+ brcm,pins = <19>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm1_gpio41: pwm1_gpio41 {
+ brcm,pins = <41>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio45: pwm1_gpio45 {
+ brcm,pins = <45>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+};
+
+&i2s {
+ dmas = <&dma 2>, <&dma 3>;
+ dma-names = "tx", "rx";
+};
+
+&sdhost {
+ dmas = <&dma 13>;
+ dma-names = "rx-tx";
+};
+
+&spi {
+ dmas = <&dma 6>, <&dma 7>;
+ dma-names = "tx", "rx";
+};
diff --git a/arch/arm/dts/bcm2835-rpi-a-plus.dts b/arch/arm/dts/bcm2835-rpi-a-plus.dts
index db8a6017f22..40b9405f1a8 100644
--- a/arch/arm/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/dts/bcm2835-rpi-a-plus.dts
@@ -8,12 +8,17 @@
compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
model = "Raspberry Pi Model A+";
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x10000000>;
+ };
+
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
@@ -99,6 +104,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&pwm {
@@ -107,6 +114,13 @@
status = "okay";
};
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
diff --git a/arch/arm/dts/bcm2835-rpi-a.dts b/arch/arm/dts/bcm2835-rpi-a.dts
index 067d1f07a2d..11edb581dba 100644
--- a/arch/arm/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/dts/bcm2835-rpi-a.dts
@@ -8,8 +8,13 @@
compatible = "raspberrypi,model-a", "brcm,bcm2835";
model = "Raspberry Pi Model A";
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x10000000>;
+ };
+
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
@@ -94,6 +99,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&pwm {
@@ -102,6 +109,13 @@
status = "okay";
};
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
diff --git a/arch/arm/dts/bcm2835-rpi-b-plus.dts b/arch/arm/dts/bcm2835-rpi-b-plus.dts
index 1e40d672b05..1b435c64bd9 100644
--- a/arch/arm/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/dts/bcm2835-rpi-b-plus.dts
@@ -9,12 +9,17 @@
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
model = "Raspberry Pi Model B+";
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x20000000>;
+ };
+
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
@@ -101,6 +106,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&pwm {
@@ -109,6 +116,13 @@
status = "okay";
};
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
diff --git a/arch/arm/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/dts/bcm2835-rpi-b-rev2.dts
index 28e7513ce61..a23c25c00ee 100644
--- a/arch/arm/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/dts/bcm2835-rpi-b-rev2.dts
@@ -9,8 +9,13 @@
compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
model = "Raspberry Pi Model B rev2";
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x10000000>;
+ };
+
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
@@ -94,6 +99,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&pwm {
@@ -102,6 +109,13 @@
status = "okay";
};
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
diff --git a/arch/arm/dts/bcm2835-rpi-b.dts b/arch/arm/dts/bcm2835-rpi-b.dts
index 31ff602e2cd..1b63d6b1975 100644
--- a/arch/arm/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/dts/bcm2835-rpi-b.dts
@@ -9,8 +9,13 @@
compatible = "raspberrypi,model-b", "brcm,bcm2835";
model = "Raspberry Pi Model B";
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x10000000>;
+ };
+
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
@@ -89,6 +94,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&pwm {
@@ -97,6 +104,13 @@
status = "okay";
};
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
diff --git a/arch/arm/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/dts/bcm2835-rpi-cm1-io1.dts
index 4764a25585a..a75c882e657 100644
--- a/arch/arm/dts/bcm2835-rpi-cm1-io1.dts
+++ b/arch/arm/dts/bcm2835-rpi-cm1-io1.dts
@@ -79,6 +79,15 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
+};
+
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
};
&uart0 {
diff --git a/arch/arm/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/dts/bcm2835-rpi-cm1.dtsi
index ef22c2da783..e4e6b6abbfc 100644
--- a/arch/arm/dts/bcm2835-rpi-cm1.dtsi
+++ b/arch/arm/dts/bcm2835-rpi-cm1.dtsi
@@ -5,11 +5,16 @@
/ {
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x20000000>;
+ };
+
reg_3v3: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "3V3";
diff --git a/arch/arm/dts/bcm2835-rpi-common.dtsi b/arch/arm/dts/bcm2835-rpi-common.dtsi
new file mode 100644
index 00000000000..8a55b6cded5
--- /dev/null
+++ b/arch/arm/dts/bcm2835-rpi-common.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This include file covers the common peripherals and configuration between
+ * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's
+ * firmware interface.
+ */
+
+#include <dt-bindings/power/raspberrypi-power.h>
+
+&v3d {
+ power-domains = <&power RPI_POWER_DOMAIN_V3D>;
+};
diff --git a/arch/arm/dts/bcm2835-rpi-zero-w.dts b/arch/arm/dts/bcm2835-rpi-zero-w.dts
index ba0167df6c5..33b2b77aa47 100644
--- a/arch/arm/dts/bcm2835-rpi-zero-w.dts
+++ b/arch/arm/dts/bcm2835-rpi-zero-w.dts
@@ -12,14 +12,19 @@
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
model = "Raspberry Pi Zero W";
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x20000000>;
+ };
+
chosen {
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
};
leds {
- act {
- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
+ led-act {
+ gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
@@ -100,12 +105,16 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
+ pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
+ bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
status = "okay";
@@ -116,6 +125,13 @@
};
};
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
diff --git a/arch/arm/dts/bcm2835-rpi-zero.dts b/arch/arm/dts/bcm2835-rpi-zero.dts
index 3b35a8a4a55..6f9b3a908f2 100644
--- a/arch/arm/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/dts/bcm2835-rpi-zero.dts
@@ -12,8 +12,13 @@
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
model = "Raspberry Pi Zero";
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x20000000>;
+ };
+
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
};
@@ -96,6 +101,15 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
+};
+
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
};
&uart0 {
diff --git a/arch/arm/dts/bcm2835-rpi.dtsi b/arch/arm/dts/bcm2835-rpi.dtsi
index 715d50c6452..87ddcad7608 100644
--- a/arch/arm/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/dts/bcm2835-rpi.dtsi
@@ -1,15 +1,10 @@
#include <dt-bindings/power/raspberrypi-power.h>
/ {
- memory@0 {
- device_type = "memory";
- reg = <0 0x10000000>;
- };
-
leds {
compatible = "gpio-leds";
- act {
+ led-act {
label = "ACT";
default-state = "keep";
linux,default-trigger = "heartbeat";
@@ -18,8 +13,12 @@
soc {
firmware: firmware {
- compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
+ compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
mboxes = <&mailbox>;
+ dma-ranges;
};
power: power {
@@ -64,32 +63,10 @@
clock-frequency = <100000>;
};
-&i2c2 {
- status = "okay";
-};
-
-&sdhci {
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio48>;
- bus-width = <4>;
-};
-
-&sdhost {
- pinctrl-names = "default";
- pinctrl-0 = <&sdhost_gpio48>;
- status = "okay";
- bus-width = <4>;
-};
-
&usb {
power-domains = <&power RPI_POWER_DOMAIN_USB>;
};
-&hdmi {
- power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
- status = "okay";
-};
-
&vec {
power-domains = <&power RPI_POWER_DOMAIN_VEC>;
status = "okay";
diff --git a/arch/arm/dts/bcm2835.dtsi b/arch/arm/dts/bcm2835.dtsi
index a5c3824c805..0549686134e 100644
--- a/arch/arm/dts/bcm2835.dtsi
+++ b/arch/arm/dts/bcm2835.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
+#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2835";
diff --git a/arch/arm/dts/bcm2836-rpi-2-b.dts b/arch/arm/dts/bcm2836-rpi-2-b.dts
index 7b4e651bafd..d8af8eeac7b 100644
--- a/arch/arm/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/dts/bcm2836-rpi-2-b.dts
@@ -10,15 +10,16 @@
model = "Raspberry Pi 2 Model B";
memory@0 {
+ device_type = "memory";
reg = <0 0x40000000>;
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
@@ -105,6 +106,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&pwm {
@@ -113,6 +116,13 @@
status = "okay";
};
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
diff --git a/arch/arm/dts/bcm2836.dtsi b/arch/arm/dts/bcm2836.dtsi
index c933e841388..b390006aef7 100644
--- a/arch/arm/dts/bcm2836.dtsi
+++ b/arch/arm/dts/bcm2836.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
+#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2836";
diff --git a/arch/arm/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/dts/bcm2837-rpi-3-a-plus.dts
index 7f4437a8eed..77099a7871b 100644
--- a/arch/arm/dts/bcm2837-rpi-3-a-plus.dts
+++ b/arch/arm/dts/bcm2837-rpi-3-a-plus.dts
@@ -14,17 +14,20 @@
};
memory@0 {
+ device_type = "memory";
reg = <0 0x20000000>;
};
leds {
- act {
+ led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
};
};
};
@@ -117,6 +120,8 @@
&hdmi {
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&pwm {
diff --git a/arch/arm/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/dts/bcm2837-rpi-3-b-plus.dts
index c6fa34c2410..61010266ca9 100644
--- a/arch/arm/dts/bcm2837-rpi-3-b-plus.dts
+++ b/arch/arm/dts/bcm2837-rpi-3-b-plus.dts
@@ -15,17 +15,20 @@
};
memory@0 {
+ device_type = "memory";
reg = <0 0x40000000>;
};
leds {
- act {
+ led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
};
};
@@ -124,6 +127,8 @@
&hdmi {
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
&pwm {
diff --git a/arch/arm/dts/bcm2837-rpi-3-b.dts b/arch/arm/dts/bcm2837-rpi-3-b.dts
index ce71f578c51..dd4a4860409 100644
--- a/arch/arm/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/dts/bcm2837-rpi-3-b.dts
@@ -15,11 +15,12 @@
};
memory@0 {
+ device_type = "memory";
reg = <0 0x40000000>;
};
leds {
- act {
+ led-act {
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
@@ -125,6 +126,8 @@
&hdmi {
hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
};
/* uart0 communicates with the BT module */
diff --git a/arch/arm/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/dts/bcm2837-rpi-cm3-io3.dts
index 6c8233a36d8..588d9411ceb 100644
--- a/arch/arm/dts/bcm2837-rpi-cm3-io3.dts
+++ b/arch/arm/dts/bcm2837-rpi-cm3-io3.dts
@@ -78,6 +78,15 @@
&hdmi {
hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
+};
+
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ bus-width = <4>;
+ status = "okay";
};
&uart0 {
diff --git a/arch/arm/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/dts/bcm2837-rpi-cm3.dtsi
index 81399b2c5af..828a20561b9 100644
--- a/arch/arm/dts/bcm2837-rpi-cm3.dtsi
+++ b/arch/arm/dts/bcm2837-rpi-cm3.dtsi
@@ -5,9 +5,18 @@
/ {
memory@0 {
+ device_type = "memory";
reg = <0 0x40000000>;
};
+ leds {
+ /*
+ * Since there is no upstream GPIO driver yet,
+ * remove the incomplete node.
+ */
+ /delete-node/ led-act;
+ };
+
reg_3v3: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "3V3";
diff --git a/arch/arm/dts/bcm2837.dtsi b/arch/arm/dts/bcm2837.dtsi
index beb6c502dad..0199ec98cd6 100644
--- a/arch/arm/dts/bcm2837.dtsi
+++ b/arch/arm/dts/bcm2837.dtsi
@@ -1,4 +1,6 @@
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
+#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2837";
diff --git a/arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi
new file mode 100644
index 00000000000..0ff0e9e2532
--- /dev/null
+++ b/arch/arm/dts/bcm283x-rpi-usb-peripheral.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+&usb {
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <256 256 512 512 512 768 768>;
+};
diff --git a/arch/arm/dts/bcm283x.dtsi b/arch/arm/dts/bcm283x.dtsi
index 9777644c6c2..a3e06b68094 100644
--- a/arch/arm/dts/bcm283x.dtsi
+++ b/arch/arm/dts/bcm283x.dtsi
@@ -18,7 +18,6 @@
/ {
compatible = "brcm,bcm2835";
model = "BCM2835";
- interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
@@ -31,16 +30,27 @@
stdout-path = "serial0:115200n8";
};
+ rmem: reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x4000000>; /* 64MB */
+ reusable;
+ linux,cma-default;
+ };
+ };
+
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
- thermal-sensors = <&thermal>;
-
trips {
cpu-crit {
- temperature = <80000>;
+ temperature = <90000>;
hysteresis = <0>;
type = "critical";
};
@@ -56,7 +66,7 @@
#address-cells = <1>;
#size-cells = <1>;
- timer@7e003000 {
+ system_timer: timer@7e003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
@@ -67,74 +77,12 @@
clock-frequency = <1000000>;
};
- txp@7e004000 {
+ txp: txp@7e004000 {
compatible = "brcm,bcm2835-txp";
reg = <0x7e004000 0x20>;
interrupts = <1 11>;
};
- dma: dma@7e007000 {
- compatible = "brcm,bcm2835-dma";
- reg = <0x7e007000 0xf00>;
- interrupts = <1 16>,
- <1 17>,
- <1 18>,
- <1 19>,
- <1 20>,
- <1 21>,
- <1 22>,
- <1 23>,
- <1 24>,
- <1 25>,
- <1 26>,
- /* dma channel 11-14 share one irq */
- <1 27>,
- <1 27>,
- <1 27>,
- <1 27>,
- /* unused shared irq for all channels */
- <1 28>;
- interrupt-names = "dma0",
- "dma1",
- "dma2",
- "dma3",
- "dma4",
- "dma5",
- "dma6",
- "dma7",
- "dma8",
- "dma9",
- "dma10",
- "dma11",
- "dma12",
- "dma13",
- "dma14",
- "dma-shared-all";
- #dma-cells = <1>;
- brcm,dma-channel-mask = <0x7f35>;
- };
-
- intc: interrupt-controller@7e00b200 {
- compatible = "brcm,bcm2835-armctrl-ic";
- reg = <0x7e00b200 0x200>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pm: watchdog@7e100000 {
- compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
- #power-domain-cells = <1>;
- #reset-cells = <1>;
- reg = <0x7e100000 0x114>,
- <0x7e00a000 0x24>;
- clocks = <&clocks BCM2835_CLOCK_V3D>,
- <&clocks BCM2835_CLOCK_PERI_IMAGE>,
- <&clocks BCM2835_CLOCK_H264>,
- <&clocks BCM2835_CLOCK_ISP>;
- clock-names = "v3d", "peri_image", "h264", "isp";
- system-power-controller;
- };
-
clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
@@ -149,12 +97,6 @@
<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
};
- rng@7e104000 {
- compatible = "brcm,bcm2835-rng";
- reg = <0x7e104000 0x10>;
- interrupts = <2 29>;
- };
-
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
@@ -184,8 +126,7 @@
interrupt-controller;
#interrupt-cells = <2>;
- /* Defines pin muxing groups according to
- * BCM2835-ARM-Peripherals.pdf page 102.
+ /* Defines common pin muxing groups
*
* While each pin can have its mux selected
* for various functions individually, some
@@ -263,15 +204,7 @@
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
- i2c_slave_gpio18: i2c_slave_gpio18 {
- brcm,pins = <18 19 20 21>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
- jtag_gpio4: jtag_gpio4 {
- brcm,pins = <4 5 6 12 13>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT4>;
@@ -286,35 +219,6 @@
brcm,function = <BCM2835_FSEL_ALT2>;
};
- pwm0_gpio12: pwm0_gpio12 {
- brcm,pins = <12>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm0_gpio18: pwm0_gpio18 {
- brcm,pins = <18>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- pwm0_gpio40: pwm0_gpio40 {
- brcm,pins = <40>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio13: pwm1_gpio13 {
- brcm,pins = <13>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio19: pwm1_gpio19 {
- brcm,pins = <19>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- pwm1_gpio41: pwm1_gpio41 {
- brcm,pins = <41>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio45: pwm1_gpio45 {
- brcm,pins = <45>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
-
sdhost_gpio48: sdhost_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT0>;
@@ -396,8 +300,8 @@
};
uart0: serial@7e201000 {
- compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
- reg = <0x7e201000 0x1000>;
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201000 0x200>;
interrupts = <2 25>;
clocks = <&clocks BCM2835_CLOCK_UART>,
<&clocks BCM2835_CLOCK_VPU>;
@@ -410,8 +314,6 @@
reg = <0x7e202000 0x100>;
interrupts = <2 24>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
- dmas = <&dma 13>;
- dma-names = "rx-tx";
status = "disabled";
};
@@ -419,16 +321,12 @@
compatible = "brcm,bcm2835-i2s";
reg = <0x7e203000 0x24>;
clocks = <&clocks BCM2835_CLOCK_PCM>;
-
- dmas = <&dma 2>,
- <&dma 3>;
- dma-names = "tx", "rx";
status = "disabled";
};
spi: spi@7e204000 {
compatible = "brcm,bcm2835-spi";
- reg = <0x7e204000 0x1000>;
+ reg = <0x7e204000 0x200>;
interrupts = <2 22>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
@@ -438,7 +336,7 @@
i2c0: i2c@7e205000 {
compatible = "brcm,bcm2835-i2c";
- reg = <0x7e205000 0x1000>;
+ reg = <0x7e205000 0x200>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
@@ -446,18 +344,6 @@
status = "disabled";
};
- pixelvalve@7e206000 {
- compatible = "brcm,bcm2835-pixelvalve0";
- reg = <0x7e206000 0x100>;
- interrupts = <2 13>; /* pwa0 */
- };
-
- pixelvalve@7e207000 {
- compatible = "brcm,bcm2835-pixelvalve1";
- reg = <0x7e207000 0x100>;
- interrupts = <2 14>; /* pwa1 */
- };
-
dpi: dpi@7e208000 {
compatible = "brcm,bcm2835-dpi";
reg = <0x7e208000 0x8c>;
@@ -486,13 +372,6 @@
"dsi0_ddr2",
"dsi0_ddr";
- };
-
- thermal: thermal@7e212000 {
- compatible = "brcm,bcm2835-thermal";
- reg = <0x7e212000 0x8>;
- clocks = <&clocks BCM2835_CLOCK_TSENS>;
- #thermal-sensor-cells = <0>;
status = "disabled";
};
@@ -541,7 +420,7 @@
status = "disabled";
};
- sdhci: sdhci@7e300000 {
+ sdhci: mmc@7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
@@ -585,44 +464,6 @@
status = "disabled";
};
- i2c2: i2c@7e805000 {
- compatible = "brcm,bcm2835-i2c";
- reg = <0x7e805000 0x1000>;
- interrupts = <2 21>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vec: vec@7e806000 {
- compatible = "brcm,bcm2835-vec";
- reg = <0x7e806000 0x1000>;
- clocks = <&clocks BCM2835_CLOCK_VEC>;
- interrupts = <2 27>;
- status = "disabled";
- };
-
- pixelvalve@7e807000 {
- compatible = "brcm,bcm2835-pixelvalve2";
- reg = <0x7e807000 0x100>;
- interrupts = <2 10>; /* pixelvalve */
- };
-
- hdmi: hdmi@7e902000 {
- compatible = "brcm,bcm2835-hdmi";
- reg = <0x7e902000 0x600>,
- <0x7e808000 0x100>;
- interrupts = <2 8>, <2 9>;
- ddc = <&i2c2>;
- clocks = <&clocks BCM2835_PLLH_PIX>,
- <&clocks BCM2835_CLOCK_HSM>;
- clock-names = "pixel", "hdmi";
- dmas = <&dma 17>;
- dma-names = "audio-rx";
- status = "disabled";
- };
-
usb: usb@7e980000 {
compatible = "brcm,bcm2835-usb";
reg = <0x7e980000 0x10000>;
@@ -634,36 +475,19 @@
phys = <&usbphy>;
phy-names = "usb2-phy";
};
-
- v3d: v3d@7ec00000 {
- compatible = "brcm,bcm2835-v3d";
- reg = <0x7ec00000 0x1000>;
- interrupts = <1 10>;
- power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
- };
-
- vc4: gpu {
- compatible = "brcm,bcm2835-vc4";
- };
};
clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
/* The oscillator is the root of the clock tree. */
- clk_osc: clock@3 {
+ clk_osc: clk-osc {
compatible = "fixed-clock";
- reg = <3>;
#clock-cells = <0>;
clock-output-names = "osc";
clock-frequency = <19200000>;
};
- clk_usb: clock@4 {
+ clk_usb: clk-usb {
compatible = "fixed-clock";
- reg = <4>;
#clock-cells = <0>;
clock-output-names = "otg";
clock-frequency = <480000000>;
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 88f7504a60f..0d534b8a28d 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_RPI_4_32B=y
CONFIG_ENV_SIZE=0x4000
+CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 59a71031540..0b3cadaced2 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00080000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_RPI_4=y
CONFIG_ENV_SIZE=0x4000
+CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index 67dbf094ef7..0b5f766cfe7 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00080000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_RPI_ARM64=y
CONFIG_ENV_SIZE=0x4000
+CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x1000000
CONFIG_OF_BOARD_SETUP=y
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 2cec01f9689..b60c03430cf 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -58,3 +58,5 @@
#define BCM2835_CLOCK_DSI1E 48
#define BCM2835_CLOCK_DSI0P 49
#define BCM2835_CLOCK_DSI1P 50
+
+#define BCM2711_CLOCK_EMMC2 51
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 07/32] arm: vexpress: Add a devicetree files for juno
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (5 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 06/32] arm: rpi: Sync rpi dts files from Linux Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-18 3:30 ` Linus Walleij
2021-12-17 3:59 ` [PATCH v8 08/32] arm: xenguest_arm64: Add a empty devicetree file Simon Glass
` (24 subsequent siblings)
31 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud,
Linus Walleij
Sync these file, obtained from Linux v5.15.
Add a note for the maintainer, and SPDX lines where they are missing.
The added lines are:
SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
Note, this matches the text in those files, but is not the same as the
GPL-2.0 of some files.
[1] https://releases.linaro.org/android/reference-lcr/juno/7.1-17.05/
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Enable the flash as suggested by Linus Walleij
Changes in v7:
- Bring in files from Linux instead
- Rewrite the commit message
arch/arm/dts/Makefile | 3 +
arch/arm/dts/juno-base.dtsi | 831 +++++++++++++++++++++++++
arch/arm/dts/juno-clocks.dtsi | 46 ++
arch/arm/dts/juno-cs-r1r2.dtsi | 85 +++
arch/arm/dts/juno-motherboard.dtsi | 303 +++++++++
arch/arm/dts/juno-r2-u-boot.dtsi | 20 +
arch/arm/dts/juno-r2.dts | 322 ++++++++++
configs/vexpress_aemv8a_juno_defconfig | 1 +
8 files changed, 1611 insertions(+)
create mode 100644 arch/arm/dts/juno-base.dtsi
create mode 100644 arch/arm/dts/juno-clocks.dtsi
create mode 100644 arch/arm/dts/juno-cs-r1r2.dtsi
create mode 100644 arch/arm/dts/juno-motherboard.dtsi
create mode 100644 arch/arm/dts/juno-r2-u-boot.dtsi
create mode 100644 arch/arm/dts/juno-r2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9cddab37207..d53bae2c350 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1149,7 +1149,10 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
+# TODO(Linus Walleij <linus.walleij@linaro.org>): Should us a single vexpress
+# Kconfig option to build all of these. See examples above.
dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
+dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb
dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
diff --git a/arch/arm/dts/juno-base.dtsi b/arch/arm/dts/juno-base.dtsi
new file mode 100644
index 00000000000..6288e104a08
--- /dev/null
+++ b/arch/arm/dts/juno-base.dtsi
@@ -0,0 +1,831 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "juno-clocks.dtsi"
+#include "juno-motherboard.dtsi"
+
+/ {
+ /*
+ * Devices shared by all Juno boards
+ */
+
+ memtimer: timer@2a810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x2a810000 0x0 0x10000>;
+ clock-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x2a820000 0x20000>;
+ status = "disabled";
+ frame@2a830000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x10000 0x10000>;
+ };
+ };
+
+ mailbox: mhu@2b1f0000 {
+ compatible = "arm,mhu", "arm,primecell";
+ reg = <0x0 0x2b1f0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ clocks = <&soc_refclk100mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ smmu_gpu: iommu@2b400000 {
+ compatible = "arm,mmu-400", "arm,smmu-v1";
+ reg = <0x0 0x2b400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ power-domains = <&scpi_devpd 1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ smmu_pcie: iommu@2b500000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x2b500000 0x0 0x10000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ smmu_etr: iommu@2b600000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x2b600000 0x0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ power-domains = <&scpi_devpd 0>;
+ };
+
+ gic: interrupt-controller@2c010000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ reg = <0x0 0x2c010000 0 0x1000>,
+ <0x0 0x2c02f000 0 0x2000>,
+ <0x0 0x2c04f000 0 0x2000>,
+ <0x0 0x2c06f000 0 0x2000>;
+ #address-cells = <1>;
+ #interrupt-cells = <3>;
+ #size-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ ranges = <0 0 0x2c1c0000 0x40000>;
+
+ v2m_0: v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0 0x10000>;
+ };
+
+ v2m@10000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x10000 0x10000>;
+ };
+
+ v2m@20000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x20000 0x10000>;
+ };
+
+ v2m@30000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x30000 0x10000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ /*
+ * Juno TRMs specify the size for these coresight components as 64K.
+ * The actual size is just 4K though 64K is reserved. Access to the
+ * unmapped reserved region results in a DECERR response.
+ */
+ etf@20010000 { /* etf0 */
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20010000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+
+ in-ports {
+ port {
+ etf0_in_port: endpoint {
+ remote-endpoint = <&main_funnel_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf0_out_port: endpoint {
+ };
+ };
+ };
+ };
+
+ tpiu@20030000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0x20030000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+ };
+
+ /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
+ main_funnel: funnel@20040000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x20040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+
+ out-ports {
+ port {
+ main_funnel_out_port: endpoint {
+ remote-endpoint = <&etf0_in_port>;
+ };
+ };
+ };
+
+ main_funnel_in_ports: in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ main_funnel_in_port0: endpoint {
+ remote-endpoint = <&cluster0_funnel_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ main_funnel_in_port1: endpoint {
+ remote-endpoint = <&cluster1_funnel_out_port>;
+ };
+ };
+ };
+ };
+
+ etr@20070000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20070000 0 0x1000>;
+ iommus = <&smmu_etr 0>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ arm,scatter-gather;
+ in-ports {
+ port {
+ etr_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+ };
+
+ stm@20100000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x20100000 0 0x1000>,
+ <0 0x28000000 0 0x1000000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ stm_out_port: endpoint {
+ };
+ };
+ };
+ };
+
+ replicator@20120000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x20120000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+ };
+ in-ports {
+ port {
+ replicator_in_port0: endpoint {
+ };
+ };
+ };
+ };
+
+ cpu_debug0: cpu-debug@22010000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x22010000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
+ etm0: etm@22040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x22040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ cluster0_etm0_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@220c0000 { /* cluster0 funnel */
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x220c0000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ cluster0_funnel_out_port: endpoint {
+ remote-endpoint = <&main_funnel_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster0_funnel_in_port0: endpoint {
+ remote-endpoint = <&cluster0_etm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ cluster0_funnel_in_port1: endpoint {
+ remote-endpoint = <&cluster0_etm1_out_port>;
+ };
+ };
+ };
+ };
+
+ cpu_debug1: cpu-debug@22110000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x22110000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
+ etm1: etm@22140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x22140000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ cluster0_etm1_out_port: endpoint {
+ remote-endpoint = <&cluster0_funnel_in_port1>;
+ };
+ };
+ };
+ };
+
+ cpu_debug2: cpu-debug@23010000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x23010000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
+ etm2: etm@23040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23040000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ cluster1_etm0_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@230c0000 { /* cluster1 funnel */
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x230c0000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ cluster1_funnel_out_port: endpoint {
+ remote-endpoint = <&main_funnel_in_port1>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster1_funnel_in_port0: endpoint {
+ remote-endpoint = <&cluster1_etm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ cluster1_funnel_in_port1: endpoint {
+ remote-endpoint = <&cluster1_etm1_out_port>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ cluster1_funnel_in_port2: endpoint {
+ remote-endpoint = <&cluster1_etm2_out_port>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ cluster1_funnel_in_port3: endpoint {
+ remote-endpoint = <&cluster1_etm3_out_port>;
+ };
+ };
+ };
+ };
+
+ cpu_debug3: cpu-debug@23110000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x23110000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
+ etm3: etm@23140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23140000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ cluster1_etm1_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port1>;
+ };
+ };
+ };
+ };
+
+ cpu_debug4: cpu-debug@23210000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x23210000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
+ etm4: etm@23240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23240000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ cluster1_etm2_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port2>;
+ };
+ };
+ };
+ };
+
+ cpu_debug5: cpu-debug@23310000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x23310000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
+ etm5: etm@23340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x23340000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ cluster1_etm3_out_port: endpoint {
+ remote-endpoint = <&cluster1_funnel_in_port3>;
+ };
+ };
+ };
+ };
+
+ gpu: gpu@2d000000 {
+ compatible = "arm,juno-mali", "arm,mali-t624";
+ reg = <0 0x2d000000 0 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&scpi_dvfs 2>;
+ power-domains = <&scpi_devpd 1>;
+ dma-coherent;
+ /* The SMMU is only really of interest to bare-metal hypervisors */
+ /* iommus = <&smmu_gpu 0>; */
+ status = "disabled";
+ };
+
+ sram: sram@2e000000 {
+ compatible = "arm,juno-sram-ns", "mmio-sram";
+ reg = <0x0 0x2e000000 0x0 0x8000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x2e000000 0x8000>;
+
+ cpu_scp_lpri: scp-sram@0 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-sram@200 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x200 0x200>;
+ };
+ };
+
+ pcie_ctlr: pcie@40000000 {
+ compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
+ device_type = "pci";
+ reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
+ bus-range = <0 255>;
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
+ <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
+ <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
+ /* Standard AXI Translation entries as programmed by EDK2 */
+ dma-ranges = <0x02000000 0x0 0x2c1c0000 0x0 0x2c1c0000 0x0 0x00040000>,
+ <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
+ <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ msi-parent = <&v2m_0>;
+ status = "disabled";
+ iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
+ iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
+ };
+
+ scpi {
+ compatible = "arm,scpi";
+ mboxes = <&mailbox 1>;
+ shmem = <&cpu_scp_hpri>;
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: clocks-0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>, <1>, <2>;
+ clock-output-names = "atlclk", "aplclk","gpuclk";
+ };
+ scpi_clk: clocks-1 {
+ compatible = "arm,scpi-variable-clocks";
+ #clock-cells = <1>;
+ clock-indices = <3>;
+ clock-output-names = "pxlclk";
+ };
+ };
+
+ scpi_devpd: power-controller {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
+
+ scpi_sensors0: sensors {
+ compatible = "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ pmic {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scpi_sensors0 0>;
+ };
+
+ soc {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scpi_sensors0 3>;
+ };
+
+ big_cluster_thermal_zone: big-cluster {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scpi_sensors0 21>;
+ status = "disabled";
+ };
+
+ little_cluster_thermal_zone: little-cluster {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scpi_sensors0 22>;
+ status = "disabled";
+ };
+
+ gpu0_thermal_zone: gpu0 {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scpi_sensors0 23>;
+ status = "disabled";
+ };
+
+ gpu1_thermal_zone: gpu1 {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scpi_sensors0 24>;
+ status = "disabled";
+ };
+ };
+
+ smmu_dma: iommu@7fb00000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x7fb00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ };
+
+ smmu_hdlcd1: iommu@7fb10000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x7fb10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ };
+
+ smmu_hdlcd0: iommu@7fb20000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x7fb20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ };
+
+ smmu_usb: iommu@7fb30000 {
+ compatible = "arm,mmu-401", "arm,smmu-v1";
+ reg = <0x0 0x7fb30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ };
+
+ dma@7ff00000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x7ff00000 0 0x1000>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_dma 0>,
+ <&smmu_dma 1>,
+ <&smmu_dma 2>,
+ <&smmu_dma 3>,
+ <&smmu_dma 4>,
+ <&smmu_dma 5>,
+ <&smmu_dma 6>,
+ <&smmu_dma 7>,
+ <&smmu_dma 8>;
+ clocks = <&soc_faxiclk>;
+ clock-names = "apb_pclk";
+ };
+
+ hdlcd@7ff50000 {
+ compatible = "arm,hdlcd";
+ reg = <0 0x7ff50000 0 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_hdlcd1 0>;
+ clocks = <&scpi_clk 3>;
+ clock-names = "pxlclk";
+
+ port {
+ hdlcd1_output: endpoint {
+ remote-endpoint = <&tda998x_1_input>;
+ };
+ };
+ };
+
+ hdlcd@7ff60000 {
+ compatible = "arm,hdlcd";
+ reg = <0 0x7ff60000 0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_hdlcd0 0>;
+ clocks = <&scpi_clk 3>;
+ clock-names = "pxlclk";
+
+ port {
+ hdlcd0_output: endpoint {
+ remote-endpoint = <&tda998x_0_input>;
+ };
+ };
+ };
+
+ soc_uart0: serial@7ff80000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x7ff80000 0x0 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ i2c@7ffa0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x7ffa0000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ i2c-sda-hold-time-ns = <500>;
+ clocks = <&soc_smc50mhz>;
+
+ hdmi-transmitter@70 {
+ compatible = "nxp,tda998x";
+ reg = <0x70>;
+ port {
+ tda998x_0_input: endpoint {
+ remote-endpoint = <&hdlcd0_output>;
+ };
+ };
+ };
+
+ hdmi-transmitter@71 {
+ compatible = "nxp,tda998x";
+ reg = <0x71>;
+ port {
+ tda998x_1_input: endpoint {
+ remote-endpoint = <&hdlcd1_output>;
+ };
+ };
+ };
+ };
+
+ usb@7ffb0000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0x7ffb0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_usb 0>;
+ clocks = <&soc_usb48mhz>;
+ };
+
+ usb@7ffc0000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0x7ffc0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&smmu_usb 0>;
+ clocks = <&soc_usb48mhz>;
+ };
+
+ memory-controller@7ffd0000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0 0x7ffd0000 0 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* last 16MB of the first memory area is reserved for secure world use by firmware */
+ reg = <0x00000000 0x80000000 0x0 0x7f000000>,
+ <0x00000008 0x80000000 0x1 0x80000000>;
+ };
+
+ bus@8000000 {
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 15>;
+ interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ site2: tlx-bus@60000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x60000000 0x10000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0>;
+ interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/arm/dts/juno-clocks.dtsi b/arch/arm/dts/juno-clocks.dtsi
new file mode 100644
index 00000000000..b0f8ccaac9e
--- /dev/null
+++ b/arch/arm/dts/juno-clocks.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * ARM Juno Platform clocks
+ *
+ * Copyright (c) 2013-2014 ARM Ltd
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ *
+ */
+/ {
+ /* SoC fixed clocks */
+ soc_uartclk: refclk7372800hz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <7372800>;
+ clock-output-names = "juno:uartclk";
+ };
+
+ soc_usb48mhz: clk48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ clock-output-names = "clk48mhz";
+ };
+
+ soc_smc50mhz: clk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "smc_clk";
+ };
+
+ soc_refclk100mhz: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ soc_faxiclk: refclk400mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "faxi_clk";
+ };
+};
diff --git a/arch/arm/dts/juno-cs-r1r2.dtsi b/arch/arm/dts/juno-cs-r1r2.dtsi
new file mode 100644
index 00000000000..eda3d9e18af
--- /dev/null
+++ b/arch/arm/dts/juno-cs-r1r2.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+ funnel@20130000 { /* cssys1 */
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x20130000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ csys1_funnel_out_port: endpoint {
+ remote-endpoint = <&etf1_in_port>;
+ };
+ };
+ };
+ in-ports {
+ port {
+ csys1_funnel_in_port0: endpoint {
+ };
+ };
+
+ };
+ };
+
+ etf@20140000 { /* etf1 */
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20140000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ in-ports {
+ port {
+ etf1_in_port: endpoint {
+ remote-endpoint = <&csys1_funnel_out_port>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ etf1_out_port: endpoint {
+ remote-endpoint = <&csys2_funnel_in_port1>;
+ };
+ };
+ };
+ };
+
+ funnel@20150000 { /* cssys2 */
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x20150000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ out-ports {
+ port {
+ csys2_funnel_out_port: endpoint {
+ remote-endpoint = <&replicator_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ csys2_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csys2_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf1_out_port>;
+ };
+ };
+
+ };
+ };
+};
diff --git a/arch/arm/dts/juno-motherboard.dtsi b/arch/arm/dts/juno-motherboard.dtsi
new file mode 100644
index 00000000000..42b17542ab1
--- /dev/null
+++ b/arch/arm/dts/juno-motherboard.dtsi
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * ARM Juno Platform motherboard peripherals
+ *
+ * Copyright (c) 2013-2014 ARM Ltd
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ *
+ */
+
+/ {
+ mb_clk24mhz: clk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "juno_mb:clk24mhz";
+ };
+
+ mb_clk25mhz: clk25mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "juno_mb:clk25mhz";
+ };
+
+ v2m_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "juno_mb:refclk1mhz";
+ };
+
+ v2m_refclk32khz: refclk32khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "juno_mb:refclk32khz";
+ };
+
+ mb_fixed_3v3: mcc-sb-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "MCC_SB_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power-button {
+ debounce-interval = <50>;
+ wakeup-source;
+ linux,code = <116>;
+ label = "POWER";
+ gpios = <&iofpga_gpio0 0 0x4>;
+ };
+ home-button {
+ debounce-interval = <50>;
+ wakeup-source;
+ linux,code = <102>;
+ label = "HOME";
+ gpios = <&iofpga_gpio0 1 0x4>;
+ };
+ rlock-button {
+ debounce-interval = <50>;
+ wakeup-source;
+ linux,code = <152>;
+ label = "RLOCK";
+ gpios = <&iofpga_gpio0 2 0x4>;
+ };
+ vol-up-button {
+ debounce-interval = <50>;
+ wakeup-source;
+ linux,code = <115>;
+ label = "VOL+";
+ gpios = <&iofpga_gpio0 3 0x4>;
+ };
+ vol-down-button {
+ debounce-interval = <50>;
+ wakeup-source;
+ linux,code = <114>;
+ label = "VOL-";
+ gpios = <&iofpga_gpio0 4 0x4>;
+ };
+ nmi-button {
+ debounce-interval = <50>;
+ wakeup-source;
+ linux,code = <99>;
+ label = "NMI";
+ gpios = <&iofpga_gpio0 5 0x4>;
+ };
+ };
+
+ bus@8000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x8000000 0 0x8000000 0x18000000>;
+
+ motherboard-bus@8000000 {
+ compatible = "arm,vexpress,v2p-p1", "simple-bus";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ ranges = <0 0 0 0x08000000 0x04000000>,
+ <1 0 0 0x14000000 0x04000000>,
+ <2 0 0 0x18000000 0x04000000>,
+ <3 0 0 0x1c000000 0x04000000>,
+ <4 0 0 0x0c000000 0x04000000>,
+ <5 0 0 0x10000000 0x04000000>;
+ arm,hbi = <0x252>;
+ arm,vexpress,site = <0>;
+
+ flash@0 {
+ /* 2 * 32MiB NOR Flash memory mounted on CS0 */
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>;
+ bank-width = <4>;
+ /*
+ * Unfortunately, accessing the flash disturbs
+ * the CPU idle states (suspend) and CPU
+ * hotplug of the platform. For this reason,
+ * flash hardware access is disabled by default.
+ */
+ status = "disabled";
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
+ };
+
+ ethernet@200000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <2 0x00000000 0x10000>;
+ interrupts = <3>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ clocks = <&mb_clk25mhz>;
+ vdd33a-supply = <&mb_fixed_3v3>;
+ vddvario-supply = <&mb_fixed_3v3>;
+ };
+
+ iofpga-bus@300000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 3 0 0x200000>;
+
+ v2m_sysctl: sysctl@20000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
+ clock-names = "refclk", "timclk", "apb_pclk";
+ #clock-cells = <1>;
+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+ assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
+ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
+ };
+
+ apbregs@10000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x010000 0x1000>;
+
+ led0 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x01>;
+ label = "vexpress:0";
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+ led1 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x02>;
+ label = "vexpress:1";
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+ led2 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x04>;
+ label = "vexpress:2";
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+ led3 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x08>;
+ label = "vexpress:3";
+ linux,default-trigger = "cpu1";
+ default-state = "off";
+ };
+ led4 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x10>;
+ label = "vexpress:4";
+ linux,default-trigger = "cpu2";
+ default-state = "off";
+ };
+ led5 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x20>;
+ label = "vexpress:5";
+ linux,default-trigger = "cpu3";
+ default-state = "off";
+ };
+ led6 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x40>;
+ label = "vexpress:6";
+ default-state = "off";
+ };
+ led7 {
+ compatible = "register-bit-led";
+ offset = <0x08>;
+ mask = <0x80>;
+ label = "vexpress:7";
+ default-state = "off";
+ };
+ };
+
+ mmc@50000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x050000 0x1000>;
+ interrupts = <5>;
+ /* cd-gpios = <&v2m_mmc_gpios 0 0>;
+ wp-gpios = <&v2m_mmc_gpios 1 0>; */
+ max-frequency = <12000000>;
+ vmmc-supply = <&mb_fixed_3v3>;
+ clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+ clock-names = "mclk", "apb_pclk";
+ };
+
+ kmi@60000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x060000 0x1000>;
+ interrupts = <8>;
+ clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ kmi@70000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x070000 0x1000>;
+ interrupts = <8>;
+ clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ watchdog@f0000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f0000 0x10000>;
+ interrupts = <7>;
+ clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+ clock-names = "wdog_clk", "apb_pclk";
+ };
+
+ v2m_timer01: timer@110000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x110000 0x10000>;
+ interrupts = <9>;
+ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
+ };
+
+ v2m_timer23: timer@120000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x120000 0x10000>;
+ interrupts = <9>;
+ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
+ };
+
+ rtc@170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x170000 0x10000>;
+ interrupts = <0>;
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ iofpga_gpio0: gpio@1d0000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x1d0000 0x1000>;
+ interrupts = <6>;
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/juno-r2-u-boot.dtsi b/arch/arm/dts/juno-r2-u-boot.dtsi
new file mode 100644
index 00000000000..72790666bb8
--- /dev/null
+++ b/arch/arm/dts/juno-r2-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * ARM Juno Platform additions for U-Boot
+ */
+
+/ {
+ bus@8000000 {
+ motherboard-bus@8000000 {
+ /*
+ * This should not be marked "disabled" in U-Boot. The
+ * boot loader is not using some CPU idle states and
+ * hotplug but may be very interested in accessing the
+ * flash.
+ */
+ flash@0 {
+ status = "okay";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/juno-r2.dts b/arch/arm/dts/juno-r2.dts
new file mode 100644
index 00000000000..52a6517d165
--- /dev/null
+++ b/arch/arm/dts/juno-r2.dts
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * ARM Ltd. Juno Platform
+ *
+ * Copyright (c) 2015 ARM Ltd.
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "juno-base.dtsi"
+#include "juno-cs-r1r2.dtsi"
+
+/ {
+ model = "ARM Juno development board (r2)";
+ compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &soc_uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&A72_0>;
+ };
+ core1 {
+ cpu = <&A72_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&A53_0>;
+ };
+ core1 {
+ cpu = <&A53_1>;
+ };
+ core2 {
+ cpu = <&A53_2>;
+ };
+ core3 {
+ cpu = <&A53_3>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2000>;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x1010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2500>;
+ };
+ };
+
+ A72_0: cpu@0 {
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&A72_L2>;
+ clocks = <&scpi_dvfs 0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <450>;
+ };
+
+ A72_1: cpu@1 {
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&A72_L2>;
+ clocks = <&scpi_dvfs 0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <450>;
+ };
+
+ A53_0: cpu@100 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <485>;
+ dynamic-power-coefficient = <140>;
+ };
+
+ A53_1: cpu@101 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x101>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <485>;
+ dynamic-power-coefficient = <140>;
+ };
+
+ A53_2: cpu@102 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x102>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <485>;
+ dynamic-power-coefficient = <140>;
+ };
+
+ A53_3: cpu@103 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x103>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <485>;
+ dynamic-power-coefficient = <140>;
+ };
+
+ A72_L2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ };
+
+ A53_L2: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ };
+ };
+
+ pmu-a72 {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&A72_0>,
+ <&A72_1>;
+ };
+
+ pmu-a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&A53_0>,
+ <&A53_1>,
+ <&A53_2>,
+ <&A53_3>;
+ };
+};
+
+&memtimer {
+ status = "okay";
+};
+
+&pcie_ctlr {
+ status = "okay";
+};
+
+&smmu_pcie {
+ status = "okay";
+};
+
+&etm0 {
+ cpu = <&A72_0>;
+};
+
+&etm1 {
+ cpu = <&A72_1>;
+};
+
+&etm2 {
+ cpu = <&A53_0>;
+};
+
+&etm3 {
+ cpu = <&A53_1>;
+};
+
+&etm4 {
+ cpu = <&A53_2>;
+};
+
+&etm5 {
+ cpu = <&A53_3>;
+};
+
+&big_cluster_thermal_zone {
+ status = "okay";
+};
+
+&little_cluster_thermal_zone {
+ status = "okay";
+};
+
+&gpu0_thermal_zone {
+ status = "okay";
+};
+
+&gpu1_thermal_zone {
+ status = "okay";
+};
+
+&etf0_out_port {
+ remote-endpoint = <&csys2_funnel_in_port0>;
+};
+
+&replicator_in_port0 {
+ remote-endpoint = <&csys2_funnel_out_port>;
+};
+
+&csys1_funnel_in_port0 {
+ remote-endpoint = <&stm_out_port>;
+};
+
+&stm_out_port {
+ remote-endpoint = <&csys1_funnel_in_port0>;
+};
+
+&cpu_debug0 {
+ cpu = <&A72_0>;
+};
+
+&cpu_debug1 {
+ cpu = <&A72_1>;
+};
+
+&cpu_debug2 {
+ cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+ cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+ cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+ cpu = <&A53_3>;
+};
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index f6ff0e0a569..0ccd990b80b 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="juno-r2"
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x90000000
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v8 07/32] arm: vexpress: Add a devicetree files for juno
2021-12-17 3:59 ` [PATCH v8 07/32] arm: vexpress: Add a devicetree files for juno Simon Glass
@ 2021-12-18 3:30 ` Linus Walleij
0 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2021-12-18 3:30 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Ilias Apalodimas, Sean Anderson,
Heinrich Schuchardt, Tom Rini, Mark Kettenis, François Ozog,
Albert Aribaud
On Fri, Dec 17, 2021 at 5:00 AM Simon Glass <sjg@chromium.org> wrote:
> Sync these file, obtained from Linux v5.15.
>
> Add a note for the maintainer, and SPDX lines where they are missing.
> The added lines are:
>
> SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
>
> Note, this matches the text in those files, but is not the same as the
> GPL-2.0 of some files.
>
> [1] https://releases.linaro.org/android/reference-lcr/juno/7.1-17.05/
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v8:
> - Enable the flash as suggested by Linus Walleij
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v8 08/32] arm: xenguest_arm64: Add a empty devicetree file
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (6 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 07/32] arm: vexpress: Add a devicetree files for juno Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 09/32] arm: octeontx: Add an " Simon Glass
` (23 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud,
Anastasiia Lukianenko, Oleksandr Andrushchenko
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.
The real devicetree is created by the Xen project on-the-fly.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Reword commit message to mention the dynamic devicetree
Changes in v7:
- Use 'empty' instead of 'fake'
arch/arm/dts/Makefile | 2 ++
arch/arm/dts/xenguest-arm64.dts | 15 +++++++++++++++
configs/xenguest_arm64_defconfig | 2 +-
3 files changed, 18 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/xenguest-arm64.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d53bae2c350..f6345988c8c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1140,6 +1140,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
+dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
+
dtb-$(CONFIG_TARGET_GE_BX50V3) += \
imx6q-bx50v3.dtb \
imx6q-b850v3.dtb \
diff --git a/arch/arm/dts/xenguest-arm64.dts b/arch/arm/dts/xenguest-arm64.dts
new file mode 100644
index 00000000000..d8734433763
--- /dev/null
+++ b/arch/arm/dts/xenguest-arm64.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Empty devicetree file for xenguest_arm64
+ *
+ * This is required to make the board build with CONFIG OF_SEPARATE
+ * Build instructions at xenguest_arm64.rst are inadequate for obtaining a real
+ * devicetree.
+ *
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+
+/ {
+};
diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig
index 8d9d9133a2e..edce34346d3 100644
--- a/configs/xenguest_arm64_defconfig
+++ b/configs/xenguest_arm64_defconfig
@@ -3,7 +3,7 @@ CONFIG_POSITION_INDEPENDENT=y
CONFIG_TARGET_XENGUEST_ARM64=y
CONFIG_SYS_TEXT_BASE=0x40080000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="xenguest-arm64"
CONFIG_IDENT_STRING=" xenguest"
CONFIG_SYS_LOAD_ADDR=0x40000000
CONFIG_BOOTDELAY=10
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 09/32] arm: octeontx: Add an empty devicetree file
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (7 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 08/32] arm: xenguest_arm64: Add a empty devicetree file Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 10/32] arm: xilinx_versal_virt: Add a " Simon Glass
` (22 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Aaron Williams,
Albert Aribaud
Add an empty file to prevent build errors when building with
CONFIG_OF_SEPARATE enabled.
Unfortunately there are no build instructions in the U-Boot tree to enable
a real file to be created.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Use 'empty' instead of 'fake'
arch/arm/dts/Makefile | 3 +++
arch/arm/dts/octeontx.dts | 14 ++++++++++++++
configs/octeontx2_95xx_defconfig | 1 +
configs/octeontx2_96xx_defconfig | 1 +
configs/octeontx_81xx_defconfig | 1 +
configs/octeontx_83xx_defconfig | 1 +
6 files changed, 21 insertions(+)
create mode 100644 arch/arm/dts/octeontx.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f6345988c8c..91302118598 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1142,6 +1142,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
+dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb
+dtb-$(CONFIG_ARCH_OCTEONTX2) += octeontx.dtb
+
dtb-$(CONFIG_TARGET_GE_BX50V3) += \
imx6q-bx50v3.dtb \
imx6q-b850v3.dtb \
diff --git a/arch/arm/dts/octeontx.dts b/arch/arm/dts/octeontx.dts
new file mode 100644
index 00000000000..60a15f5df23
--- /dev/null
+++ b/arch/arm/dts/octeontx.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Dummy devicetre file for octeontx2 boards
+ *
+ * This is required to make the board build with CONFIG OF_SEPARATE
+ * I could not find any in-tree documentation at all so this is a dummy file.
+ *
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+
+/ {
+};
diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index e1b86a5a8b6..e3df390c94b 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX2_95XX=y
CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="octeontx"
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index ec03d959771..0478b3068a6 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX2_96XX=y
CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="octeontx"
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index d0728ac3c67..d871be8f812 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX_81XX=y
CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="octeontx"
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index 6c9609b0cd3..94b072bf6fa 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0xF00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_TARGET_OCTEONTX_83XX=y
CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="octeontx"
CONFIG_DEBUG_UART_BASE=0x87e028000000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 10/32] arm: xilinx_versal_virt: Add a devicetree file
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (8 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 09/32] arm: octeontx: Add an " Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 11/32] arm: bcm7xxx: " Simon Glass
` (21 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud,
Michal Simek
Add an empty file to prevent build errors when building with
CONFIG_OF_SEPARATE enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/dts/Makefile | 3 ++-
arch/arm/dts/xilinx-versal-virt.dts | 11 +++++++++++
configs/xilinx_versal_virt_defconfig | 1 +
3 files changed, 14 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/xilinx-versal-virt.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 91302118598..b07a1b3378e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -360,7 +360,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini.dtb \
versal-mini-emmc0.dtb \
- versal-mini-emmc1.dtb
+ versal-mini-emmc1.dtb \
+ xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
dtb-$(CONFIG_AM33XX) += \
diff --git a/arch/arm/dts/xilinx-versal-virt.dts b/arch/arm/dts/xilinx-versal-virt.dts
new file mode 100644
index 00000000000..733e532f987
--- /dev/null
+++ b/arch/arm/dts/xilinx-versal-virt.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Empty device tree for versal-virt board
+ *
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+
+/ {
+};
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 11598623954..f0ec2639a38 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x100000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt"
CONFIG_CMD_FRU=y
CONFIG_DEFINE_TCM_OCM_MMAP=y
CONFIG_COUNTER_FREQUENCY=100000000
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 11/32] arm: bcm7xxx: Add a devicetree file
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (9 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 10/32] arm: xilinx_versal_virt: Add a " Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 12/32] arm: qemu-ppce500: " Simon Glass
` (20 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud,
Thomas Fitzsimmons
Add an empty devicetree file for these boards. It seems to be possible to
obtain a real one from another bootloader called 'bolt' but I will leave
this to the maintainer.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Mention that this is empty, rather than a dummy file
arch/arm/dts/Makefile | 2 ++
arch/arm/dts/bcm7xxx.dts | 15 +++++++++++++++
configs/bcm7260_defconfig | 1 +
configs/bcm7445_defconfig | 1 +
4 files changed, 19 insertions(+)
create mode 100644 arch/arm/dts/bcm7xxx.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b07a1b3378e..8bb15b96cc7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1092,6 +1092,8 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
+dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
+
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
diff --git a/arch/arm/dts/bcm7xxx.dts b/arch/arm/dts/bcm7xxx.dts
new file mode 100644
index 00000000000..786ce3ff959
--- /dev/null
+++ b/arch/arm/dts/bcm7xxx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Empty devicetre file for bcm7260 board
+ *
+ * This is required to make the board build with CONFIG OF_SEPARATE
+ * In-tree document explains how to obtain a real devicetree using 'bolt' but
+ * I did not attempt this.
+ *
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+
+/ {
+};
diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig
index 257d81052a8..2b527b65770 100644
--- a/configs/bcm7260_defconfig
+++ b/configs/bcm7260_defconfig
@@ -7,6 +7,7 @@ CONFIG_TARGET_BCM7260=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x814800
+CONFIG_DEFAULT_DEVICE_TREE="bcm7xxx"
CONFIG_ENV_OFFSET_REDUND=0x824800
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig
index 9ffa436e454..3ae678ba56e 100644
--- a/configs/bcm7445_defconfig
+++ b/configs/bcm7445_defconfig
@@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x1E0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="bcm7xxx"
CONFIG_ENV_OFFSET_REDUND=0x1F0000
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_FIT=y
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 12/32] arm: qemu-ppce500: Add a devicetree file
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (10 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 11/32] arm: bcm7xxx: " Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 13/32] arm: highbank: Add devicetree files Simon Glass
` (19 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud,
Alexander Graf, Bin Meng
This uses QEMU virt which creates its own devicetree.
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Switch to using an empty file for qemu virt
arch/powerpc/dts/Makefile | 1 +
arch/powerpc/dts/qemu-ppce500.dts | 10 ++++++++++
configs/qemu-ppce500_defconfig | 1 +
3 files changed, 12 insertions(+)
create mode 100644 arch/powerpc/dts/qemu-ppce500.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index ceaa8ce5c82..66d22ae8a45 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -18,6 +18,7 @@ dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
+dtb-$(CONFIG_TARGET_QEMU_PPCE500) += qemu-ppce500.dtb
dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
diff --git a/arch/powerpc/dts/qemu-ppce500.dts b/arch/powerpc/dts/qemu-ppce500.dts
new file mode 100644
index 00000000000..e88e09e1796
--- /dev/null
+++ b/arch/powerpc/dts/qemu-ppce500.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Empty device tree for qemu-ppce400
+ *
+ * Copyright 2021 Google LLC
+ */
+/dts-v1/;
+
+/ {
+};
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index f386f526548..ae4cd8b9618 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -1,6 +1,7 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xf01000
CONFIG_ENV_SIZE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500"
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_QEMU_PPCE500=y
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 13/32] arm: highbank: Add devicetree files
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (11 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 12/32] arm: qemu-ppce500: " Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 14/32] fdt: Make OF_BOARD a bool option Simon Glass
` (18 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Albert Aribaud,
Andre Przywara
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Use an empty tree due to maintainer objections
Changes in v7:
- Bring in files from Linux instead
arch/arm/dts/Makefile | 2 ++
arch/arm/dts/highbank.dts | 9 +++++++++
configs/highbank_defconfig | 1 +
3 files changed, 12 insertions(+)
create mode 100644 arch/arm/dts/highbank.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8bb15b96cc7..453e2fd1a98 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -871,6 +871,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
+
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
fsl-imx8qm-mek.dtb \
diff --git a/arch/arm/dts/highbank.dts b/arch/arm/dts/highbank.dts
new file mode 100644
index 00000000000..1480bad9104
--- /dev/null
+++ b/arch/arm/dts/highbank.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Empty devicetree for highbank/midway
+ */
+
+/dts-v1/;
+
+/ {
+};
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index 85b42c70f55..af40f713184 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="highbank"
CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_DISTRO_DEFAULTS=y
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 14/32] fdt: Make OF_BOARD a bool option
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (12 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 13/32] arm: highbank: Add devicetree files Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 15/32] fdt: Drop CONFIG_BINMAN_STANDALONE_FDT Simon Glass
` (17 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
This should not be a separate option from OF_SEPARATE. It is a run-time
option to override the devicetree, even if present.
Move the option out of the choice.
Disable BINMAN_FDT for a few boards which don't actually use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
configs/qemu-ppce500_defconfig | 1 +
configs/qemu-riscv32_spl_defconfig | 2 ++
configs/qemu-riscv64_spl_defconfig | 1 +
dts/Kconfig | 11 ++++++-----
4 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index ae4cd8b9618..81d12d5f3c1 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -56,4 +56,5 @@ CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
CONFIG_ADDR_MAP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_PANIC_HANG=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index c4422969c61..8889b028c6b 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
+# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
@@ -18,3 +19,4 @@ CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
+# CONFIG_BINMAN_FDT is not set
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index e02ca3a1465..8f875949ec0 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -19,3 +19,4 @@ CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
+# CONFIG_BINMAN_FDT is not set
diff --git a/dts/Kconfig b/dts/Kconfig
index b7c4a2fec03..9994ab13dcb 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -97,11 +97,9 @@ config OF_LIVE
choice
prompt "Provider of DTB for DT control"
depends on OF_CONTROL
- default OF_BOARD if SANDBOX
config OF_SEPARATE
bool "Separate DTB for DT control"
- depends on !SANDBOX
help
If this option is enabled, the device tree will be built and
placed as a separate u-boot.dtb file alongside the U-Boot image.
@@ -114,14 +112,17 @@ config OF_EMBED
and development only and is not recommended for production devices.
Boards in the mainline U-Boot tree should not use it.
+endchoice
+
config OF_BOARD
bool "Provided by the board (e.g a previous loader) at runtime"
+ default y if SANDBOX
help
If this option is enabled, the device tree will be provided by
- the board at runtime if the board supports it, instead of being
- bundled with the image.
+ the board at runtime if the board supports it. The device tree bundled
+ with the image (if any) will be overridden / ignored.
-endchoice
+ A device tree file must be provided in the tree.
config DEFAULT_DEVICE_TREE
string "Default Device Tree for DT control"
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 15/32] fdt: Drop CONFIG_BINMAN_STANDALONE_FDT
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (13 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 14/32] fdt: Make OF_BOARD a bool option Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 16/32] fdt: Make it easier to debug u-boot.dtsi files Simon Glass
` (16 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
This was added as a hack to work around not having an in-tree devicetree.
Now that this is fixed it is not needed.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Add an fdt: tag
Makefile | 3 +--
dts/Kconfig | 18 ------------------
tools/binman/binman.rst | 20 --------------------
3 files changed, 1 insertion(+), 40 deletions(-)
diff --git a/Makefile b/Makefile
index 043af9a5dcd..6671c5d9e2f 100644
--- a/Makefile
+++ b/Makefile
@@ -953,7 +953,6 @@ endif
endif
INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb
-INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb
ifeq ($(CONFIG_SPL_FRAMEWORK),y)
INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
endif
@@ -1427,7 +1426,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
- $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
,$(UBOOT_BIN)) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
diff --git a/dts/Kconfig b/dts/Kconfig
index 9994ab13dcb..6ebbac2a649 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -16,24 +16,6 @@ config BINMAN
bool
select DTOC
-config BINMAN_STANDALONE_FDT
- bool
- depends on BINMAN
- default y if OF_BOARD
- help
- This option tells U-Boot build system that a standalone device tree
- source is explicitly required when using binman to package U-Boot.
-
- This is not necessary in a common scenario where a device tree source
- that contains the binman node is provided in the arch/<arch>/dts
- directory for a specific board. Such device tree sources are built for
- OF_SEPARATE or OF_EMBED. However for a scenario like the board device
- tree blob is not provided in the U-Boot build tree, but fed to U-Boot
- in the runtime, e.g.: in the OF_BOARD case that it is passed by
- a prior stage bootloader. For such scenario, a standalone device tree
- blob containing binman node to describe how to package U-Boot should
- be provided explicitly.
-
menu "Device Tree Control"
depends on SUPPORT_OF_CONTROL
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 10389a52c4b..56f865800e6 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -232,26 +232,6 @@ You can use other, more specific CONFIG options - see 'Automatic .dtsi
inclusion' below.
-Using binman with OF_BOARD
---------------------------------------------
-
-Normally binman is used with a board configured with OF_SEPARATE or OF_EMBED.
-This is a typical scenario where a device tree source that contains the binman
-node is provided in the arch/<arch>/dts directory for a specific board.
-
-However for a board configured with OF_BOARD, no device tree blob is provided
-in the U-Boot build phase hence the binman node information is not available.
-In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT
-is introduced, to tell the build system that a standalone device tree blob
-containing binman node is explicitly required.
-
-Note there is a Kconfig option BINMAN_FDT which enables U-Boot run time to
-access information about binman entries, stored in the device tree in a binman
-node. Generally speaking, this option makes sense for OF_SEPARATE or OF_EMBED.
-For the other OF_CONTROL methods, it's quite possible binman node is not
-available as binman is invoked during the build phase, thus this option is not
-turned on by default for these OF_CONTROL methods.
-
Access to binman entry offsets at run time (symbols)
----------------------------------------------------
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 16/32] fdt: Make it easier to debug u-boot.dtsi files
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (14 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 15/32] fdt: Drop CONFIG_BINMAN_STANDALONE_FDT Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 17/32] fdt: Move MULTI_DTB_FIT handling out of fdtdec_setup() Simon Glass
` (15 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
At present one must hack the Makefile to see what is going on with these
files. Also it doesn't quite work correctly.
Fix this by using an environment variable for debugging. Update the docs
also.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Add a new patch to make it easier to debug u-boot.dtsi files
scripts/Makefile.lib | 4 +++-
tools/binman/binman.rst | 14 ++++++++------
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 39f03398ed8..b4e63bc0ca4 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -175,7 +175,9 @@ u_boot_dtsi_options_raw = $(warning Automatic .dtsi inclusion: options: \
# Uncomment for debugging
# This shows all the files that were considered and the one that we chose.
-# u_boot_dtsi_options_debug = $(u_boot_dtsi_options_raw)
+ifdef DEVICE_TREE_DEBUG
+u_boot_dtsi_options_debug = $(warning $(u_boot_dtsi_options_raw))
+endif
# We use the first match
u_boot_dtsi = $(strip $(u_boot_dtsi_options_debug) \
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 56f865800e6..3e063d1f86c 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -790,12 +790,14 @@ Binman will search for the following files in arch/<arch>/dts::
U-Boot will only use the first one that it finds. If you need to include a
more general file you can do that from the more specific file using #include.
-If you are having trouble figuring out what is going on, you can uncomment
-the 'warning' line in scripts/Makefile.lib to see what it has found::
-
- # Uncomment for debugging
- # This shows all the files that were considered and the one that we chose.
- # u_boot_dtsi_options_debug = $(u_boot_dtsi_options_raw)
+If you are having trouble figuring out what is going on, you can use
+`DEVICE_TREE_DEBUG=1` with your build::
+
+ make DEVICE_TREE_DEBUG=1
+ scripts/Makefile.lib:334: Automatic .dtsi inclusion: options:
+ arch/arm/dts/juno-r2-u-boot.dtsi arch/arm/dts/-u-boot.dtsi
+ arch/arm/dts/armv8-u-boot.dtsi arch/arm/dts/armltd-u-boot.dtsi
+ arch/arm/dts/u-boot.dtsi ... found: "arch/arm/dts/juno-r2-u-boot.dtsi"
Updating an ELF file
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 17/32] fdt: Move MULTI_DTB_FIT handling out of fdtdec_setup()
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (15 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 16/32] fdt: Make it easier to debug u-boot.dtsi files Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 18/32] fdt: Drop #ifdefs with MULTI_DTB_FIT Simon Glass
` (14 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
This logic is a bit convoluted for one function. Move the mulit-FIT part
into its own function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
---
(no changes since v1)
lib/fdtdec.c | 62 ++++++++++++++++++++++++++++++++--------------------
1 file changed, 38 insertions(+), 24 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 7681f272d27..e0ce2532f95 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1594,13 +1594,46 @@ __weak int fdtdec_board_setup(const void *fdt_blob)
return 0;
}
+/**
+ * setup_multi_dtb_fit() - locate the correct dtb from a FIT
+ *
+ * This supports the CONFIG_MULTI_DTB_FIT feature, looking for the dtb in a
+ * supplied FIT
+ *
+ * It accepts the current value of gd->fdt_blob, which points to the FIT, then
+ * updates that gd->fdt_blob, to point to the chosen dtb so that U-Boot uses the
+ * correct one
+ */
+static void setup_multi_dtb_fit(void)
+{
+# if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
+ void *blob;
+
+ /*
+ * Try and uncompress the blob.
+ * Unfortunately there is no way to know how big the input blob really
+ * is. So let us set the maximum input size arbitrarily high. 16MB
+ * ought to be more than enough for packed DTBs.
+ */
+ if (uncompress_blob(gd->fdt_blob, 0x1000000, &blob) == 0)
+ gd->fdt_blob = blob;
+
+ /*
+ * Check if blob is a FIT images containings DTBs.
+ * If so, pick the most relevant
+ */
+ blob = locate_dtb_in_fit(gd->fdt_blob);
+ if (blob) {
+ gd->multi_dtb_fit = gd->fdt_blob;
+ gd->fdt_blob = blob;
+ }
+#endif /* # MULTI_DTB_FIT */
+}
+
int fdtdec_setup(void)
{
int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL)
-# if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
- void *fdt_blob;
-# endif
# ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
# ifdef CONFIG_SPL_BUILD
@@ -1621,27 +1654,8 @@ int fdtdec_setup(void)
(unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
# endif
-# if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
- /*
- * Try and uncompress the blob.
- * Unfortunately there is no way to know how big the input blob really
- * is. So let us set the maximum input size arbitrarily high. 16MB
- * ought to be more than enough for packed DTBs.
- */
- if (uncompress_blob(gd->fdt_blob, 0x1000000, &fdt_blob) == 0)
- gd->fdt_blob = fdt_blob;
-
- /*
- * Check if blob is a FIT images containings DTBs.
- * If so, pick the most relevant
- */
- fdt_blob = locate_dtb_in_fit(gd->fdt_blob);
- if (fdt_blob) {
- gd->multi_dtb_fit = gd->fdt_blob;
- gd->fdt_blob = fdt_blob;
- }
-
-# endif
+ if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
+ setup_multi_dtb_fit();
#endif
ret = fdtdec_prepare_fdt();
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 18/32] fdt: Drop #ifdefs with MULTI_DTB_FIT
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (16 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 17/32] fdt: Move MULTI_DTB_FIT handling out of fdtdec_setup() Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 19/32] fdt: Drop CONFIG_SPL_BUILD check in fdtdec_setup() Simon Glass
` (13 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
Refactor the code to drop the #ifdefs for this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
dts/Kconfig | 1 -
include/asm-generic/global_data.h | 8 ++++++++
lib/fdtdec.c | 31 +++++++++++--------------------
3 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/dts/Kconfig b/dts/Kconfig
index 6ebbac2a649..5dcc79d5192 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -177,7 +177,6 @@ endchoice
config MULTI_DTB_FIT_UNCOMPRESS_SZ
hex "Size of memory reserved to uncompress the DTBs"
- depends on (MULTI_DTB_FIT_GZIP || MULTI_DTB_FIT_LZO)
default 0x8000
help
This is the size of this area where the DTBs are uncompressed.
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 16fd305a65c..99daa20c765 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -512,6 +512,14 @@ static_assert(sizeof(struct global_data) == GD_SIZE);
#define gd_acpi_ctx() NULL
#endif
+#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
+#define gd_multi_dtb_fit() gd->multi_dtb_fit
+#define gd_set_multi_dtb_fit(_dtb) gd->multi_dtb_fit = _dtb
+#else
+#define gd_multi_dtb_fit() NULL
+#define gd_set_multi_dtb_fit(_dtb)
+#endif
+
/**
* enum gd_flags - global data flags
*
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index e0ce2532f95..4967ab87075 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1146,11 +1146,10 @@ int fdtdec_setup_mem_size_base_lowest(void)
return 0;
}
-#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
-# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
- CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
{
+#if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
+ CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
size_t sz_out = CONFIG_VAL(MULTI_DTB_FIT_UNCOMPRESS_SZ);
bool gzip = 0, lzo = 0;
ulong sz_in = sz_src;
@@ -1175,11 +1174,11 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
return -ENOMEM;
}
} else {
-# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA)
+# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA)
dst = (void *)CONFIG_VAL(MULTI_DTB_FIT_USER_DEF_ADDR);
-# else
+# else
return -ENOTSUPP;
-# endif
+# endif
}
if (CONFIG_IS_ENABLED(GZIP) && gzip)
@@ -1197,16 +1196,12 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
return -EBADMSG;
}
*dstp = dst;
- return 0;
-}
-# else
-static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
-{
+#else
+ *dstp = (void *)src;
*dstp = (void *)src;
+#endif
return 0;
}
-# endif
-#endif
#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
/*
@@ -1606,7 +1601,6 @@ __weak int fdtdec_board_setup(const void *fdt_blob)
*/
static void setup_multi_dtb_fit(void)
{
-# if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
void *blob;
/*
@@ -1624,10 +1618,9 @@ static void setup_multi_dtb_fit(void)
*/
blob = locate_dtb_in_fit(gd->fdt_blob);
if (blob) {
- gd->multi_dtb_fit = gd->fdt_blob;
+ gd_set_multi_dtb_fit(gd->fdt_blob);
gd->fdt_blob = blob;
}
-#endif /* # MULTI_DTB_FIT */
}
int fdtdec_setup(void)
@@ -1664,7 +1657,6 @@ int fdtdec_setup(void)
return ret;
}
-#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
int fdtdec_resetup(int *rescan)
{
void *fdt_blob;
@@ -1675,8 +1667,8 @@ int fdtdec_resetup(int *rescan)
* FIT image stillpresent there. Save the time and space
* required to uncompress it again.
*/
- if (gd->multi_dtb_fit) {
- fdt_blob = locate_dtb_in_fit(gd->multi_dtb_fit);
+ if (gd_multi_dtb_fit()) {
+ fdt_blob = locate_dtb_in_fit(gd_multi_dtb_fit());
if (fdt_blob == gd->fdt_blob) {
/*
@@ -1700,7 +1692,6 @@ int fdtdec_resetup(int *rescan)
*rescan = 0;
return 0;
}
-#endif
int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
phys_addr_t *basep, phys_size_t *sizep,
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 19/32] fdt: Drop CONFIG_SPL_BUILD check in fdtdec_setup()
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (17 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 18/32] fdt: Drop #ifdefs with MULTI_DTB_FIT Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 20/32] fdt: Drop #ifdef around board_fdt_blob_setup() Simon Glass
` (12 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
Move this to the header file to clean up the C code.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
include/fdtdec.h | 14 ++++++++++++++
lib/fdtdec.c | 6 +-----
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 6c7ab887b20..68786111a44 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -111,6 +111,20 @@ struct fdt_pci_addr {
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */
+/* Get a pointer to the embedded devicetree, if there is one, else NULL */
+static inline u8 *dtb_dt_embedded(void)
+{
+#ifdef CONFIG_OF_EMBED
+# ifdef CONFIG_SPL_BUILD
+ return __dtb_dt_spl_begin;
+# else
+ return __dtb_dt_begin;
+# endif
+#else
+ return NULL;
+#endif
+}
+
/**
* Compute the size of a resource.
*
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4967ab87075..fbdc92c0813 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1629,11 +1629,7 @@ int fdtdec_setup(void)
#if CONFIG_IS_ENABLED(OF_CONTROL)
# ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
-# ifdef CONFIG_SPL_BUILD
- gd->fdt_blob = __dtb_dt_spl_begin;
-# else
- gd->fdt_blob = __dtb_dt_begin;
-# endif
+ gd->fdt_blob = dtb_dt_embedded();
# elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
/* Allow the board to override the fdt address. */
gd->fdt_blob = board_fdt_blob_setup(&ret);
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 20/32] fdt: Drop #ifdef around board_fdt_blob_setup()
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (18 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 19/32] fdt: Drop CONFIG_SPL_BUILD check in fdtdec_setup() Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 21/32] fdt: Use if() for fdtcontroladdr check Simon Glass
` (11 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
This serves no purpose. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
lib/fdtdec.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index fbdc92c0813..299a2c3a32f 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1203,7 +1203,6 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
return 0;
}
-#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
/*
* For CONFIG_OF_SEPARATE, the board may optionally implement this to
* provide and/or fixup the fdt.
@@ -1226,7 +1225,6 @@ __weak void *board_fdt_blob_setup(int *err)
return fdt_blob;
}
-#endif
int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size)
{
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 21/32] fdt: Use if() for fdtcontroladdr check
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (19 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 20/32] fdt: Drop #ifdef around board_fdt_blob_setup() Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 22/32] fdt: Drop OF_CONTROL check in fdtdec_setup() Simon Glass
` (10 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
Change this to use if() instead of #if
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
lib/fdtdec.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 299a2c3a32f..659aeffd82e 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1634,12 +1634,11 @@ int fdtdec_setup(void)
if (ret)
return ret;
# endif
-# ifndef CONFIG_SPL_BUILD
- /* Allow the early environment to override the fdt address */
- gd->fdt_blob = map_sysmem
- (env_get_ulong("fdtcontroladdr", 16,
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Allow the early environment to override the fdt address */
+ gd->fdt_blob = map_sysmem(env_get_ulong("fdtcontroladdr", 16,
(unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
-# endif
+ }
if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
setup_multi_dtb_fit();
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 22/32] fdt: Drop OF_CONTROL check in fdtdec_setup()
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (20 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 21/32] fdt: Use if() for fdtcontroladdr check Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 23/32] fdt: Drop remaining preprocessor macros " Simon Glass
` (9 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
This function should only be called when OF_CONTROL is enabled. It
fails in fdtdec_prepare_fdt() anyway, since gd->fdt_blob stays as NULL
if OF_CONTROL is not enabled.
Drop this useless check.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
lib/fdtdec.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 659aeffd82e..5b31064cee2 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1624,16 +1624,15 @@ static void setup_multi_dtb_fit(void)
int fdtdec_setup(void)
{
int ret;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-# ifdef CONFIG_OF_EMBED
+#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
gd->fdt_blob = dtb_dt_embedded();
-# elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
+#elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
/* Allow the board to override the fdt address. */
gd->fdt_blob = board_fdt_blob_setup(&ret);
if (ret)
return ret;
-# endif
+#endif
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
/* Allow the early environment to override the fdt address */
gd->fdt_blob = map_sysmem(env_get_ulong("fdtcontroladdr", 16,
@@ -1642,7 +1641,6 @@ int fdtdec_setup(void)
if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
setup_multi_dtb_fit();
-#endif
ret = fdtdec_prepare_fdt();
if (!ret)
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 23/32] fdt: Drop remaining preprocessor macros in fdtdec_setup()
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (21 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 22/32] fdt: Drop OF_CONTROL check in fdtdec_setup() Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 24/32] fdt: Don't call board_fdt_blob_setup() without OF_BOARD Simon Glass
` (8 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
We only have two choices for obtaining the devicetree. Simplify the code
to make that clear.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
lib/fdtdec.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 5b31064cee2..a7f62123a94 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1624,15 +1624,17 @@ static void setup_multi_dtb_fit(void)
int fdtdec_setup(void)
{
int ret;
-#ifdef CONFIG_OF_EMBED
- /* Get a pointer to the FDT */
- gd->fdt_blob = dtb_dt_embedded();
-#elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
- /* Allow the board to override the fdt address. */
- gd->fdt_blob = board_fdt_blob_setup(&ret);
- if (ret)
- return ret;
-#endif
+
+ /* The devicetree is typically appended to U-Boot */
+ if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
+ /* Allow the board to override the fdt address. */
+ gd->fdt_blob = board_fdt_blob_setup(&ret);
+ if (ret)
+ return ret;
+ } else { /* embed dtb in ELF file for testing / development */
+ gd->fdt_blob = dtb_dt_embedded();
+ }
+
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
/* Allow the early environment to override the fdt address */
gd->fdt_blob = map_sysmem(env_get_ulong("fdtcontroladdr", 16,
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 24/32] fdt: Don't call board_fdt_blob_setup() without OF_BOARD
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (22 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 23/32] fdt: Drop remaining preprocessor macros " Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 25/32] dm: core: Allow getting some basic stats Simon Glass
` (7 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
At present this override function is called even when OF_BOARD is not
enabled. This makes it impossible to disable this feature and in fact
makes the OF_BOARD option useless.
Reinstate its intended purpose, so that it is possible to switch between
the appended devicetree and one provided by the board's custom function.
A follower patch adds warnings for this scenario, but for now we don't
have a Kconfig that definitively tells us that OF_BOARD should be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Mention the follower patch
Changes in v7:
- Fix 'Is' typo in commit message
Changes in v5:
- Add new patches to clean up fdtdec_setup() and surrounds
include/fdtdec.h | 7 +++++--
lib/fdtdec.c | 21 ++++++++++++---------
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 68786111a44..68a36f10583 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -1170,10 +1170,13 @@ int fdtdec_resetup(int *rescan);
/**
* Board-specific FDT initialization. Returns the address to a device tree blob.
- * Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined
- * and the board implements it.
+ *
+ * Called when CONFIG_OF_BOARD is defined.
+ *
+ * The existing devicetree is available at gd->fdt_blob
*
* @err internal error code if we fail to setup a DTB
+ * @returns new devicetree blob pointer
*/
void *board_fdt_blob_setup(int *err);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index a7f62123a94..31a509bc221 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1203,15 +1203,15 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
return 0;
}
-/*
- * For CONFIG_OF_SEPARATE, the board may optionally implement this to
- * provide and/or fixup the fdt.
+/**
+ * fdt_find_separate() - Find a devicetree at the end of the image
+ *
+ * @return pointer to FDT blob
*/
-__weak void *board_fdt_blob_setup(int *err)
+static void *fdt_find_separate(void)
{
void *fdt_blob = NULL;
- *err = 0;
#ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
@@ -1626,13 +1626,16 @@ int fdtdec_setup(void)
int ret;
/* The devicetree is typically appended to U-Boot */
- if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
- /* Allow the board to override the fdt address. */
+ if (IS_ENABLED(CONFIG_OF_SEPARATE))
+ gd->fdt_blob = fdt_find_separate();
+ else /* embed dtb in ELF file for testing / development */
+ gd->fdt_blob = dtb_dt_embedded();
+
+ /* Allow the board to override the fdt address. */
+ if (IS_ENABLED(CONFIG_OF_BOARD)) {
gd->fdt_blob = board_fdt_blob_setup(&ret);
if (ret)
return ret;
- } else { /* embed dtb in ELF file for testing / development */
- gd->fdt_blob = dtb_dt_embedded();
}
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 25/32] dm: core: Allow getting some basic stats
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (23 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 24/32] fdt: Don't call board_fdt_blob_setup() without OF_BOARD Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 26/32] fdt: Record where the devicetree came from Simon Glass
` (6 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Marek Vasut,
Pavel Herrmann
Add a function that returns some basic stats about driver model. For now
we only have two.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/core/device.c | 11 ++++++++++
drivers/core/root.c | 7 ++++++
drivers/core/uclass.c | 13 ++++++++++++
include/dm/device.h | 11 +++++++++-
include/dm/root.h | 8 +++++++
include/dm/uclass-internal.h | 7 ++++++
test/dm/core.c | 41 ++++++++++++++++++++++++++++++++++++
7 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 74374ff881c..4873c47d10b 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -739,6 +739,17 @@ int device_get_child_count(const struct udevice *parent)
return count;
}
+int device_get_decendent_count(const struct udevice *parent)
+{
+ const struct udevice *dev;
+ int count = 1;
+
+ list_for_each_entry(dev, &parent->child_head, sibling_node)
+ count += device_get_decendent_count(dev);
+
+ return count;
+}
+
int device_find_child_by_seq(const struct udevice *parent, int seq,
struct udevice **devp)
{
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 26b8195faa3..815173f86eb 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -26,6 +26,7 @@
#include <dm/read.h>
#include <dm/root.h>
#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
#include <dm/util.h>
#include <linux/list.h>
@@ -407,6 +408,12 @@ int dm_init_and_scan(bool pre_reloc_only)
return 0;
}
+void dm_get_stats(int *device_countp, int *uclass_countp)
+{
+ *device_countp = device_get_decendent_count(gd->dm_root);
+ *uclass_countp = uclass_get_count();
+}
+
#ifdef CONFIG_ACPIGEN
static int root_acpi_get_name(const struct udevice *dev, char *out_name)
{
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 2aa21430775..336ea8d243d 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -643,6 +643,19 @@ int uclass_next_device_check(struct udevice **devp)
return device_probe(*devp);
}
+int uclass_get_count(void)
+{
+ const struct uclass *uc;
+ int count = 0;
+
+ if (gd->dm_root) {
+ list_for_each_entry(uc, gd->uclass_root, sibling_node)
+ count++;
+ }
+
+ return count;
+}
+
int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data,
struct udevice **devp)
{
diff --git a/include/dm/device.h b/include/dm/device.h
index daf28a0a457..19d37e0e76c 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -593,7 +593,7 @@ int device_get_child(const struct udevice *parent, int index,
struct udevice **devp);
/**
- * device_get_child_count() - Get the available child count of a device
+ * device_get_child_count() - Get the child count of a device
*
* Returns the number of children to a device.
*
@@ -601,6 +601,15 @@ int device_get_child(const struct udevice *parent, int index,
*/
int device_get_child_count(const struct udevice *parent);
+/**
+ * device_get_decendent_count() - Get the total number of decendents of a device
+ *
+ * Returns the total number of decendents, including all children
+ *
+ * @parent: Parent device to check
+ */
+int device_get_decendent_count(const struct udevice *parent);
+
/**
* device_find_child_by_seq() - Find a child device based on a sequence
*
diff --git a/include/dm/root.h b/include/dm/root.h
index 42510b106ab..780f269db65 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -131,4 +131,12 @@ int dm_remove_devices_flags(uint flags);
static inline int dm_remove_devices_flags(uint flags) { return 0; }
#endif
+/**
+ * dm_get_stats() - Get some stats for driver mode
+ *
+ * @device_countp: Returns total number of devices that are bound
+ * @uclass_countp: Returns total number of uclasses in use
+ */
+void dm_get_stats(int *device_countp, int *uclass_countp);
+
#endif
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
index 49808c5c856..fb0edcc2969 100644
--- a/include/dm/uclass-internal.h
+++ b/include/dm/uclass-internal.h
@@ -306,6 +306,13 @@ int uclass_pre_remove_device(struct udevice *dev);
static inline int uclass_pre_remove_device(struct udevice *dev) { return 0; }
#endif
+/**
+ * uclass_get_count() - Get the number of uclasses
+ *
+ * Returns the number of uclasses instantiated in driver model
+ */
+int uclass_get_count(void);
+
/**
* uclass_find() - Find uclass by its id
*
diff --git a/test/dm/core.c b/test/dm/core.c
index c9a7606666c..c76dfdb1651 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -307,11 +307,15 @@ static int dm_test_lifecycle(struct unit_test_state *uts)
{
int op_count[DM_TEST_OP_COUNT];
struct udevice *dev, *test_dev;
+ int start_dev_count, start_uc_count;
+ int dev_count, uc_count;
int pingret;
int ret;
memcpy(op_count, dm_testdrv_op_count, sizeof(op_count));
+ dm_get_stats(&start_dev_count, &start_uc_count);
+
ut_assertok(device_bind_by_name(uts->root, false, &driver_info_manual,
&dev));
ut_assert(dev);
@@ -319,6 +323,11 @@ static int dm_test_lifecycle(struct unit_test_state *uts)
== op_count[DM_TEST_OP_BIND] + 1);
ut_assert(!dev_get_priv(dev));
+ /* We should have one more device */
+ dm_get_stats(&dev_count, &uc_count);
+ ut_asserteq(start_dev_count + 1, dev_count);
+ ut_asserteq(start_uc_count, uc_count);
+
/* Probe the device - it should fail allocating private data */
uts->force_fail_alloc = 1;
ret = device_probe(dev);
@@ -353,6 +362,11 @@ static int dm_test_lifecycle(struct unit_test_state *uts)
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]);
+ /* We should have one less device */
+ dm_get_stats(&dev_count, &uc_count);
+ ut_asserteq(start_dev_count, dev_count);
+ ut_asserteq(start_uc_count, uc_count);
+
return 0;
}
DM_TEST(dm_test_lifecycle, UT_TESTF_SCAN_PDATA | UT_TESTF_PROBE_TEST);
@@ -526,17 +540,31 @@ DM_TEST(dm_test_leak, 0);
/* Test uclass init/destroy methods */
static int dm_test_uclass(struct unit_test_state *uts)
{
+ int dev_count, uc_count;
struct uclass *uc;
+ /* We should have just the root device and uclass */
+ dm_get_stats(&dev_count, &uc_count);
+ ut_asserteq(1, dev_count);
+ ut_asserteq(1, uc_count);
+
ut_assertok(uclass_get(UCLASS_TEST, &uc));
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
ut_assert(uclass_get_priv(uc));
+ dm_get_stats(&dev_count, &uc_count);
+ ut_asserteq(1, dev_count);
+ ut_asserteq(2, uc_count);
+
ut_assertok(uclass_destroy(uc));
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
+ dm_get_stats(&dev_count, &uc_count);
+ ut_asserteq(1, dev_count);
+ ut_asserteq(1, uc_count);
+
return 0;
}
DM_TEST(dm_test_uclass, 0);
@@ -1217,3 +1245,16 @@ static int dm_test_dma_offset(struct unit_test_state *uts)
}
DM_TEST(dm_test_dma_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
#endif
+
+/* Test dm_get_stats() */
+static int dm_test_get_stats(struct unit_test_state *uts)
+{
+ int dev_count, uc_count;
+
+ dm_get_stats(&dev_count, &uc_count);
+ ut_assert(dev_count > 50);
+ ut_assert(uc_count > 30);
+
+ return 0;
+}
+DM_TEST(dm_test_get_stats, UT_TESTF_SCAN_FDT);
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 26/32] fdt: Record where the devicetree came from
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (24 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 25/32] dm: core: Allow getting some basic stats Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 27/32] fdt: Report the devicetree source Simon Glass
` (5 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
Keep track of where the devicetree came from, so we can report this later.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Drop FDTSRC_PASSAGE for now
include/asm-generic/global_data.h | 4 ++++
include/fdtdec.h | 32 +++++++++++++++++++++++++++++++
lib/fdtdec.c | 20 ++++++++++++++-----
3 files changed, 51 insertions(+), 5 deletions(-)
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 99daa20c765..104282bd479 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -244,6 +244,10 @@ struct global_data {
* @fdt_size: space reserved for relocated device space
*/
unsigned long fdt_size;
+ /**
+ * @fdt_src: Source of FDT
+ */
+ enum fdt_source_t fdt_src;
#if CONFIG_IS_ENABLED(OF_LIVE)
/**
* @of_root: root node of the live tree
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 68a36f10583..09525ce510a 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -55,6 +55,31 @@ struct bd_info;
#define SPL_BUILD 0
#endif
+/**
+ * enum fdt_source_t - indicates where the devicetree came from
+ *
+ * These are listed in approximate order of desirability after FDTSRC_NONE
+ *
+ * @FDTSRC_SEPARATE: Appended to U-Boot. This is the normal approach if U-Boot
+ * is the only firmware being booted
+ * @FDTSRC_FIT: Found in a multi-dtb FIT. This should be used when U-Boot must
+ * select a devicetree from many options
+ * @FDTSRC_BOARD: Located by custom board code. This should only be used when
+ * the prior stage does not support FDTSRC_PASSAGE
+ * @FDTSRC_EMBED: Embedded into U-Boot executable. This should onyl be used when
+ * U-Boot is packaged as an ELF file, e.g. for debugging purposes
+ * @FDTSRC_ENV: Provided by the fdtcontroladdr environment variable. This should
+ * be used for debugging/development only
+ * @FDTSRC_NONE: No devicetree at all
+ */
+enum fdt_source_t {
+ FDTSRC_SEPARATE,
+ FDTSRC_FIT,
+ FDTSRC_BOARD,
+ FDTSRC_EMBED,
+ FDTSRC_ENV,
+};
+
/*
* Information about a resource. start is the first address of the resource
* and end is the last address (inclusive). The length of the resource will
@@ -1215,4 +1240,11 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
phys_addr_t *basep, phys_size_t *sizep,
struct bd_info *bd);
+/**
+ * fdtdec_get_srcname() - Get the name of where the devicetree comes from
+ *
+ * @return source name
+ */
+const char *fdtdec_get_srcname(void);
+
#endif
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 31a509bc221..8cfa958fb96 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1618,6 +1618,7 @@ static void setup_multi_dtb_fit(void)
if (blob) {
gd_set_multi_dtb_fit(gd->fdt_blob);
gd->fdt_blob = blob;
+ gd->fdt_src = FDTSRC_FIT;
}
}
@@ -1626,22 +1627,31 @@ int fdtdec_setup(void)
int ret;
/* The devicetree is typically appended to U-Boot */
- if (IS_ENABLED(CONFIG_OF_SEPARATE))
+ if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
gd->fdt_blob = fdt_find_separate();
- else /* embed dtb in ELF file for testing / development */
+ gd->fdt_src = FDTSRC_SEPARATE;
+ } else { /* embed dtb in ELF file for testing / development */
gd->fdt_blob = dtb_dt_embedded();
+ gd->fdt_src = FDTSRC_EMBED;
+ }
/* Allow the board to override the fdt address. */
if (IS_ENABLED(CONFIG_OF_BOARD)) {
gd->fdt_blob = board_fdt_blob_setup(&ret);
if (ret)
return ret;
+ gd->fdt_src = FDTSRC_BOARD;
}
+ /* Allow the early environment to override the fdt address */
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
- /* Allow the early environment to override the fdt address */
- gd->fdt_blob = map_sysmem(env_get_ulong("fdtcontroladdr", 16,
- (unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
+ ulong addr;
+
+ addr = env_get_hex("fdtcontroladdr", 0);
+ if (addr) {
+ gd->fdt_blob = map_sysmem(addr, 0);
+ gd->fdt_src = FDTSRC_ENV;
+ }
}
if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 27/32] fdt: Report the devicetree source
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (25 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 26/32] fdt: Record where the devicetree came from Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 28/32] fdt: Add a Kconfig for boards with a prior stage Simon Glass
` (4 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
It can be confusing to figure out where the devicetree came from. It seems
important enough to warrant a message during boot. Add information about
the number of devices and uclasses too since it is helpful to have some
idea what is going on with driver model.
Report the devicetree source in bdinfo too.
This looks something like this, with > marking the new line.
U-Boot 2021.10-00190 (Oct 30 2021 - 09:01:29 -0600)
DRAM: 128 MiB
> Core: 42 devices, 11 uclasses, devicetree: passage
Flash: 64 MiB
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Drop FDTSRC_PASSAGE for now
cmd/bdinfo.c | 2 ++
common/board_r.c | 18 ++++++++++++++++++
lib/fdtdec.c | 13 +++++++++++++
3 files changed, 33 insertions(+)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index bf63cc6d649..c56b3f4f6ec 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -128,6 +128,8 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
lmb_dump_all_force(&lmb);
+ if (IS_ENABLED(CONFIG_OF_REAL))
+ printf("devicetree = %s\n", fdtdec_get_srcname());
}
arch_print_bdinfo();
diff --git a/common/board_r.c b/common/board_r.c
index 31a59c585a8..99adff14b39 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -586,6 +586,23 @@ int initr_mem(void)
}
#endif
+static int dm_announce(void)
+{
+ int device_count;
+ int uclass_count;
+
+ if (IS_ENABLED(CONFIG_DM)) {
+ dm_get_stats(&device_count, &uclass_count);
+ printf("Core: %d devices, %d uclasses", device_count,
+ uclass_count);
+ if (CONFIG_IS_ENABLED(OF_REAL))
+ printf(", devicetree: %s", fdtdec_get_srcname());
+ printf("\n");
+ }
+
+ return 0;
+}
+
static int run_main_loop(void)
{
#ifdef CONFIG_SANDBOX
@@ -661,6 +678,7 @@ static init_fnc_t init_sequence_r[] = {
stdio_init_tables,
serial_initialize,
initr_announce,
+ dm_announce,
#if CONFIG_IS_ENABLED(WDT)
initr_watchdog,
#endif
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 8cfa958fb96..118c100b389 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -76,6 +76,19 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
};
+static const char *const fdt_src_name[] = {
+ [FDTSRC_SEPARATE] = "separate",
+ [FDTSRC_FIT] = "fit",
+ [FDTSRC_BOARD] = "board",
+ [FDTSRC_EMBED] = "embed",
+ [FDTSRC_ENV] = "env",
+};
+
+const char *fdtdec_get_srcname(void)
+{
+ return fdt_src_name[gd->fdt_src];
+}
+
const char *fdtdec_get_compatible(enum fdt_compat_id id)
{
/* We allow reading of the 'unknown' ID for testing purposes */
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 28/32] fdt: Add a Kconfig for boards with a prior stage
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (26 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 27/32] fdt: Report the devicetree source Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 29/32] fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD Simon Glass
` (3 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
When U-Boot is started from another firmware program, not just a prior
phase of U-Boot, special behaviour is typically used. In particular, the
device tree may come from that prior stage.
At present this is sort-of indicated by OF_BOARD, although the
correlation is not 1:1, since that option simply means that the board has
a custom mechanism for obtaining the device tree. For example, sandbox
defines OF_BOARD. Also the board_fdt_blob_setup() function can in fact
make use of the devicetree in U-Boot if it wishes, as used by
dragonboard410c until very recently.
Add an explicit Kconfig for this situation. Update the OF_BOARD option to
more-accurately reflect what it is doing, e.g. for sandbox.
Drop the docs in the README as it is out of date.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Drop the devicetree docs in the README
- Move board-config changes to a separate patch
Changes in v7:
- Add new patch to add a Kconfig for boards with a prior stage
README | 29 -----------------------------
dts/Kconfig | 33 ++++++++++++++++++++++++++++-----
lib/fdtdec.c | 1 +
3 files changed, 29 insertions(+), 34 deletions(-)
diff --git a/README b/README
index 056b717557b..3496bef7774 100644
--- a/README
+++ b/README
@@ -646,35 +646,6 @@ The following options need to be configured:
which adds regex support to some commands, as for
example "env grep" and "setexpr".
-- Device tree:
- CONFIG_OF_CONTROL
- If this variable is defined, U-Boot will use a device tree
- to configure its devices, instead of relying on statically
- compiled #defines in the board file. This option is
- experimental and only available on a few boards. The device
- tree is available in the global data as gd->fdt_blob.
-
- U-Boot needs to get its device tree from somewhere. This can
- be done using one of the three options below:
-
- CONFIG_OF_SEPARATE
- If this variable is defined, U-Boot will build a device tree
- binary. It will be called u-boot.dtb. Architecture-specific
- code will locate it at run-time. Generally this works by:
-
- cat u-boot.bin u-boot.dtb >image.bin
-
- and in fact, U-Boot does this for you, creating a file called
- u-boot-dtb.bin which is useful in the common case. You can
- still use the individual files if you need something more
- exotic.
-
- CONFIG_OF_BOARD
- If this variable is defined, U-Boot will use the device tree
- provided by the board at runtime instead of embedding one with
- the image. Only boards defining board_fdt_blob_setup() support
- this option (see include/fdtdec.h file).
-
- Watchdog:
CONFIG_WATCHDOG
If this variable is defined, it enables watchdog
diff --git a/dts/Kconfig b/dts/Kconfig
index 5dcc79d5192..e57ce84b98d 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -98,13 +98,36 @@ endchoice
config OF_BOARD
bool "Provided by the board (e.g a previous loader) at runtime"
- default y if SANDBOX
+ default y if SANDBOX || OF_HAS_PRIOR_STAGE
help
- If this option is enabled, the device tree will be provided by
- the board at runtime if the board supports it. The device tree bundled
- with the image (if any) will be overridden / ignored.
+ If this option is enabled, the device tree is provided at runtime by
+ a custom function called board_fdt_blob_setup(). The board must
+ implement this function if it wishes to provide special behaviour.
- A device tree file must be provided in the tree.
+ With this option, the device tree build by U-Boot may be overridden or
+ ignored. See OF_HAS_PRIOR_STAGE.
+
+ Note: Boards which use this to handle a device tree passed from an
+ earlier stage should enable OF_HAS_PRIOR_STAGE.
+
+config OF_HAS_PRIOR_STAGE
+ bool
+ help
+ Indicates that a prior stage of the firmware (before U-Boot proper)
+ makes use of device tree and this board normally boots with that prior
+ stage, that provides a devicetree to U-Boot.
+
+ This means that the device tree built in U-Boot should not be packaged
+ in the firmware image. Instead, the prior stage's device tree should
+ be so packaged. At runtime, the prior stage reads this, does any
+ necessary fix-ups, then passes it to U-Boot. See OF_BOARD.
+
+ This option does not preclude using the U-Boot device tree, e.g. for
+ development purposes, but it is not recommended, and likely will not
+ even work, for production systems.
+
+ Note: This option must be set in Kconfig and cannot be enabled or
+ disabled in the board's defconfig file.
config DEFAULT_DEVICE_TREE
string "Default Device Tree for DT control"
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 118c100b389..280cda61a72 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1595,6 +1595,7 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
return 0;
}
+/* TODO(sjg@chromium.org): This function should not be weak */
__weak int fdtdec_board_setup(const void *fdt_blob)
{
return 0;
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 29/32] fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (27 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 28/32] fdt: Add a Kconfig for boards with a prior stage Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 30/32] fdt: Makefile: Ensure that OF_BOARD is used when needed Simon Glass
` (2 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
Use this new Kconfig instead of OF_BOARD, so we know for sure which boards
obtain their devicetree from a prior stage. Leave sandbox alone since it
does not. Also don't touch xilinx_versal_virt since it does not have a
specific TARGET Kconfig.
This option implies OF_BOARD for now, but with future work standard
passage may be used instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Move board-config changes to a separate patch
arch/arm/Kconfig | 12 +++++++++---
arch/arm/mach-bcm283x/Kconfig | 1 +
arch/powerpc/cpu/mpc85xx/Kconfig | 1 +
board/emulation/qemu-riscv/Kconfig | 1 +
configs/ae350_rv32_defconfig | 1 -
configs/ae350_rv32_spl_defconfig | 1 -
configs/ae350_rv32_spl_xip_defconfig | 1 -
configs/ae350_rv64_defconfig | 1 -
configs/ae350_rv64_spl_defconfig | 1 -
configs/ae350_rv64_spl_xip_defconfig | 1 -
configs/bcm7260_defconfig | 1 -
configs/bcm7445_defconfig | 1 -
configs/highbank_defconfig | 1 -
configs/octeontx2_95xx_defconfig | 1 -
configs/octeontx2_96xx_defconfig | 1 -
configs/octeontx_81xx_defconfig | 1 -
configs/octeontx_83xx_defconfig | 1 -
configs/qemu-ppce500_defconfig | 1 -
configs/qemu-riscv32_defconfig | 1 -
configs/qemu-riscv32_smode_defconfig | 1 -
configs/qemu-riscv32_spl_defconfig | 1 -
configs/qemu-riscv64_defconfig | 1 -
configs/qemu-riscv64_smode_defconfig | 1 -
configs/qemu-riscv64_spl_defconfig | 1 -
configs/qemu_arm64_defconfig | 1 -
configs/qemu_arm_defconfig | 1 -
configs/rpi_4_32b_defconfig | 1 -
configs/rpi_4_defconfig | 1 -
configs/rpi_arm64_defconfig | 1 -
configs/vexpress_aemv8a_juno_defconfig | 1 -
configs/xenguest_arm64_defconfig | 1 -
31 files changed, 12 insertions(+), 30 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index eed27af74e8..85c964b7a18 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -635,6 +635,7 @@ config ARCH_BCMSTB
select GPIO_EXTRA_HEADER
select OF_CONTROL
imply CMD_DM
+ imply OF_HAS_PRIOR_STAGE
help
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
@@ -707,12 +708,12 @@ config ARCH_HIGHBANK
select DM
select DM_SERIAL
select OF_CONTROL
- select OF_BOARD
select CLK
select CLK_CCF
select AHCI
select DM_ETH
select PHYS_64BIT
+ imply OF_HAS_PRIOR_STAGE
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
@@ -935,13 +936,13 @@ config ARCH_APPLE
select IOMMU
select LINUX_KERNEL_IMAGE_HEADER
select OF_CONTROL
- select OF_BOARD
select PINCTRL
select POSITION_INDEPENDENT
select USB
imply CMD_DM
imply CMD_GPT
imply DISTRO_DEFAULTS
+ imply OF_HAS_PRIOR_STAGE
config ARCH_OWL
bool "Actions Semi OWL SoCs"
@@ -966,6 +967,7 @@ config ARCH_QEMU
imply DM_RNG
imply DM_RTC
imply RTC_PL031
+ imply OF_HAS_PRIOR_STAGE
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
@@ -1243,7 +1245,6 @@ config TARGET_VEXPRESS64_JUNO
select PL01X_SERIAL
select DM
select OF_CONTROL
- select OF_BOARD
select CLK
select DM_SERIAL
select ARM_PSCI_FW
@@ -1251,6 +1252,7 @@ config TARGET_VEXPRESS64_JUNO
select DM_ETH
select BLK
select USB
+ imply OF_HAS_PRIOR_STAGE
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
@@ -1907,6 +1909,7 @@ config ARCH_OCTEONTX
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
+ imply OF_HAS_PRIOR_STAGE
config ARCH_OCTEONTX2
bool "Support OcteonTX2 SoCs"
@@ -1918,6 +1921,7 @@ config ARCH_OCTEONTX2
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
+ imply OF_HAS_PRIOR_STAGE
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
@@ -1954,6 +1958,8 @@ config TARGET_XENGUEST_ARM64
select LINUX_KERNEL_IMAGE_HEADER
select XEN_SERIAL
select SSCANF
+ imply OF_HAS_PRIOR_STAGE
+
endchoice
config SUPPORT_PASSING_ATAGS
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index b3287ce8bce..2eb3802d9ae 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -188,6 +188,7 @@ config TARGET_RPI_4
This option creates a build targeting the ARMv8/AArch64 ISA.
select BCM2711_64B
+ imply OF_HAS_PRIOR_STAGE
config TARGET_RPI_ARM64
bool "Raspberry Pi one binary 64-bit build"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 836aeddbe29..d71ca86ab06 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -109,6 +109,7 @@ config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
select ARCH_QEMU_E500
select PHYS_64BIT
+ imply OF_HAS_PRIOR_STAGE
config TARGET_T1024RDB
bool "Support T1024RDB"
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 1bbf1bc84af..a380db61a0f 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -65,5 +65,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply VIRTIO_BLK
imply MTD_NOR_FLASH
imply CFI_FLASH
+ imply OF_HAS_PRIOR_STAGE
endif
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index fe18a1cee4e..f65f58cbefd 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -17,7 +17,6 @@ CONFIG_CMD_SF_TEST=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 9287544781f..9324ed1f6cd 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -21,7 +21,6 @@ CONFIG_CMD_SF_TEST=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_SEND_HOSTNAME=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index 18d114e24c4..bd06c8ed897 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -23,7 +23,6 @@ CONFIG_CMD_SF_TEST=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_SEND_HOSTNAME=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 01016c238c8..479c1ded58c 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -18,7 +18,6 @@ CONFIG_CMD_SF_TEST=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 42b93f52751..1ec993ccc5f 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -22,7 +22,6 @@ CONFIG_CMD_SF_TEST=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_SEND_HOSTNAME=y
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index 9071b7c6530..b6a97f27d1d 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -24,7 +24,6 @@ CONFIG_CMD_SF_TEST=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTP_SEND_HOSTNAME=y
diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig
index 2b527b65770..d430dea9e3b 100644
--- a/configs/bcm7260_defconfig
+++ b/configs/bcm7260_defconfig
@@ -27,7 +27,6 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DOS_PARTITION=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig
index 3ae678ba56e..de64161f8c1 100644
--- a/configs/bcm7445_defconfig
+++ b/configs/bcm7445_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DOS_PARTITION=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index af40f713184..3e8bfcf73a6 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -22,7 +22,6 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_BOARD=y
CONFIG_ENV_IS_IN_NVRAM=y
CONFIG_ENV_ADDR=0xFFF88000
CONFIG_SCSI_AHCI=y
diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index e3df390c94b..0dbb954273f 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -64,7 +64,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index 0478b3068a6..65fb8474e10 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -65,7 +65,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index d871be8f812..ea62be30631 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -66,7 +66,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index 94b072bf6fa..47ddc50e7b7 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -63,7 +63,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 81d12d5f3c1..894203d75ba 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -27,7 +27,6 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index 4c0f51bd2aa..b892fd6d6ec 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -12,6 +12,5 @@ CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index 19406080100..b4856fd3852 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -13,7 +13,6 @@ CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index 8889b028c6b..efe8d390fd9 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -15,7 +15,6 @@ CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index cba975d703d..036484c7f79 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -13,6 +13,5 @@ CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 6b7771488fe..e519bb6bb78 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -16,7 +16,6 @@ CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 8f875949ec0..8b512372d6c 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -15,7 +15,6 @@ CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_SBI=y
# CONFIG_CMD_MII is not set
-CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 3c75fb71828..46053576c01 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -28,7 +28,6 @@ CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x4000000
CONFIG_SCSI_AHCI=y
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index a644a5f3e79..f2994920a3f 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -30,7 +30,6 @@ CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x4000000
CONFIG_SCSI_AHCI=y
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 0d534b8a28d..8f87a4336d2 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -21,7 +21,6 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 0b3cadaced2..461a7655ab9 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -21,7 +21,6 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index 0b5f766cfe7..351d247daeb 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -20,7 +20,6 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_TFTP_TSIZE=y
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index 0ccd990b80b..ffadfc03eeb 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -33,7 +33,6 @@ CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_UBI=y
-CONFIG_OF_BOARD=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xBFC0000
CONFIG_SATA_SIL=y
diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig
index edce34346d3..223bb782b7d 100644
--- a/configs/xenguest_arm64_defconfig
+++ b/configs/xenguest_arm64_defconfig
@@ -33,7 +33,6 @@ CONFIG_CMD_PVBLOCK=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
-CONFIG_OF_BOARD=y
CONFIG_DM=y
# CONFIG_MMC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 30/32] fdt: Makefile: Ensure that OF_BOARD is used when needed
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (28 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 29/32] fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-24 14:34 ` Tom Rini
2021-12-17 3:59 ` [PATCH v8 31/32] fdt: Avoid emitting an device tree when not needed Simon Glass
2021-12-17 3:59 ` [PATCH v8 32/32] fdt: Show a runtime warning based on devicetree source Simon Glass
31 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren,
Masahiro Yamada
Boards which define OF_HAS_PRIOR_STAGE must define OF_BOARD at present,
since a custom function is the only way to obtain the devicetree at
runtime.
Add a build error when this requirement is not met, to avoid accepting
any patches which break this requirement.
Add a whitelist for boards which use it, currently none. This whitelist
can be updated for local development, if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Add new patch to ensure that OF_BOARD is used when needed
Makefile | 7 +++++++
scripts/check-of.sh | 42 ++++++++++++++++++++++++++++++++++++++++
scripts/of_whitelist.txt | 1 +
3 files changed, 50 insertions(+)
create mode 100755 scripts/check-of.sh
create mode 100644 scripts/of_whitelist.txt
diff --git a/Makefile b/Makefile
index 6671c5d9e2f..98ef2642f68 100644
--- a/Makefile
+++ b/Makefile
@@ -1061,6 +1061,10 @@ quiet_cmd_cfgcheck = CFGCHK $2
cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
$(srctree)/scripts/config_whitelist.txt $(srctree)
+quiet_cmd_ofcheck = OFCHK $2
+cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \
+ $(srctree)/scripts/of_whitelist.txt
+
# Concat the value of all the CONFIGs (result is 'y' or 'yy', etc. )
got = $(foreach cfg,$(1),$($(cfg)))
@@ -1139,6 +1143,9 @@ endif
@# know about unless they are in Kconfig. All the existing CONFIG
@# options are whitelisted, so new ones should not be added.
$(call cmd,cfgcheck,u-boot.cfg)
+ @# Check that this build does not override OF_HAS_PRIOR_STAGE by
+ @# disabling OF_BOARD.
+ $(call cmd,ofcheck,$(KCONFIG_CONFIG))
PHONY += dtbs
dtbs: dts/dt.dtb
diff --git a/scripts/check-of.sh b/scripts/check-of.sh
new file mode 100755
index 00000000000..3ce7105cad4
--- /dev/null
+++ b/scripts/check-of.sh
@@ -0,0 +1,42 @@
+#!/bin/sh
+# Copyright 2021 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Check that the .config file provided does not try to disable OF_BOARD for
+# boards that use CONFIG_OF_HAS_PRIOR_STAGE
+#
+# Usage
+# check-of.sh <path to .config> <path to whitelist file>
+#
+# For example:
+# scripts/check-of.sh b/chromebook_link/u-boot.cfg kconfig_whitelist.txt
+#
+# Exit code is 0 if OK, 3 if the .config is wrong, as above
+
+set -e
+set -u
+
+PROG_NAME="${0##*/}"
+
+usage() {
+ echo "$PROG_NAME <path to .config> <path to whitelist file>"
+ exit 1
+}
+
+[ $# -ge 2 ] || usage
+
+path="$1"
+whitelist="$2"
+
+sys_config="$(sed -n 's/CONFIG_SYS_CONFIG_NAME="\(.*\)"$/\1/p' "${path}")"
+
+if grep -q OF_HAS_PRIOR_STAGE=y "${path}"; then
+ if ! grep -lq CONFIG_OF_BOARD=y "${path}"; then
+ echo >&2 "This board uses a prior stage to provide the device tree."
+ echo >&2 "Please enable CONFIG_OF_BOARD to ensure that it works correctly."
+ if grep -q "${sys_config}" "${whitelist}"; then
+ exit 0
+ fi
+ exit 3
+ fi
+fi
diff --git a/scripts/of_whitelist.txt b/scripts/of_whitelist.txt
new file mode 100644
index 00000000000..e82cf557bb2
--- /dev/null
+++ b/scripts/of_whitelist.txt
@@ -0,0 +1 @@
+# List of boards which are permitted to use OF_HAS_PRIOR_STAGE without OF_BOARD
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v8 30/32] fdt: Makefile: Ensure that OF_BOARD is used when needed
2021-12-17 3:59 ` [PATCH v8 30/32] fdt: Makefile: Ensure that OF_BOARD is used when needed Simon Glass
@ 2021-12-24 14:34 ` Tom Rini
0 siblings, 0 replies; 36+ messages in thread
From: Tom Rini @ 2021-12-24 14:34 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Ilias Apalodimas, Sean Anderson,
Heinrich Schuchardt, Mark Kettenis, François Ozog,
Jerry Van Baren, Masahiro Yamada
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On Thu, Dec 16, 2021 at 08:59:37PM -0700, Simon Glass wrote:
> Boards which define OF_HAS_PRIOR_STAGE must define OF_BOARD at present,
> since a custom function is the only way to obtain the devicetree at
> runtime.
>
> Add a build error when this requirement is not met, to avoid accepting
> any patches which break this requirement.
>
> Add an allowlist for boards which use it, currently none. This allowlist
> can be updated for local development, if needed.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> [trini: change of_whitelist to of_allowlist]
> Signed-off-by: Tom Rini <trini@konsulko.com>
(My changes for the email record, the rest of the series was taken
as-is)
Applied to u-boot/next, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v8 31/32] fdt: Avoid emitting an device tree when not needed
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (29 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 30/32] fdt: Makefile: Ensure that OF_BOARD is used when needed Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
2021-12-17 3:59 ` [PATCH v8 32/32] fdt: Show a runtime warning based on devicetree source Simon Glass
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
U-Boot always needs some sort of a device tree in the build. Some boards
never actually use this, at least in production systems, since a prior
firmware stage sets one up and passes it to U-Boot. At present the only
mechanism to do that is with custom function (OF_BOARD), but future work
will include a standard way of doing this ('standard passage').
It can be confusing to see a device tree emitted from the U-Boot build in
this situation. Add an option to drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Fix devicetree logic so that just u-boot.dtb is omitted
Makefile | 6 ++++--
dts/Kconfig | 10 ++++++++++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 98ef2642f68..dc391af29ca 100644
--- a/Makefile
+++ b/Makefile
@@ -952,7 +952,9 @@ INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
endif
endif
INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
-INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb
+
+# Allow omitting the .dtb output if it is not normally used
+INPUTS-$(CONFIG_OF_SEPARATE) += $(if $(CONFIG_OF_OMIT_DTB),dts/dt.dtb,u-boot.dtb)
ifeq ($(CONFIG_SPL_FRAMEWORK),y)
INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
endif
@@ -1199,7 +1201,7 @@ u-boot.bin: u-boot-fit-dtb.bin FORCE
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
$(call if_changed,cat)
-else ifeq ($(CONFIG_OF_SEPARATE),y)
+else ifeq ($(CONFIG_OF_SEPARATE).$(CONFIG_OF_OMIT_DTB),y.)
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
$(call if_changed,cat)
diff --git a/dts/Kconfig b/dts/Kconfig
index e57ce84b98d..fb7df533f92 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -129,6 +129,16 @@ config OF_HAS_PRIOR_STAGE
Note: This option must be set in Kconfig and cannot be enabled or
disabled in the board's defconfig file.
+config OF_OMIT_DTB
+ bool "Omit the device tree output when building"
+ default y if OF_HAS_PRIOR_STAGE && !BINMAN
+ help
+ As a special case, avoid writing a device tree file u-boot.dtb when
+ building. Also don't include that file in u-boot.bin
+
+ This is used for boards which normally provide a devicetree via a
+ runtime mechanism (such as OF_BOARD), to avoid confusion.
+
config DEFAULT_DEVICE_TREE
string "Default Device Tree for DT control"
depends on OF_CONTROL
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v8 32/32] fdt: Show a runtime warning based on devicetree source
2021-12-17 3:59 [PATCH v8 00/32] fdt: Make OF_BOARD a boolean option Simon Glass
` (30 preceding siblings ...)
2021-12-17 3:59 ` [PATCH v8 31/32] fdt: Avoid emitting an device tree when not needed Simon Glass
@ 2021-12-17 3:59 ` Simon Glass
31 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2021-12-17 3:59 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Ilias Apalodimas, Sean Anderson, Heinrich Schuchardt, Tom Rini,
Mark Kettenis, François Ozog, Simon Glass, Jerry Van Baren
When running, if the devicetree failed to come from the expected source,
show a warning, e.g:
U-Boot ...
DRAM: 128 MiB
Core: 42 devices, 11 uclasses, devicetree: separate
Warning: Unexpected devicetree source (not from a prior stage)
Warning: U-Boot may not function properly
Flash: 64 MiB
...
These warnings should only appear if the board config has been changed, or
the prior stage is broken.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v8:
- Drop documentation patches
- Drop the build-time warning, since people may ignore it
common/board_r.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/common/board_r.c b/common/board_r.c
index 99adff14b39..6d520662dbb 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -598,6 +598,12 @@ static int dm_announce(void)
if (CONFIG_IS_ENABLED(OF_REAL))
printf(", devicetree: %s", fdtdec_get_srcname());
printf("\n");
+ if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE) &&
+ (gd->fdt_src == FDTSRC_SEPARATE ||
+ gd->fdt_src == FDTSRC_EMBED)) {
+ printf("Warning: Unexpected devicetree source (not from a prior stage)");
+ printf("Warning: U-Boot may not function properly\n");
+ }
}
return 0;
--
2.34.1.173.g76aa8bc2d0-goog
^ permalink raw reply related [flat|nested] 36+ messages in thread