From: Gaurav Jain <gaurav.jain@nxp.com>
To: u-boot@lists.denx.de
Cc: Stefano Babic <sbabic@denx.de>,
Fabio Estevam <festevam@gmail.com>, Peng Fan <peng.fan@nxp.com>,
Simon Glass <sjg@chromium.org>, Michael Walle <michael@walle.cc>,
Priyanka Jain <priyanka.jain@nxp.com>, Ye Li <ye.li@nxp.com>,
Horia Geanta <horia.geanta@nxp.com>, Ji Luo <ji.luo@nxp.com>,
Franck Lenormand <franck.lenormand@nxp.com>,
Silvano Di Ninno <silvano.dininno@nxp.com>,
Sahil malhotra <sahil.malhotra@nxp.com>,
Pankaj Gupta <pankaj.gupta@nxp.com>,
Varun Sethi <V.Sethi@nxp.com>,
"NXP i . MX U-Boot Team" <uboot-imx@nxp.com>,
Shengzhou Liu <Shengzhou.Liu@nxp.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
Rajesh Bhagat <rajesh.bhagat@nxp.com>,
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,
Wasim Khan <wasim.khan@nxp.com>,
Alison Wang <alison.wang@nxp.com>,
Pramod Kumar <pramod.kumar_1@nxp.com>,
Tang Yuantian <andy.tang@nxp.com>,
Adrian Alonso <adrian.alonso@nxp.com>,
Vladimir Oltean <olteanv@gmail.com>,
Gaurav Jain <gaurav.jain@nxp.com>
Subject: [PATCH v10 10/14] Layerscape: Add crypto node in device tree
Date: Wed, 12 Jan 2022 19:01:23 +0530 [thread overview]
Message-ID: <20220112133127.16880-11-gaurav.jain@nxp.com> (raw)
In-Reply-To: <20220112133127.16880-1-gaurav.jain@nxp.com>
LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/arm/dts/fsl-ls1012a.dtsi | 46 ++++++++++++++++++++++++++++++++++-
arch/arm/dts/fsl-ls1043a.dtsi | 45 +++++++++++++++++++++++++++++++++-
arch/arm/dts/fsl-ls1046a.dtsi | 44 +++++++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls1088a.dtsi | 39 +++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls2080a.dtsi | 39 +++++++++++++++++++++++++++++
arch/arm/dts/fsl-lx2160a.dtsi | 41 ++++++++++++++++++++++++++++++-
arch/arm/dts/ls1021a.dtsi | 40 ++++++++++++++++++++++++++++++
7 files changed, 291 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 0ea899c7d7..1cdcc99c1e 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor
*/
@@ -71,6 +71,50 @@
bus-width = <4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 52dc5a9638..72877d2ff5 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
@@ -125,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a60cbf11fc..c655e002aa 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
+ * Copyright 2021 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@@ -124,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index f73fdfda8b..9b7c54b260 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -174,6 +174,45 @@
dr_mode = "host";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 72ba52594a..a1837454f4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -239,6 +239,45 @@
status = "disabled";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <0 139 0x4>; /* Level high type */
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 140 0x4>; /* Level high type */
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 141 0x4>; /* Level high type */
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 142 0x4>; /* Level high type */
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 143 0x4>; /* Level high type */
+ };
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc", "simple-mfd";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 52e4d7205a..57c7d3ef71 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
*/
@@ -27,6 +27,45 @@
clock-output-names = "sysclk";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 86192cbb7f..be330c130f 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -3,6 +3,7 @@
* Freescale ls1021a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include "skeleton.dtsi"
@@ -144,6 +145,45 @@
big-endian;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1700000 0x100000>;
+ ranges = <0x0 0x1700000 0x100000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;
--
2.17.1
next prev parent reply other threads:[~2022-01-12 13:33 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-12 13:31 [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
2022-01-12 20:03 ` Simon Glass
2022-01-12 13:31 ` [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
2022-01-31 21:45 ` ZHIZHIKIN Andrey
2022-01-31 22:02 ` Michael Walle
2022-02-03 5:27 ` [EXT] " Gaurav Jain
2022-02-11 9:48 ` Gaurav Jain
2022-02-11 16:26 ` ZHIZHIKIN Andrey
2022-01-12 13:31 ` [PATCH v10 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 04/14] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 05/14] i.MX6: Enable Job ring driver model Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 06/14] i.MX7: " Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 07/14] i.MX7ULP: " Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 08/14] i.MX8: Add crypto node in device tree Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 09/14] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
2022-01-12 13:31 ` Gaurav Jain [this message]
2022-01-12 13:31 ` [PATCH v10 11/14] Layerscape: " Gaurav Jain
2022-01-12 15:50 ` Michael Walle
2022-01-12 13:31 ` [PATCH v10 12/14] PPC: Add crypto node in device tree Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 13/14] PPC: Enable Job ring driver model Gaurav Jain
2022-01-12 13:31 ` [PATCH v10 14/14] update CAAM MAINTAINER Gaurav Jain
2022-01-31 6:01 ` [PATCH v10 00/14] Add CAAM driver model support Gaurav Jain
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