[PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL

From: Gaurav Jain <gaurav.jain@nxp.com>
To: u-boot@lists.denx.de
Cc: Stefano Babic <sbabic@denx.de>,
	Fabio Estevam <festevam@gmail.com>, Peng Fan <peng.fan@nxp.com>,
	Simon Glass <sjg@chromium.org>, Michael Walle <michael@walle.cc>,
	Priyanka Jain <priyanka.jain@nxp.com>, Ye Li <ye.li@nxp.com>,
	Horia Geanta <horia.geanta@nxp.com>, Ji Luo <ji.luo@nxp.com>,
	Franck Lenormand <franck.lenormand@nxp.com>,
	Silvano Di Ninno <silvano.dininno@nxp.com>,
	Sahil malhotra <sahil.malhotra@nxp.com>,
	Pankaj Gupta <pankaj.gupta@nxp.com>,
	Varun Sethi <V.Sethi@nxp.com>,
	"NXP i . MX U-Boot Team" <uboot-imx@nxp.com>,
	Shengzhou Liu <Shengzhou.Liu@nxp.com>,
	Mingkai Hu <mingkai.hu@nxp.com>,
	Rajesh Bhagat <rajesh.bhagat@nxp.com>,
	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,
	Wasim Khan <wasim.khan@nxp.com>,
	Alison Wang <alison.wang@nxp.com>,
	Pramod Kumar <pramod.kumar_1@nxp.com>,
	Tang Yuantian <andy.tang@nxp.com>,
	Adrian Alonso <adrian.alonso@nxp.com>,
	Vladimir Oltean <olteanv@gmail.com>,
	Gaurav Jain <gaurav.jain@nxp.com>
Subject: [PATCH v10 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL
Date: Wed, 12 Jan 2022 19:01:15 +0530	[thread overview]
Message-ID: <20220112133127.16880-3-gaurav.jain@nxp.com> (raw)
In-Reply-To: <20220112133127.16880-1-gaurav.jain@nxp.com>

disabled use of JR0 in SPL and uboot, as JR0 is reserved
for secure boot.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/imx8mm-evk-u-boot.dtsi      | 19 ++++++++++++++++++-
 arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++-
 arch/arm/dts/imx8mp-evk-u-boot.dtsi      | 19 ++++++++++++++++++-
 arch/arm/dts/imx8mq-evk-u-boot.dtsi      |  4 ++++
 4 files changed, 58 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 6b459831e7..e5682ca165 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include "imx8mm-u-boot.dtsi"
@@ -68,6 +68,23 @@
 	u-boot,dm-spl;
 };
 
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+	status = "disabled";
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
 &usdhc1 {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 1d3844437d..d8df863083 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 / {
@@ -104,6 +104,23 @@
 	u-boot,dm-spl;
 };
 
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+	status = "disabled";
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
 &usdhc1 {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index ab849ebaac..f3f83ba303 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include "imx8mp-u-boot.dtsi"
@@ -67,6 +67,23 @@
 	u-boot,dm-spl;
 };
 
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+	status = "disabled";
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
 &i2c1 {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 6f9c81462e..8f1f942215 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -10,3 +10,7 @@
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };
+
+&sec_jr0 {
+	status = "disabled";
+};
-- 
2.17.1

