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* [PATCH] video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()
@ 2022-02-01 13:02 Patrick Delaunay
  2022-02-23  7:41 ` Patrice CHOTARD
  0 siblings, 1 reply; 3+ messages in thread
From: Patrick Delaunay @ 2022-02-01 13:02 UTC (permalink / raw)
  To: u-boot
  Cc: Yannick Fertré,
	Gabriel Fernandez, Patrick Delaunay, Anatolij Gustschin,
	Patrice Chotard, U-Boot STM32, Yannick Fertré

From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

The clk_set_rate() function returns rate as an 'ulong' not
an 'int' and rate > 0 by default.

This patch avoids to display the associated warning when
the set rate function returns the new frequency.

Fixes: aeaf330649e8 ("video: stm32: stm32_ltdc: add bridge to display controller")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 drivers/video/stm32/stm32_ltdc.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 87e5fd54d9..e741e74739 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -338,6 +338,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
 	struct display_timing timings;
 	struct clk pclk;
 	struct reset_ctl rst;
+	ulong rate;
 	int ret;
 
 	priv->regs = (void *)dev_read_addr(dev);
@@ -375,13 +376,13 @@ static int stm32_ltdc_probe(struct udevice *dev)
 		}
 	}
 
-	ret = clk_set_rate(&pclk, timings.pixelclock.typ);
-	if (ret)
-		dev_warn(dev, "fail to set pixel clock %d hz\n",
-			 timings.pixelclock.typ);
+	rate = clk_set_rate(&pclk, timings.pixelclock.typ);
+	if (IS_ERR_VALUE(rate))
+		dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
+			 timings.pixelclock.typ, rate);
 
 	dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
-		timings.pixelclock.typ, clk_get_rate(&pclk));
+		timings.pixelclock.typ, rate);
 
 	ret = reset_get_by_index(dev, 0, &rst);
 	if (ret) {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()
  2022-02-01 13:02 [PATCH] video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate() Patrick Delaunay
@ 2022-02-23  7:41 ` Patrice CHOTARD
  2022-03-15  7:56   ` [Uboot-stm32] " Patrice CHOTARD
  0 siblings, 1 reply; 3+ messages in thread
From: Patrice CHOTARD @ 2022-02-23  7:41 UTC (permalink / raw)
  To: Patrick Delaunay, u-boot
  Cc: Yannick Fertré,
	Gabriel Fernandez, Anatolij Gustschin, U-Boot STM32,
	Yannick Fertré

Hi Patrick

On 2/1/22 14:02, Patrick Delaunay wrote:
> From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
> 
> The clk_set_rate() function returns rate as an 'ulong' not
> an 'int' and rate > 0 by default.
> 
> This patch avoids to display the associated warning when
> the set rate function returns the new frequency.
> 
> Fixes: aeaf330649e8 ("video: stm32: stm32_ltdc: add bridge to display controller")
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
> ---
> 
>  drivers/video/stm32/stm32_ltdc.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
> index 87e5fd54d9..e741e74739 100644
> --- a/drivers/video/stm32/stm32_ltdc.c
> +++ b/drivers/video/stm32/stm32_ltdc.c
> @@ -338,6 +338,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
>  	struct display_timing timings;
>  	struct clk pclk;
>  	struct reset_ctl rst;
> +	ulong rate;
>  	int ret;
>  
>  	priv->regs = (void *)dev_read_addr(dev);
> @@ -375,13 +376,13 @@ static int stm32_ltdc_probe(struct udevice *dev)
>  		}
>  	}
>  
> -	ret = clk_set_rate(&pclk, timings.pixelclock.typ);
> -	if (ret)
> -		dev_warn(dev, "fail to set pixel clock %d hz\n",
> -			 timings.pixelclock.typ);
> +	rate = clk_set_rate(&pclk, timings.pixelclock.typ);
> +	if (IS_ERR_VALUE(rate))
> +		dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
> +			 timings.pixelclock.typ, rate);
>  
>  	dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
> -		timings.pixelclock.typ, clk_get_rate(&pclk));
> +		timings.pixelclock.typ, rate);
>  
>  	ret = reset_get_by_index(dev, 0, &rst);
>  	if (ret) {

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [Uboot-stm32] [PATCH] video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()
  2022-02-23  7:41 ` Patrice CHOTARD
@ 2022-03-15  7:56   ` Patrice CHOTARD
  0 siblings, 0 replies; 3+ messages in thread
From: Patrice CHOTARD @ 2022-03-15  7:56 UTC (permalink / raw)
  To: Patrick Delaunay, u-boot
  Cc: U-Boot STM32, Yannick Fertré, Yannick Fertré,
	Anatolij Gustschin, Gabriel Fernandez

Hi Patrick

On 2/23/22 08:41, Patrice CHOTARD wrote:
> Hi Patrick
> 
> On 2/1/22 14:02, Patrick Delaunay wrote:
>> From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
>>
>> The clk_set_rate() function returns rate as an 'ulong' not
>> an 'int' and rate > 0 by default.
>>
>> This patch avoids to display the associated warning when
>> the set rate function returns the new frequency.
>>
>> Fixes: aeaf330649e8 ("video: stm32: stm32_ltdc: add bridge to display controller")
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
>> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
>> ---
>>
>>  drivers/video/stm32/stm32_ltdc.c | 11 ++++++-----
>>  1 file changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
>> index 87e5fd54d9..e741e74739 100644
>> --- a/drivers/video/stm32/stm32_ltdc.c
>> +++ b/drivers/video/stm32/stm32_ltdc.c
>> @@ -338,6 +338,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
>>  	struct display_timing timings;
>>  	struct clk pclk;
>>  	struct reset_ctl rst;
>> +	ulong rate;
>>  	int ret;
>>  
>>  	priv->regs = (void *)dev_read_addr(dev);
>> @@ -375,13 +376,13 @@ static int stm32_ltdc_probe(struct udevice *dev)
>>  		}
>>  	}
>>  
>> -	ret = clk_set_rate(&pclk, timings.pixelclock.typ);
>> -	if (ret)
>> -		dev_warn(dev, "fail to set pixel clock %d hz\n",
>> -			 timings.pixelclock.typ);
>> +	rate = clk_set_rate(&pclk, timings.pixelclock.typ);
>> +	if (IS_ERR_VALUE(rate))
>> +		dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
>> +			 timings.pixelclock.typ, rate);
>>  
>>  	dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
>> -		timings.pixelclock.typ, clk_get_rate(&pclk));
>> +		timings.pixelclock.typ, rate);
>>  
>>  	ret = reset_get_by_index(dev, 0, &rst);
>>  	if (ret) {
> 
> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
> 
> Thanks
> Patrice
> _______________________________________________
> Uboot-stm32 mailing list
> Uboot-stm32@st-md-mailman.stormreply.com
> https://st-md-mailman.stormreply.com/mailman/listinfo/uboot-stm32

Applied to u-boot-stm32

Thanks
Patrice

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-03-15  7:56 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2022-02-01 13:02 [PATCH] video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate() Patrick Delaunay
2022-02-23  7:41 ` Patrice CHOTARD
2022-03-15  7:56   ` [Uboot-stm32] " Patrice CHOTARD

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