* [PATCH] ARM: armv7: add non-SPL enable for Cortex SMPEN
@ 2022-04-21 17:52 Ralph Siemsen
2022-04-21 18:01 ` Tom Rini
0 siblings, 1 reply; 4+ messages in thread
From: Ralph Siemsen @ 2022-04-21 17:52 UTC (permalink / raw)
To: u-boot; +Cc: Ralph Siemsen, Andre Przywara, Tom Rini
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
arch/arm/cpu/armv7/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 2eeef3cba9..9f859b7c95 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -76,6 +76,11 @@ config ARMV7_LPAE
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
+config ARMV7_SET_CORTEX_SMPEN
+ bool
+ help
+ Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+
config SPL_ARMV7_SET_CORTEX_SMPEN
bool
help
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: armv7: add non-SPL enable for Cortex SMPEN
2022-04-21 17:52 [PATCH] ARM: armv7: add non-SPL enable for Cortex SMPEN Ralph Siemsen
@ 2022-04-21 18:01 ` Tom Rini
2022-04-21 18:23 ` Ralph Siemsen
0 siblings, 1 reply; 4+ messages in thread
From: Tom Rini @ 2022-04-21 18:01 UTC (permalink / raw)
To: Ralph Siemsen; +Cc: u-boot, Andre Przywara
[-- Attachment #1: Type: text/plain, Size: 1119 bytes --]
On Thu, Apr 21, 2022 at 01:52:02PM -0400, Ralph Siemsen wrote:
> Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
> added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
> platforms not using SPL boot, add the corresponding non-SPL config,
> so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
>
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
>
> arch/arm/cpu/armv7/Kconfig | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
> index 2eeef3cba9..9f859b7c95 100644
> --- a/arch/arm/cpu/armv7/Kconfig
> +++ b/arch/arm/cpu/armv7/Kconfig
> @@ -76,6 +76,11 @@ config ARMV7_LPAE
> Say Y here to use the long descriptor page table format. This is
> required if U-Boot runs in HYP mode.
>
> +config ARMV7_SET_CORTEX_SMPEN
> + bool
> + help
> + Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
> +
> config SPL_ARMV7_SET_CORTEX_SMPEN
> bool
> help
OK, but this doesn't do anything. Where are you select'ing the new
symbol from?
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: armv7: add non-SPL enable for Cortex SMPEN
2022-04-21 18:01 ` Tom Rini
@ 2022-04-21 18:23 ` Ralph Siemsen
2022-04-21 18:24 ` Tom Rini
0 siblings, 1 reply; 4+ messages in thread
From: Ralph Siemsen @ 2022-04-21 18:23 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot, Andre Przywara
On Thu, Apr 21, 2022 at 2:01 PM Tom Rini <trini@konsulko.com> wrote:
> OK, but this doesn't do anything. Where are you select'ing the new
> symbol from?
It is in code for a new platform which I am going to slowly beat into
shape and try to get upstreamed.
If you prefer to see everything at once, I can do that, but I figured
I'd post the small stuff as I find it, to try and get it out of the
way.
Ralph
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: armv7: add non-SPL enable for Cortex SMPEN
2022-04-21 18:23 ` Ralph Siemsen
@ 2022-04-21 18:24 ` Tom Rini
0 siblings, 0 replies; 4+ messages in thread
From: Tom Rini @ 2022-04-21 18:24 UTC (permalink / raw)
To: Ralph Siemsen; +Cc: u-boot, Andre Przywara
[-- Attachment #1: Type: text/plain, Size: 704 bytes --]
On Thu, Apr 21, 2022 at 02:23:04PM -0400, Ralph Siemsen wrote:
> On Thu, Apr 21, 2022 at 2:01 PM Tom Rini <trini@konsulko.com> wrote:
>
> > OK, but this doesn't do anything. Where are you select'ing the new
> > symbol from?
>
> It is in code for a new platform which I am going to slowly beat into
> shape and try to get upstreamed.
>
> If you prefer to see everything at once, I can do that, but I figured
> I'd post the small stuff as I find it, to try and get it out of the
> way.
OK, I'll keep it in mind for then. But in general, yes, it's OK to
wait and post it as a series, if it's not some sort of general
regression fix or similar stand-alone functionality.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-04-21 18:24 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-21 17:52 [PATCH] ARM: armv7: add non-SPL enable for Cortex SMPEN Ralph Siemsen
2022-04-21 18:01 ` Tom Rini
2022-04-21 18:23 ` Ralph Siemsen
2022-04-21 18:24 ` Tom Rini
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).