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* [PATCH v8 0/4] Add octal DTR support for Macronix flash
@ 2022-07-04  6:12 JaimeLiao
  2022-07-04  6:12 ` [PATCH v8 1/4] mtd: spi-nor: add support for Macronix Octal flash JaimeLiao
                   ` (3 more replies)
  0 siblings, 4 replies; 12+ messages in thread
From: JaimeLiao @ 2022-07-04  6:12 UTC (permalink / raw)
  To: u-boot, jagan, vigneshr, miquel.raynal; +Cc: zhengxunli, jaimeliao, JaimeLiao

This series add support for Macronix octal DTR flash, add flag for
Softreset with "INVERT" command extension type on boot and follow
linux kernel to enable 4byte opcode when possible.

v8:
  Correct spi nor flash information in IDs table.

v7:
  Correct title and description of patchworks.
  Correct description for spi_nor_macronix_octal_dtr_enable.
  Add SFDP informations for flashes in commit log.

v6:
  Parcing SCCR 22nd dword for checking Octal DTR mode support

v5:
  Replace SPI_FLASH_MACRONIX_OCTAL with SPI_FLASH_MACRONIX.
  Remove patch of set_4byte opcode.

v4:
  Add flag SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT to seperate command extension
  types.
  Replace ifdef with CONFIG_IS_ENABLED and modify uncorrect descriptions.

v3:
  Add flag  SPI_NOR_CMD_EXT_INVERT to seperate command extension types.
  replace CONFIG_SPI_FLASH_MACRONIX with SPI_FLASH_MACRONIX_OCTAL for
  spi_nor_macronix_octal_dtr_enable function.
v2:
  add ret checking for write enable in spi_nor_macronix_octal_dtr_enable
  function.

JaimeLiao (4):
  mtd: spi-nor: add support for Macronix Octal flash
  mtd: spi-nor-core: Adding different type of command extension in Soft
    Reset
  mtd: spi-nor: Parse SFDP SCCR Map
  mtd: spi-nor-core: Add support for Macronix Octal flash

 drivers/mtd/spi/Kconfig        |   7 ++
 drivers/mtd/spi/spi-nor-core.c | 141 ++++++++++++++++++++++++++++++++-
 drivers/mtd/spi/spi-nor-ids.c  |  19 ++++-
 include/linux/mtd/spi-nor.h    |  11 +++
 4 files changed, 176 insertions(+), 2 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH v8 1/4] mtd: spi-nor: add support for Macronix Octal flash
  2022-07-04  6:12 [PATCH v8 0/4] Add octal DTR support for Macronix flash JaimeLiao
@ 2022-07-04  6:12 ` JaimeLiao
  2022-07-04  6:12 ` [PATCH v8 2/4] mtd: spi-nor-core: Adding different type of command extension in Soft Reset JaimeLiao
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 12+ messages in thread
From: JaimeLiao @ 2022-07-04  6:12 UTC (permalink / raw)
  To: u-boot, jagan, vigneshr, miquel.raynal; +Cc: zhengxunli, jaimeliao, JaimeLiao

Follow patch <f6adec1af4b2f5d3012480c6cdce7743b74a6156> (Allow using Micron mt35xu512aba
in Octal DTR mode).
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency for adding Macronix flash in Octal DTR mode.
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/spi-nor-core.c | 82 ++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h    | 10 +++++
 2 files changed, 92 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 3b7c817c02..5d319e4c0f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3526,6 +3526,84 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
 };
 #endif /* CONFIG_SPI_FLASH_MT35XU */
 
+#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
+/**
+ * spi_nor_macronix_octal_dtr_enable() - Enable octal DTR on Macronix flashes.
+ * @nor:	pointer to a 'struct spi_nor'
+ *
+ * Set Macronix max dummy cycles 20 to allow the flash to run at fastest frequency.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	int ret;
+	u8 buf;
+
+	ret = write_enable(nor);
+	if (ret)
+		return ret;
+
+	buf = SPINOR_REG_MXIC_DC_20;
+	op = (struct spi_mem_op)
+		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
+			   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_DATA_OUT(1, &buf, 1));
+
+	ret = spi_mem_exec_op(nor->spi, &op);
+	if (ret)
+		return ret;
+
+	ret = spi_nor_wait_till_ready(nor);
+	if (ret)
+		return ret;
+
+	nor->read_dummy = MXIC_MAX_DC;
+	ret = write_enable(nor);
+	if (ret)
+		return ret;
+
+	buf = SPINOR_REG_MXIC_OPI_DTR_EN;
+	op = (struct spi_mem_op)
+		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
+			   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_DATA_OUT(1, &buf, 1));
+
+	ret = spi_mem_exec_op(nor->spi, &op);
+	if (ret) {
+		dev_err(nor->dev, "Failed to enable octal DTR mode\n");
+		return ret;
+	}
+	nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+
+	return 0;
+}
+
+static void macronix_octal_default_init(struct spi_nor *nor)
+{
+	nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
+}
+
+static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
+					 struct spi_nor_flash_parameter *params)
+{
+	/*
+	 * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
+	 * SPI_NOR_OCTAL_DTR_READ flag exists.
+	 */
+	if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
+		params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+}
+
+static struct spi_nor_fixups macronix_octal_fixups = {
+	.default_init = macronix_octal_default_init,
+	.post_sfdp = macronix_octal_post_sfdp_fixup,
+};
+#endif /* CONFIG_SPI_FLASH_MACRONIX */
+
 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
  * @nor:                 pointer to a 'struct spi_nor'
  *
@@ -3696,6 +3774,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
 	if (!strcmp(nor->info->name, "mt35xu512aba"))
 		nor->fixups = &mt35xu512aba_fixups;
 #endif
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
+	nor->fixups = &macronix_octal_fixups;
+#endif /* SPI_FLASH_MACRONIX */
 }
 
 int spi_nor_scan(struct spi_nor *nor)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4ceeae623d..c76235d701 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -119,6 +119,16 @@
 /* Used for Macronix and Winbond flashes. */
 #define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
 #define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */
+#define SPINOR_OP_EN4B			0xb7		/* Enter 4-byte mode */
+#define SPINOR_OP_EX4B			0xe9		/* Exit 4-byte mode */
+#define SPINOR_OP_RD_CR2		0x71		/* Read configuration register 2 */
+#define SPINOR_OP_WR_CR2		0x72		/* Write configuration register 2 */
+#define SPINOR_OP_MXIC_DTR_RD		0xee		/* Fast Read opcode in DTR mode */
+#define SPINOR_REG_MXIC_CR2_MODE	0x00000000	/* For setting octal DTR mode */
+#define SPINOR_REG_MXIC_OPI_DTR_EN	0x2		/* Enable Octal DTR */
+#define SPINOR_REG_MXIC_CR2_DC		0x00000300	/* For setting dummy cycles */
+#define SPINOR_REG_MXIC_DC_20		0x0		/* Setting dummy cycles to 20 */
+#define MXIC_MAX_DC			20		/* Maximum value of dummy cycles */
 
 /* Used for Spansion flashes only. */
 #define SPINOR_OP_BRWR		0x17	/* Bank register write */
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH v8 2/4] mtd: spi-nor-core: Adding different type of command extension in Soft Reset
  2022-07-04  6:12 [PATCH v8 0/4] Add octal DTR support for Macronix flash JaimeLiao
  2022-07-04  6:12 ` [PATCH v8 1/4] mtd: spi-nor: add support for Macronix Octal flash JaimeLiao
@ 2022-07-04  6:12 ` JaimeLiao
  2022-07-07  4:49   ` Jagan Teki
  2022-07-04  6:12 ` [PATCH v8 3/4] mtd: spi-nor: Parse SFDP SCCR Map JaimeLiao
  2022-07-04  6:12 ` [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash JaimeLiao
  3 siblings, 1 reply; 12+ messages in thread
From: JaimeLiao @ 2022-07-04  6:12 UTC (permalink / raw)
  To: u-boot, jagan, vigneshr, miquel.raynal; +Cc: zhengxunli, jaimeliao, JaimeLiao

Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
in the begging of probe.

Command extension type is not standardized across flash vendors in DTR mode.

For suiting different vendor flash devices, adding a flag to seperate types for
soft reset on boot.

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/Kconfig        | 7 +++++++
 drivers/mtd/spi/spi-nor-core.c | 7 ++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index f350c7e5dc..5bb1baa019 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS
 	 can support a type of operation in a much more refined way compared
 	 to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
 
+config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
+	bool "Command extension type is INVERT for Software Reset on boot"
+	default n
+	help
+	 Because of SFDP information can not be get before boot.
+	 So define command extension type is INVERT when Software Reset on boot only.
+
 config SPI_FLASH_SOFT_RESET
 	bool "Software Reset support for SPI NOR flashes"
 	help
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 5d319e4c0f..50460feaf8 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3697,7 +3697,12 @@ static int spi_nor_soft_reset(struct spi_nor *nor)
 	enum spi_nor_cmd_ext ext;
 
 	ext = nor->cmd_ext_type;
-	nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+	if (nor->cmd_ext_type == SPI_NOR_EXT_NONE) {
+		nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+#if CONFIG_IS_ENABLED(SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT)
+		nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
+#endif /* SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT */
+	}
 
 	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
 			SPI_MEM_OP_NO_DUMMY,
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH v8 3/4] mtd: spi-nor: Parse SFDP SCCR Map
  2022-07-04  6:12 [PATCH v8 0/4] Add octal DTR support for Macronix flash JaimeLiao
  2022-07-04  6:12 ` [PATCH v8 1/4] mtd: spi-nor: add support for Macronix Octal flash JaimeLiao
  2022-07-04  6:12 ` [PATCH v8 2/4] mtd: spi-nor-core: Adding different type of command extension in Soft Reset JaimeLiao
@ 2022-07-04  6:12 ` JaimeLiao
  2022-07-04  6:12 ` [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash JaimeLiao
  3 siblings, 0 replies; 12+ messages in thread
From: JaimeLiao @ 2022-07-04  6:12 UTC (permalink / raw)
  To: u-boot, jagan, vigneshr, miquel.raynal; +Cc: zhengxunli, jaimeliao, JaimeLiao

Parse SCCR 22nd dword and check DTR Octal Mode Enable
Volatile bit for Octal DTR enable

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/spi-nor-core.c | 52 ++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h    |  1 +
 2 files changed, 53 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 50460feaf8..1ff34cc317 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -65,6 +65,10 @@ struct sfdp_parameter_header {
 #define SFDP_SECTOR_MAP_ID	0xff81	/* Sector Map Table */
 #define SFDP_SST_ID		0x01bf	/* Manufacturer specific Table */
 #define SFDP_PROFILE1_ID	0xff05	/* xSPI Profile 1.0 Table */
+#define SFDP_SCCR_MAP_ID	0xff87	/*
+					 * Status, Control and Configuration
+					 * Register Map.
+					 */
 
 #define SFDP_SIGNATURE		0x50444653U
 #define SFDP_JESD216_MAJOR	1
@@ -174,6 +178,9 @@ struct sfdp_header {
 #define PROFILE1_DWORD5_DUMMY_100MHZ		GENMASK(11, 7)
 #define PROFILE1_DUMMY_DEFAULT			20
 
+/* Status, Control and Configuration Register Map(SCCR) */
+#define SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE      BIT(31)
+
 struct sfdp_bfpt {
 	u32	dwords[BFPT_DWORD_MAX];
 };
@@ -2456,6 +2463,44 @@ out:
 	return ret;
 }
 
+/**
+ * spi_nor_parse_sccr() - Parse the Status, Control and Configuration Register
+ *			  Map.
+ * @nor:		  pointer to a 'struct spi_nor'
+ * @sccr_header:	  pointer to the 'struct sfdp_parameter_header' describing
+ * 			  the SCCR Map table length and version.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_parse_sccr(struct spi_nor *nor,
+			      const struct sfdp_parameter_header *sccr_header)
+{
+	u32 *table, addr;
+	size_t len;
+	int ret, i;
+
+	len = sccr_header->length * sizeof(*table);
+	table = kmalloc(len, GFP_KERNEL);
+	if (!table)
+		return -ENOMEM;
+
+	addr = SFDP_PARAM_HEADER_PTP(sccr_header);
+	ret = spi_nor_read_sfdp(nor, addr, len, table);
+	if (ret)
+		goto out;
+
+	/* Fix endianness of the table DWORDs. */
+	for (i = 0; i < sccr_header->length; i++)
+		table[i] = le32_to_cpu(table[i]);
+
+	if (FIELD_GET(SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE, table[22]))
+		nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
+
+out:
+	kfree(table);
+	return ret;
+}
+
 /**
  * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
  * @nor:		pointer to a 'struct spi_nor'
@@ -2562,6 +2607,10 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
 			err = spi_nor_parse_profile1(nor, param_header, params);
 			break;
 
+		case SFDP_SCCR_MAP_ID:
+			err = spi_nor_parse_sccr(nor, param_header);
+			break;
+
 		default:
 			break;
 		}
@@ -3620,6 +3669,9 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor)
 	      nor->write_proto == SNOR_PROTO_8_8_8_DTR))
 		return 0;
 
+	if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
+		return 0;
+
 	ret = nor->octal_dtr_enable(nor);
 	if (ret)
 		return ret;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index c76235d701..ba98ad467f 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -290,6 +290,7 @@ enum spi_nor_option_flags {
 	SNOR_F_USE_CLSR		= BIT(5),
 	SNOR_F_BROKEN_RESET	= BIT(6),
 	SNOR_F_SOFT_RESET	= BIT(7),
+	SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
 };
 
 struct spi_nor;
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash
  2022-07-04  6:12 [PATCH v8 0/4] Add octal DTR support for Macronix flash JaimeLiao
                   ` (2 preceding siblings ...)
  2022-07-04  6:12 ` [PATCH v8 3/4] mtd: spi-nor: Parse SFDP SCCR Map JaimeLiao
@ 2022-07-04  6:12 ` JaimeLiao
  2022-07-15  9:04   ` Jagan Teki
  3 siblings, 1 reply; 12+ messages in thread
From: JaimeLiao @ 2022-07-04  6:12 UTC (permalink / raw)
  To: u-boot, jagan, vigneshr, miquel.raynal; +Cc: zhengxunli, jaimeliao, JaimeLiao

Adding Macronix Octal flash for Octal DTR support.

The octaflash series can be divided into the following types:

MX25 series : Serial NOR Flash.
MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW series : Support simultaneous Read-while-Write operation in multiple
               bank architecture. Read-while-write feature which means read
               data one bank while another bank is programing or erasing.

MX25LM : 3.0V Octal I/O
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf

MX25UM : 1.8V Octal I/O
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf

MX66LM : 3.0V Octal I/O with stacked die
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf

MX66UM : 1.8V Octal I/O with stacked die
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf

MX25LW : 3.0V Octal I/O with Read-while-Write
MX25UW : 1.8V Octal I/O with Read-while-Write
MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
MX66UW : 1.8V Octal I/O with Read-while-Write and stack die

About LW/UW series, please contact us freely if you have any
questions. For adding Octal NOR Flash IDs, we have validated
each Flash on plateform zynq-picozed.

As below are the SFDP table dump.

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2943c
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx66uw2g345gx0
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw2g345gx0
zynq> hexdump mx66uw2g345gx0
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 7fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 7987 0001 1284 e200 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 237c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 001f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2853b
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx66lm1g45g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66lm1g45g
zynq> hexdump mx66lm1g45g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 6987 0001 1282 e200 02cc 3867
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 6666
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
0000130 3514 001c 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2853a
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25lm51245g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lm51245g
zynq> hexdump mx25lm51245g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 7989 0001 128d e200 02cc 4467
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 6666
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
0000130 3514 001c 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2863a
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25lw51245g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lw51245g
zynq> hexdump mx25lw51245g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 0000 0000 0000 0000
0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 798b 0001 128f e200 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 6666
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
0000130 3514 001c 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28539
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25lm25645g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lm25645g
zynq> hexdump mx25lm25645g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 6987 0001 1282 d200 02cc 3867
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 6666
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
0000130 3514 001c 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2843c
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx66uw2g345g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw2g345g
zynq> hexdump mx66uw2g345g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 7fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 7987 0001 1284 e200 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 237c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 001f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2803b
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx66um1g45g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66um1g45g
zynq> hexdump mx66um1g45g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 7989 0001 128d e200 02cc 4467
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 3514 809c 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2813b
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx66uw1g45g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw1g45g
zynq> hexdump mx66uw1g45g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 798b 0001 128f e200 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2813a
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25uw51245g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw51245g
zynq> hexdump mx25uw51245g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 798b 0001 128f e200 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 7777
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c2843a
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25uw51345g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw51345g
zynq> hexdump mx25uw51345g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 798b 0001 128f e200 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 237c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28039
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25um25645g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25um25645g
zynq> random: fast init done
zynq> hexdump mx25um25645g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 7987 0001 1284 d200 02cc 3867
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 3514 809c 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28139
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25uw25645g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw25645g
zynq> hexdump mx25uw25645g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 7989 0001 128d d200 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28339
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25um25345g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25um25345g
zynq> hexdump mx25um25345g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 6987 0001 1282 d200 02cc 3867
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 237c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0904 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28439
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25uw25345g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw25345g
zynq> hexdump mx25uw25345g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 7987 0001 1284 d200 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 237c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28138
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25uw12845g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw12845g
zynq> hexdump mx25uw12845g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 0000 0000 0000 0000
0000040 20e5 ff8a ffff 07ff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 798b 0001 128f c900 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28438
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25uw12345g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw12345g
zynq> hexdump mx25uw12345g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 07ff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 798b 0001 128f c900 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 237c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28137
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25uw6445g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw6445g
zynq> hexdump mx25uw6445g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 03ff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 7989 0001 128d c400 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 a37c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
c28437
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
macronix
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
mx25uw6345g
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw6345g
zynq> hexdump mx25uw6345g
0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
0000030 0000 0000 0000 0000 ffff ffff ffff ffff
0000040 20e5 ff8a ffff 03ff ff00 ff00 ff00 ff00
0000050 ffee ffff ffff ff00 ffff ff00 200c d810
0000060 ff00 ff00 798b 0001 128f c400 04cc 4667
0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
0000080 0000 0000 0000 237c 0048 0000 0000 8888
0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
00000b0 7172 b803 7172 b803 0000 0000 a390 8218
00000c0 c000 9669 0000 0000 0000 0000 7172 9800
00000d0 7172 b800 7172 9900 0000 0000 7172 9800
00000e0 7172 f800 7172 9900 7172 f900 0000 0000
00000f0 0000 0000 1501 d001 7172 d806 0000 5086
0000100 0000 0106 0000 0000 0002 0301 0200 0000
0000110 0000 0106 0000 0000 0000 0672 0200 0000
0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
0000130 4514 8098 0643 000f dc21 ffff ffff ffff
0000140 ffff ffff ffff ffff ffff ffff ffff ffff

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/spi-nor-ids.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 7050ddc397..7f1eae4a6d 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -180,7 +180,24 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
 	{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
-	{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66lm1g45g",    0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lm51245g",   0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lw51245g",   0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lm25645g",   0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66um1g45g",    0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw1g45g",    0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw51245g",   0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw51345g",   0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25um25645g",   0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw25645g",   0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25um25345g",   0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw25345g",   0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw12845g",   0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw12345g",   0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw6445g",    0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw6345g",    0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
 #endif
 
 #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* Re: [PATCH v8 2/4] mtd: spi-nor-core: Adding different type of command extension in Soft Reset
  2022-07-04  6:12 ` [PATCH v8 2/4] mtd: spi-nor-core: Adding different type of command extension in Soft Reset JaimeLiao
@ 2022-07-07  4:49   ` Jagan Teki
  2022-07-07  6:26     ` liao jaime
  0 siblings, 1 reply; 12+ messages in thread
From: Jagan Teki @ 2022-07-07  4:49 UTC (permalink / raw)
  To: JaimeLiao; +Cc: u-boot, vigneshr, miquel.raynal, zhengxunli, jaimeliao

On Mon, Jul 4, 2022 at 11:42 AM JaimeLiao <jaimeliao.tw@gmail.com> wrote:
>
> Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
> in the begging of probe.
>
> Command extension type is not standardized across flash vendors in DTR mode.
>
> For suiting different vendor flash devices, adding a flag to seperate types for
> soft reset on boot.
>
> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> ---
>  drivers/mtd/spi/Kconfig        | 7 +++++++
>  drivers/mtd/spi/spi-nor-core.c | 7 ++++++-
>  2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
> index f350c7e5dc..5bb1baa019 100644
> --- a/drivers/mtd/spi/Kconfig
> +++ b/drivers/mtd/spi/Kconfig
> @@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS
>          can support a type of operation in a much more refined way compared
>          to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
>
> +config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
> +       bool "Command extension type is INVERT for Software Reset on boot"
> +       default n
> +       help
> +        Because of SFDP information can not be get before boot.
> +        So define command extension type is INVERT when Software Reset on boot only.
> +
>  config SPI_FLASH_SOFT_RESET
>         bool "Software Reset support for SPI NOR flashes"
>         help
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 5d319e4c0f..50460feaf8 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3697,7 +3697,12 @@ static int spi_nor_soft_reset(struct spi_nor *nor)
>         enum spi_nor_cmd_ext ext;
>
>         ext = nor->cmd_ext_type;
> -       nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> +       if (nor->cmd_ext_type == SPI_NOR_EXT_NONE) {
> +               nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> +#if CONFIG_IS_ENABLED(SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT)
> +               nor->cmd_ext_type = SPI_NOR_EXT_INVERT;

Better check those parts whose extension is not standard instead of CONFIG.

Jagan.

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v8 2/4] mtd: spi-nor-core: Adding different type of command extension in Soft Reset
  2022-07-07  4:49   ` Jagan Teki
@ 2022-07-07  6:26     ` liao jaime
  0 siblings, 0 replies; 12+ messages in thread
From: liao jaime @ 2022-07-07  6:26 UTC (permalink / raw)
  To: Jagan Teki; +Cc: u-boot, vigneshr, Miquel Raynal, zhengxunli, jaimeliao

Hi Jagan

>
> On Mon, Jul 4, 2022 at 11:42 AM JaimeLiao <jaimeliao.tw@gmail.com> wrote:
> >
> > Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
> > in the begging of probe.
> >
> > Command extension type is not standardized across flash vendors in DTR mode.
> >
> > For suiting different vendor flash devices, adding a flag to seperate types for
> > soft reset on boot.
> >
> > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > ---
> >  drivers/mtd/spi/Kconfig        | 7 +++++++
> >  drivers/mtd/spi/spi-nor-core.c | 7 ++++++-
> >  2 files changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
> > index f350c7e5dc..5bb1baa019 100644
> > --- a/drivers/mtd/spi/Kconfig
> > +++ b/drivers/mtd/spi/Kconfig
> > @@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS
> >          can support a type of operation in a much more refined way compared
> >          to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
> >
> > +config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
> > +       bool "Command extension type is INVERT for Software Reset on boot"
> > +       default n
> > +       help
> > +        Because of SFDP information can not be get before boot.
> > +        So define command extension type is INVERT when Software Reset on boot only.
> > +
> >  config SPI_FLASH_SOFT_RESET
> >         bool "Software Reset support for SPI NOR flashes"
> >         help
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index 5d319e4c0f..50460feaf8 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -3697,7 +3697,12 @@ static int spi_nor_soft_reset(struct spi_nor *nor)
> >         enum spi_nor_cmd_ext ext;
> >
> >         ext = nor->cmd_ext_type;
> > -       nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> > +       if (nor->cmd_ext_type == SPI_NOR_EXT_NONE) {
> > +               nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> > +#if CONFIG_IS_ENABLED(SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT)
> > +               nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
>
> Better check those parts whose extension is not standard instead of CONFIG.
spi_nor_soft_reset will be execute before read ID and read SFDP so
that I think we are hard
to get information from flash device.
>
> Jagan.

Thanks
Jaime

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash
  2022-07-04  6:12 ` [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash JaimeLiao
@ 2022-07-15  9:04   ` Jagan Teki
  2022-07-15  9:16     ` liao jaime
  0 siblings, 1 reply; 12+ messages in thread
From: Jagan Teki @ 2022-07-15  9:04 UTC (permalink / raw)
  To: JaimeLiao; +Cc: u-boot, vigneshr, miquel.raynal, zhengxunli, jaimeliao

On Mon, Jul 4, 2022 at 11:43 AM JaimeLiao <jaimeliao.tw@gmail.com> wrote:
>
> Adding Macronix Octal flash for Octal DTR support.
>
> The octaflash series can be divided into the following types:
>
> MX25 series : Serial NOR Flash.
> MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> LW/UW series : Support simultaneous Read-while-Write operation in multiple
>                bank architecture. Read-while-write feature which means read
>                data one bank while another bank is programing or erasing.
>

Can you resend this patch on top of u-boot-spi/master

Jagan.

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash
  2022-07-15  9:04   ` Jagan Teki
@ 2022-07-15  9:16     ` liao jaime
  2022-07-15  9:18       ` Jagan Teki
  0 siblings, 1 reply; 12+ messages in thread
From: liao jaime @ 2022-07-15  9:16 UTC (permalink / raw)
  To: Jagan Teki; +Cc: u-boot, vigneshr, Miquel Raynal, zhengxunli, jaimeliao

Hi Jagan
>
> On Mon, Jul 4, 2022 at 11:43 AM JaimeLiao <jaimeliao.tw@gmail.com> wrote:
> >
> > Adding Macronix Octal flash for Octal DTR support.
> >
> > The octaflash series can be divided into the following types:
> >
> > MX25 series : Serial NOR Flash.
> > MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> > LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> > LW/UW series : Support simultaneous Read-while-Write operation in multiple
> >                bank architecture. Read-while-write feature which means read
> >                data one bank while another bank is programing or erasing.
> >
>
> Can you resend this patch on top of u-boot-spi/master
This patchset is created in the newest version of U-boot(2022.07-rc5).
>
> Jagan.

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash
  2022-07-15  9:16     ` liao jaime
@ 2022-07-15  9:18       ` Jagan Teki
  2022-07-15  9:21         ` liao jaime
  0 siblings, 1 reply; 12+ messages in thread
From: Jagan Teki @ 2022-07-15  9:18 UTC (permalink / raw)
  To: liao jaime; +Cc: u-boot, vigneshr, Miquel Raynal, zhengxunli, jaimeliao

On Fri, Jul 15, 2022 at 2:47 PM liao jaime <jaimeliao.tw@gmail.com> wrote:
>
> Hi Jagan
> >
> > On Mon, Jul 4, 2022 at 11:43 AM JaimeLiao <jaimeliao.tw@gmail.com> wrote:
> > >
> > > Adding Macronix Octal flash for Octal DTR support.
> > >
> > > The octaflash series can be divided into the following types:
> > >
> > > MX25 series : Serial NOR Flash.
> > > MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> > > LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> > > LW/UW series : Support simultaneous Read-while-Write operation in multiple
> > >                bank architecture. Read-while-write feature which means read
> > >                data one bank while another bank is programing or erasing.
> > >
> >
> > Can you resend this patch on top of u-boot-spi/master
> This patchset is created in the newest version of U-boot(2022.07-rc5).

Yes. u-boot-spi/master has moved something further. please send only
this patch on top of it.

Jagan.

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash
  2022-07-15  9:18       ` Jagan Teki
@ 2022-07-15  9:21         ` liao jaime
  2022-07-15  9:30           ` Jagan Teki
  0 siblings, 1 reply; 12+ messages in thread
From: liao jaime @ 2022-07-15  9:21 UTC (permalink / raw)
  To: Jagan Teki; +Cc: u-boot, vigneshr, Miquel Raynal, zhengxunli, jaimeliao

Hi Jagan

>
> On Fri, Jul 15, 2022 at 2:47 PM liao jaime <jaimeliao.tw@gmail.com> wrote:
> >
> > Hi Jagan
> > >
> > > On Mon, Jul 4, 2022 at 11:43 AM JaimeLiao <jaimeliao.tw@gmail.com> wrote:
> > > >
> > > > Adding Macronix Octal flash for Octal DTR support.
> > > >
> > > > The octaflash series can be divided into the following types:
> > > >
> > > > MX25 series : Serial NOR Flash.
> > > > MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> > > > LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> > > > LW/UW series : Support simultaneous Read-while-Write operation in multiple
> > > >                bank architecture. Read-while-write feature which means read
> > > >                data one bank while another bank is programing or erasing.
> > > >
> > >
> > > Can you resend this patch on top of u-boot-spi/master
> > This patchset is created in the newest version of U-boot(2022.07-rc5).
>
> Yes. u-boot-spi/master has moved something further. please send only
> this patch on top of it.
Ok I will prepare for it.
Should I re-send this patch for new version v9 or keep on v8?

>
> Jagan.

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash
  2022-07-15  9:21         ` liao jaime
@ 2022-07-15  9:30           ` Jagan Teki
  0 siblings, 0 replies; 12+ messages in thread
From: Jagan Teki @ 2022-07-15  9:30 UTC (permalink / raw)
  To: liao jaime; +Cc: u-boot, vigneshr, Miquel Raynal, zhengxunli, jaimeliao

On Fri, Jul 15, 2022 at 2:51 PM liao jaime <jaimeliao.tw@gmail.com> wrote:
>
> Hi Jagan
>
> >
> > On Fri, Jul 15, 2022 at 2:47 PM liao jaime <jaimeliao.tw@gmail.com> wrote:
> > >
> > > Hi Jagan
> > > >
> > > > On Mon, Jul 4, 2022 at 11:43 AM JaimeLiao <jaimeliao.tw@gmail.com> wrote:
> > > > >
> > > > > Adding Macronix Octal flash for Octal DTR support.
> > > > >
> > > > > The octaflash series can be divided into the following types:
> > > > >
> > > > > MX25 series : Serial NOR Flash.
> > > > > MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> > > > > LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> > > > > LW/UW series : Support simultaneous Read-while-Write operation in multiple
> > > > >                bank architecture. Read-while-write feature which means read
> > > > >                data one bank while another bank is programing or erasing.
> > > > >
> > > >
> > > > Can you resend this patch on top of u-boot-spi/master
> > > This patchset is created in the newest version of U-boot(2022.07-rc5).
> >
> > Yes. u-boot-spi/master has moved something further. please send only
> > this patch on top of it.
> Ok I will prepare for it.
> Should I re-send this patch for new version v9 or keep on v8?

v9 4/4 enough.

^ permalink raw reply	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-07-15  9:30 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-04  6:12 [PATCH v8 0/4] Add octal DTR support for Macronix flash JaimeLiao
2022-07-04  6:12 ` [PATCH v8 1/4] mtd: spi-nor: add support for Macronix Octal flash JaimeLiao
2022-07-04  6:12 ` [PATCH v8 2/4] mtd: spi-nor-core: Adding different type of command extension in Soft Reset JaimeLiao
2022-07-07  4:49   ` Jagan Teki
2022-07-07  6:26     ` liao jaime
2022-07-04  6:12 ` [PATCH v8 3/4] mtd: spi-nor: Parse SFDP SCCR Map JaimeLiao
2022-07-04  6:12 ` [PATCH v8 4/4] mtd: spi-nor-core: Add support for Macronix Octal flash JaimeLiao
2022-07-15  9:04   ` Jagan Teki
2022-07-15  9:16     ` liao jaime
2022-07-15  9:18       ` Jagan Teki
2022-07-15  9:21         ` liao jaime
2022-07-15  9:30           ` Jagan Teki

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