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From: Andre Przywara <andre.przywara@arm.com>
To: Samuel Holland <samuel@sholland.org>
Cc: u-boot@lists.denx.de, Jagan Teki <jagan@amarulasolutions.com>,
	Dario Binacchi <dario.binacchi@amarulasolutions.com>,
	Hans de Goede <hdegoede@redhat.com>,
	Lukasz Majewski <lukma@denx.de>,
	Michael Trimarchi <michael@amarulasolutions.com>,
	Sean Anderson <seanga2@gmail.com>, Simon Glass <sjg@chromium.org>
Subject: Re: [PATCH 2/6] pinctrl: sunxi: Add NAND pinmuxes
Date: Mon, 18 Jul 2022 17:20:06 +0100	[thread overview]
Message-ID: <20220718172006.28729c32@donnerap.cambridge.arm.com> (raw)
In-Reply-To: <20220714031526.33697-3-samuel@sholland.org>

On Wed, 13 Jul 2022 22:15:22 -0500
Samuel Holland <samuel@sholland.org> wrote:

Hi,

> NAND is always at function 2 on port C.

Indeed.

> 
> Pin lists and mux values were taken from the Linux drivers.

Compared against the manuals. I didn't bother the check the pin ranges (I
think some additional CS pins were not covered by the comments), but that
shouldn't matter anyways.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

> Signed-off-by: Samuel Holland <samuel@sholland.org>

Cheers,
Andre

P.S.: I see that the A83T kernel pinctrl driver uses "nand" for *some* pins
instead of "nand0", not sure if that should to be fixed, or if it's too
late for that (not that NAND is mentioned at all in the A83T DT files ...)

> ---
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 9ce2bc1b3afb..b10e3e7b0690 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -268,6 +268,7 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
>  #endif
>  	{ "mmc2",	3 },	/* PC6-PC15 */
>  	{ "mmc3",	2 },	/* PI4-PI9 */
> +	{ "nand0",	2 },	/* PC0-PC24 */
>  	{ "spi0",	3 },	/* PC0-PC2, PC23 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
> @@ -292,6 +293,7 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG3-PG8 */
>  	{ "mmc2",	3 },	/* PC6-PC15 */
> +	{ "nand0",	2 },	/* PC0-PC19 */
>  	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
> @@ -318,6 +320,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC6-PC15, PC24 */
>  	{ "mmc3",	4 },	/* PC6-PC15, PC24 */
> +	{ "nand0",	2 },	/* PC0-PC26 */
>  	{ "spi0",	3 },	/* PC0-PC2, PC27 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
> @@ -361,6 +364,7 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
>  	{ "mmc1",	4 },	/* PG0-PG5 */
>  #endif
>  	{ "mmc2",	3 },	/* PC5-PC15, PC24 */
> +	{ "nand0",	2 },	/* PC0-PC24 */
>  	{ "spi0",	3 },	/* PC0-PC2, PC23 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
> @@ -384,6 +388,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC5-PC16 */
> +	{ "nand0",	2 },	/* PC0-PC16 */
>  	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
> @@ -421,6 +426,7 @@ static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC5-PC16 */
> +	{ "nand0",	2 },	/* PC0-PC16 */
>  	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
> @@ -447,6 +453,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC5-PC16 */
> +	{ "nand0",	2 },	/* PC0-PC18 */
>  	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
> @@ -487,6 +494,7 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC5-PC16 */
> +	{ "nand0",	2 },	/* PC0-PC16 */
>  	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
> @@ -553,6 +561,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC6-PC16 */
> +	{ "nand0",	2 },	/* PC0-PC18 */
>  	{ "spi0",	3 },	/* PC0-PC2, PC19 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
> @@ -592,6 +601,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC1-PC16 */
> +	{ "nand0",	2 },	/* PC0-PC16 */
>  	{ "pwm",	2 },	/* PD22 */
>  	{ "spi0",	4 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -633,6 +643,7 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC1-PC16 */
> +	{ "nand0",	2 },	/* PC0-PC16 */
>  	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
> @@ -659,6 +670,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC1-PC14 */
> +	{ "nand0",	2 },	/* PC0-PC16 */
>  	{ "spi0",	4 },	/* PC0-PC7 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
> @@ -696,6 +708,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC0-PC16 */
> +	{ "nand0",	2 },	/* PC0-PC16 */
>  	{ "spi0",	4 },	/* PC0-PC7, PC15-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */


  parent reply	other threads:[~2022-07-18 16:20 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-14  3:15 [PATCH 0/6] mtd: nand: sunxi: Convert to devicetree and the driver model Samuel Holland
2022-07-14  3:15 ` [PATCH 1/6] clk: sunxi: Add NAND clocks and resets Samuel Holland
2022-07-15  9:25   ` Jagan Teki
2022-07-18 16:10   ` Andre Przywara
2022-07-18 23:50     ` Samuel Holland
2022-07-14  3:15 ` [PATCH 2/6] pinctrl: sunxi: Add NAND pinmuxes Samuel Holland
2022-07-15  9:26   ` Jagan Teki
2022-07-18 16:20   ` Andre Przywara [this message]
2022-07-18 17:26     ` Michael Nazzareno Trimarchi
2022-07-19  2:04     ` Samuel Holland
2022-07-14  3:15 ` [PATCH 3/6] mtd: nand: sunxi: Remove an unnecessary check Samuel Holland
2022-07-17 14:01   ` Michael Nazzareno Trimarchi
2022-07-14  3:15 ` [PATCH 4/6] mtd: nand: sunxi: Convert from fdtdec to ofnode Samuel Holland
2022-07-14  3:15 ` [PATCH 5/6] mtd: nand: sunxi: Convert to the driver model Samuel Holland
2022-07-17 14:10   ` Michael Nazzareno Trimarchi
2022-07-14  3:15 ` [PATCH 6/6] mtd: nand: sunxi: Pass the device to the init function Samuel Holland
2022-07-14  5:38 ` [PATCH 0/6] mtd: nand: sunxi: Convert to devicetree and the driver model Michael Nazzareno Trimarchi
2022-07-14  6:47   ` Icenowy Zheng

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