* [PATCH v2 1/8] vf610: synchronise device tree with linux
2022-08-26 18:31 [PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1 Marcel Ziswiler
@ 2022-08-26 18:31 ` Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 2/8] imxrt1020: fix lpuart issue in common u-boot device tree Marcel Ziswiler
` (6 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Marcel Ziswiler @ 2022-08-26 18:31 UTC (permalink / raw)
To: u-boot
Cc: Fabio Estevam, Jesse Taube, Giulio Benetti, Marcel Ziswiler,
Stefano Babic, Wolfgang Denk
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Synchronise device tree with linux v6.0-rc1 plus the recent DDR pinmux
addition still being in-flight.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
(no changes since v1)
arch/arm/dts/vf610-pinfunc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h
index 740276431aa..b7b7322a2d1 100644
--- a/arch/arm/dts/vf610-pinfunc.h
+++ b/arch/arm/dts/vf610-pinfunc.h
@@ -802,7 +802,6 @@
#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0
#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0
#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
-
#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0
#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0
#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0
@@ -853,4 +852,5 @@
#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0
#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0
#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0
+
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 2/8] imxrt1020: fix lpuart issue in common u-boot device tree
2022-08-26 18:31 [PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1 Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 1/8] vf610: synchronise device tree with linux Marcel Ziswiler
@ 2022-08-26 18:31 ` Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 3/8] imxrt1050: synchronise device tree with linux Marcel Ziswiler
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Marcel Ziswiler @ 2022-08-26 18:31 UTC (permalink / raw)
To: u-boot
Cc: Fabio Estevam, Jesse Taube, Giulio Benetti, Marcel Ziswiler,
NXP i.MX U-Boot Team, Stefano Babic
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Fix lpuart issue in common U-Boot device tree.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
(no changes since v1)
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 ++++---
arch/arm/dts/imxrt1020-evk.dts | 1 -
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 9e1b074d2e7..7cab486f5fa 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -67,9 +67,6 @@
imxrt1020-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
u-boot,dm-spl;
@@ -81,6 +78,10 @@
};
};
+&pinctrl_lpuart1 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index 22ae5ed7359..d4d1de4ea84 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "imxrt1020.dtsi"
-#include "imxrt1020-evk-u-boot.dtsi"
#include "imxrt1020-pinfunc.h"
/ {
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 3/8] imxrt1050: synchronise device tree with linux
2022-08-26 18:31 [PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1 Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 1/8] vf610: synchronise device tree with linux Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 2/8] imxrt1020: fix lpuart issue in common u-boot device tree Marcel Ziswiler
@ 2022-08-26 18:31 ` Marcel Ziswiler
2022-08-28 6:50 ` Jesse Taube
2022-08-26 18:31 ` [PATCH v2 4/8] imx8ulp: " Marcel Ziswiler
` (4 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Marcel Ziswiler @ 2022-08-26 18:31 UTC (permalink / raw)
To: u-boot
Cc: Fabio Estevam, Jesse Taube, Giulio Benetti, Marcel Ziswiler,
NXP i.MX U-Boot Team, Stefano Babic
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 155 ++++++++++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++-----------------
arch/arm/dts/imxrt1050-pinfunc.h | 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 ++++++-------
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 248 insertions(+), 343 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448a..7db53b19c2f 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,6 +4,8 @@
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
+#include <dt-bindings/memory/imxrt-sdram.h>
+
/ {
chosen {
u-boot,dm-spl;
@@ -15,6 +17,52 @@
soc {
u-boot,dm-spl;
+
+ semc@402f0000 {
+ compatible = "fsl,imxrt-semc";
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ reg = <0x402f0000 0x4000>;
+ status = "okay";
+ u-boot,dm-spl;
+
+ /*
+ * Memory configuration from sdram datasheet IS42S16160J-6BLI
+ */
+ fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
+ MUX_CSX0_SDRAM_CS1
+ 0
+ 0
+ 0
+ 0>;
+ fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
+ BL_8
+ COL_9BITS
+ CL_3>;
+ fsl,sdram-timing = /bits/ 8 <0x2
+ 0x2
+ 0x9
+ 0x1
+ 0x5
+ 0x6
+
+ 0x20
+ 0x09
+ 0x01
+ 0x00
+
+ 0x04
+ 0x0A
+ 0x21
+ 0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x80000000>;
+ fsl,memory-size = <MEM_SIZE_32M>;
+ u-boot,dm-spl;
+ };
+ };
};
};
@@ -50,7 +98,7 @@
u-boot,dm-spl;
};
-&gpt1 {
+&gpt {
u-boot,dm-spl;
};
@@ -58,33 +106,108 @@
u-boot,dm-spl;
};
-&semc {
- u-boot,dm-spl;
-
- bank1: bank@0 {
- u-boot,dm-spl;
- };
-};
-
&iomuxc {
u-boot,dm-spl;
imxrt1050-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
- };
-
- pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1 /* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1 /* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1 /* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1 /* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1 /* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
+ 0xf1 /* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
+ 0xf1 /* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
+ 0xf1 /* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
+ 0xf1 /* SEMC_DM0 */
+ MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+ 0xf1 /* SEMC_A0 */
+ MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
+ 0xf1 /* SEMC_A1 */
+ MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
+ 0xf1 /* SEMC_A2 */
+ MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
+ 0xf1 /* SEMC_A3 */
+ MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
+ 0xf1 /* SEMC_A4 */
+ MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
+ 0xf1 /* SEMC_A5 */
+ MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
+ 0xf1 /* SEMC_A6 */
+ MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
+ 0xf1 /* SEMC_A7 */
+ MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
+ 0xf1 /* SEMC_A8 */
+ MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
+ 0xf1 /* SEMC_A9 */
+ MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
+ 0xf1 /* SEMC_A11 */
+ MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
+ 0xf1 /* SEMC_A12 */
+ MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
+ 0xf1 /* SEMC_BA0 */
+ MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
+ 0xf1 /* SEMC_BA1 */
+ MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
+ 0xf1 /* SEMC_A10 */
+ MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
+ 0xf1 /* SEMC_CAS */
+ MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
+ 0xf1 /* SEMC_RAS */
+ MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
+ 0xf1 /* SEMC_CLK */
+ MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
+ 0xf1 /* SEMC_CKE */
+ MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
+ 0xf1 /* SEMC_WE */
+ MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
+ 0xf1 /* SEMC_CS0 */
+ MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
+ 0xf1 /* SEMC_D8 */
+ MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
+ 0xf1 /* SEMC_D9 */
+ MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
+ 0xf1 /* SEMC_D10 */
+ MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
+ 0xf1 /* SEMC_D11 */
+ MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
+ 0xf1 /* SEMC_D12 */
+ MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
+ 0xf1 /* SEMC_D13 */
+ MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
+ 0xf1 /* SEMC_D14 */
+ MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
+ 0xf1 /* SEMC_D15 */
+ MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
+ 0xf1 /* SEMC_DM1 */
+ MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
+ (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
+ >;
u-boot,dm-spl;
};
};
};
+&pinctrl_lpuart1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc0 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index fb2da3adfcf..6a9c10decf5 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
@@ -6,7 +6,6 @@
/dts-v1/;
#include "imxrt1050.dtsi"
-#include "imxrt1050-evk-u-boot.dtsi"
#include "imxrt1050-pinfunc.h"
/ {
@@ -14,210 +13,52 @@
compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- tick-timer = &gpt1;
+ stdout-path = &lpuart1;
};
- memory {
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ };
+
+ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x2000000>;
};
};
-&lpuart1 { /* console */
+&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
-&semc {
- /*
- * Memory configuration from sdram datasheet IS42S16160J-6BLI
- */
- fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
- MUX_CSX0_SDRAM_CS1
- 0
- 0
- 0
- 0>;
- fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
- BL_8
- COL_9BITS
- CL_3>;
- fsl,sdram-timing = /bits/ 8 <0x2
- 0x2
- 0x9
- 0x1
- 0x5
- 0x6
-
- 0x20
- 0x09
- 0x01
- 0x00
-
- 0x04
- 0x0A
- 0x21
- 0x50>;
-
- bank1: bank@0 {
- fsl,base-address = <0x80000000>;
- fsl,memory-size = <MEM_SIZE_32M>;
- };
-};
-
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart1>;
-
- imxrt1050-evk {
- pinctrl_lpuart1: lpuart1grp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
- 0xf1
- MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
- 0xf1
- >;
- };
-
- pinctrl_semc: semcgrp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
- 0xf1 /* SEMC_D0 */
- MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
- 0xf1 /* SEMC_D1 */
- MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
- 0xf1 /* SEMC_D2 */
- MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
- 0xf1 /* SEMC_D3 */
- MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
- 0xf1 /* SEMC_D4 */
- MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
- 0xf1 /* SEMC_D5 */
- MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
- 0xf1 /* SEMC_D6 */
- MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
- 0xf1 /* SEMC_D7 */
- MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
- 0xf1 /* SEMC_DM0 */
- MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
- 0xf1 /* SEMC_A0 */
- MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
- 0xf1 /* SEMC_A1 */
- MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
- 0xf1 /* SEMC_A2 */
- MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
- 0xf1 /* SEMC_A3 */
- MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
- 0xf1 /* SEMC_A4 */
- MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
- 0xf1 /* SEMC_A5 */
- MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
- 0xf1 /* SEMC_A6 */
- MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
- 0xf1 /* SEMC_A7 */
- MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
- 0xf1 /* SEMC_A8 */
- MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
- 0xf1 /* SEMC_A9 */
- MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
- 0xf1 /* SEMC_A11 */
- MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
- 0xf1 /* SEMC_A12 */
- MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
- 0xf1 /* SEMC_BA0 */
- MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
- 0xf1 /* SEMC_BA1 */
- MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
- 0xf1 /* SEMC_A10 */
- MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
- 0xf1 /* SEMC_CAS */
- MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
- 0xf1 /* SEMC_RAS */
- MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
- 0xf1 /* SEMC_CLK */
- MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
- 0xf1 /* SEMC_CKE */
- MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
- 0xf1 /* SEMC_WE */
- MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
- 0xf1 /* SEMC_CS0 */
- MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
- 0xf1 /* SEMC_D8 */
- MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
- 0xf1 /* SEMC_D9 */
- MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
- 0xf1 /* SEMC_D10 */
- MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
- 0xf1 /* SEMC_D11 */
- MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
- 0xf1 /* SEMC_D12 */
- MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
- 0xf1 /* SEMC_D13 */
- MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
- 0xf1 /* SEMC_D14 */
- MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
- 0xf1 /* SEMC_D15 */
- MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
- 0xf1 /* SEMC_DM1 */
- MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
- (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
- >;
- };
-
- pinctrl_usdhc0: usdhc0grp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
- 0x1B000
- MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
- 0xB069
- MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
- 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
- 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
- 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
- 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
- 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
- 0x17061
- >;
- };
-
- pinctrl_lcdif: lcdifgrp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
- MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
- MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
- >;
- };
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
+ MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
+ >;
};
-};
-&gpt1 {
- status = "okay";
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
+ MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
+ MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
+ >;
+ };
};
&usdhc1 {
@@ -226,42 +67,6 @@
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>;
- status = "okay";
-
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
-};
-
-&lcdif {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcdif>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <16>;
- bus-width = <16>;
-
- display-timings {
- timing0: timing0 {
- clock-frequency = <9300000>;
- hactive = <480>;
- vactive = <272>;
- hback-porch = <4>;
- hfront-porch = <8>;
- vback-porch = <4>;
- vfront-porch = <8>;
- hsync-len = <41>;
- vsync-len = <10>;
- de-active = <1>;
- pixelclk-active = <0>;
- hsync-active = <0>;
- vsync-active = <0>;
- };
- };
- };
-};
-
-&usbotg1 {
- dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h
index a29031ab3de..22c14a3262a 100644
--- a/arch/arm/dts/imxrt1050-pinfunc.h
+++ b/arch/arm/dts/imxrt1050-pinfunc.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 09f4712af68..03e6a858a7b 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
@@ -8,53 +8,37 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1050-clock.h>
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/memory/imxrt-sdram.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
- aliases {
- display0 = &lcdif;
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
- mmc0 = &usdhc1;
- serial0 = &lpuart1;
- usbphy0 = &usbphy1;
- };
-
clocks {
osc: osc {
- compatible = "fsl,imx-osc", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
- };
- soc {
- semc: semc@402f0000 {
- compatible = "fsl,imxrt-semc";
- reg = <0x402f0000 0x4000>;
- clocks = <&clks IMXRT1050_CLK_SEMC>;
- pinctrl-0 = <&pinctrl_semc>;
- pinctrl-names = "default";
- status = "okay";
+ osc3M: osc3M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3000000>;
};
+ };
+ soc {
lpuart1: serial@40184000 {
- compatible = "fsl,imxrt-lpuart";
+ compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x40184000 0x4000>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <20>;
clocks = <&clks IMXRT1050_CLK_LPUART1>;
- clock-names = "per";
+ clock-names = "ipg";
status = "disabled";
};
- iomuxc: iomuxc@401f8000 {
- compatible = "fsl,imxrt-iomuxc";
+ iomuxc: pinctrl@401f8000 {
+ compatible = "fsl,imxrt1050-iomuxc";
reg = <0x401f8000 0x4000>;
fsl,mux_mask = <0x7>;
};
@@ -64,31 +48,61 @@
reg = <0x400d8000 0x4000>;
};
- clks: ccm@400fc000 {
+ clks: clock-controller@400fc000 {
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <95>, <96>;
+ clocks = <&osc>;
+ clock-names = "osc";
#clock-cells = <1>;
- };
-
- usdhc1: usdhc@402c0000 {
- compatible = "fsl,imxrt-usdhc";
- reg = <0x402c0000 0x10000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMXRT1050_CLK_USDHC1>;
- clock-names = "per";
+ assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL1_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL2_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL3_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
+ <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
+ assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
+ <&clks IMXRT1050_CLK_PLL1_ARM>,
+ <&clks IMXRT1050_CLK_PLL2_SYS>,
+ <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
+ <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
+ <&clks IMXRT1050_CLK_PLL2_SYS>;
+ };
+
+ edma1: dma-controller@400e8000 {
+ #dma-cells = <2>;
+ compatible = "fsl,imx7ulp-edma";
+ reg = <0x400e8000 0x4000>,
+ <0x400ec000 0x4000>;
+ dma-channels = <32>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
+ clock-names = "dma", "dmamux0";
+ clocks = <&clks IMXRT1050_CLK_DMA>,
+ <&clks IMXRT1050_CLK_DMA_MUX>;
+ };
+
+ usdhc1: mmc@402c0000 {
+ compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x402c0000 0x4000>;
+ interrupts = <110>;
+ clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
+ <&clks IMXRT1050_CLK_OSC>,
+ <&clks IMXRT1050_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
bus-width = <4>;
+ fsl,wp-controller;
+ no-1-8-v;
+ max-frequency = <4000000>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
status = "disabled";
};
gpio1: gpio@401b8000 {
- compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <80>, <81>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -96,10 +110,9 @@
};
gpio2: gpio@401bc000 {
- compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <82>, <83>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -107,10 +120,9 @@
};
gpio3: gpio@401c0000 {
- compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <84>, <85>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -118,10 +130,9 @@
};
gpio4: gpio@401c4000 {
- compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x401c4000 0x4000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <86>, <87>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -129,60 +140,21 @@
};
gpio5: gpio@400c0000 {
- compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
reg = <0x400c0000 0x4000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <88>, <89>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
- lcdif: lcdif@402b8000 {
- compatible = "fsl,imxrt-lcdif";
- reg = <0x402b8000 0x4000>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
- <&clks IMXRT1050_CLK_LCDIF_APB>;
- clock-names = "pix", "axi";
- assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
- assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
- status = "disabled";
- };
-
- gpt1: gpt1@401ec000 {
- compatible = "fsl,imxrt-gpt";
+ gpt: timer@401ec000 {
+ compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
reg = <0x401ec000 0x4000>;
interrupts = <100>;
- clocks = <&osc>;
- status = "disabled";
- };
-
- usbphy1: usbphy@400d9000 {
- compatible = "fsl,imxrt-usbphy";
- reg = <0x400d9000 0x1000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- usbmisc: usbmisc@402e0800 {
- #index-cells = <1>;
- compatible = "fsl,imxrt-usbmisc";
- reg = <0x402e0800 0x200>;
- clocks = <&clks IMXRT1050_CLK_USBOH3>;
- };
-
- usbotg1: usb@402e0000 {
- compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
- reg = <0x402e0000 0x200>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMXRT1050_CLK_USBOH3>;
- fsl,usbphy = <&usbphy1>;
- fsl,usbmisc = <&usbmisc 0>;
- ahb-burst-config = <0x0>;
- tx-burst-size-dword = <0x10>;
- rx-burst-size-dword = <0x10>;
- status = "disabled";
+ clocks = <&osc3M>;
+ clock-names = "per";
};
};
};
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h
index f74dbbcf937..93bef0832d1 100644
--- a/include/dt-bindings/clock/imxrt1050-clock.h
+++ b/include/dt-bindings/clock/imxrt1050-clock.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright(C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
@@ -62,6 +62,11 @@
#define IMXRT1050_CLK_PLL7_USB_HOST 53
#define IMXRT1050_CLK_LCDIF_PIX 54
#define IMXRT1050_CLK_USBOH3 55
-#define IMXRT1050_CLK_END 56
+#define IMXRT1050_CLK_IPG_PDOF 56
+#define IMXRT1050_CLK_PER_CLK_SEL 57
+#define IMXRT1050_CLK_PER_PDOF 58
+#define IMXRT1050_CLK_DMA 59
+#define IMXRT1050_CLK_DMA_MUX 60
+#define IMXRT1050_CLK_END 61
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/8] imxrt1050: synchronise device tree with linux
2022-08-26 18:31 ` [PATCH v2 3/8] imxrt1050: synchronise device tree with linux Marcel Ziswiler
@ 2022-08-28 6:50 ` Jesse Taube
2022-10-22 12:57 ` Marcel Ziswiler
0 siblings, 1 reply; 12+ messages in thread
From: Jesse Taube @ 2022-08-28 6:50 UTC (permalink / raw)
To: Marcel Ziswiler, u-boot
Cc: Fabio Estevam, Giulio Benetti, Marcel Ziswiler,
NXP i.MX U-Boot Team, Stefano Babic
On 8/26/22 14:31, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Synchronise device tree with linux v6.0-rc1.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v2:
> - imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
>
> arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 155 ++++++++++--
> arch/arm/dts/imxrt1050-evk.dts | 257 +++-----------------
> arch/arm/dts/imxrt1050-pinfunc.h | 2 +-
> arch/arm/dts/imxrt1050.dtsi | 168 ++++++-------
> include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
> 5 files changed, 248 insertions(+), 343 deletions(-)
>
> diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> index 617cece448a..7db53b19c2f 100644
> --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> @@ -4,6 +4,8 @@
> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> */
>
> +#include <dt-bindings/memory/imxrt-sdram.h>
> +
#include "imxrt1050-pinfunc.h"
> / {
> chosen {
> u-boot,dm-spl;
diff says `tick-timer = &gpt;` its important for boot
> @@ -15,6 +17,52 @@
>
> soc {
> u-boot,dm-spl;
> +
> + semc@402f0000 {
> + compatible = "fsl,imxrt-semc";
> + clocks = <&clks IMXRT1050_CLK_SEMC>;
> + pinctrl-0 = <&pinctrl_semc>;
> + pinctrl-names = "default";
> + reg = <0x402f0000 0x4000>;
> + status = "okay";
> + u-boot,dm-spl;
I dont think this part under should go here tell me if im wrong. It
should be move outside as a reference.
> + /*
> + * Memory configuration from sdram datasheet IS42S16160J-6BLI
> + */
> + fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
> + MUX_CSX0_SDRAM_CS1
> + 0
> + 0
> + 0
> + 0>;
> + fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
> + BL_8
> + COL_9BITS
> + CL_3>;
> + fsl,sdram-timing = /bits/ 8 <0x2
> + 0x2
> + 0x9
> + 0x1
> + 0x5
> + 0x6
> +
> + 0x20
> + 0x09
> + 0x01
> + 0x00
> +
> + 0x04
> + 0x0A
> + 0x21
> + 0x50>;
> +
> + bank1: bank@0 {
> + fsl,base-address = <0x80000000>;
> + fsl,memory-size = <MEM_SIZE_32M>;
> + u-boot,dm-spl;
> + };
> + };
> };
> };
>
> @@ -50,7 +98,7 @@
> u-boot,dm-spl;
> };
>
> -&gpt1 {
> +&gpt {
Add diff:
clocks = <&osc>;
compatible = "fsl,imxrt-gpt";
status = "okay";
> u-boot,dm-spl;
> };
>
> @@ -58,33 +106,108 @@
> u-boot,dm-spl;
> };
>
> -&semc {
> - u-boot,dm-spl;
> -
> - bank1: bank@0 {
> - u-boot,dm-spl;
> - };
> -};
> -
> &iomuxc {
> u-boot,dm-spl;
>
> imxrt1050-evk {drop unneeded node ^^^
> u-boot,dm-spl;
> - pinctrl_lpuart1: lpuart1grp {
> - u-boot,dm-spl;
> - };
>
> pinctrl_semc: semcgrp {
> - u-boot,dm-spl;
> - };
> -
> - pinctrl_usdhc0: usdhc0grp {
> + fsl,pins = <
> + MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
> + 0xf1 /* SEMC_D0 */
> + MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
> + 0xf1 /* SEMC_D1 */
> + MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
> + 0xf1 /* SEMC_D2 */
> + MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
> + 0xf1 /* SEMC_D3 */
> + MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
> + 0xf1 /* SEMC_D4 */
> + MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
> + 0xf1 /* SEMC_D5 */
> + MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
> + 0xf1 /* SEMC_D6 */
> + MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
> + 0xf1 /* SEMC_D7 */
> + MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
> + 0xf1 /* SEMC_DM0 */
> + MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> + 0xf1 /* SEMC_A0 */
> + MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
> + 0xf1 /* SEMC_A1 */
> + MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
> + 0xf1 /* SEMC_A2 */
> + MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
> + 0xf1 /* SEMC_A3 */
> + MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
> + 0xf1 /* SEMC_A4 */
> + MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
> + 0xf1 /* SEMC_A5 */
> + MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
> + 0xf1 /* SEMC_A6 */
> + MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
> + 0xf1 /* SEMC_A7 */
> + MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
> + 0xf1 /* SEMC_A8 */
> + MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
> + 0xf1 /* SEMC_A9 */
> + MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
> + 0xf1 /* SEMC_A11 */
> + MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
> + 0xf1 /* SEMC_A12 */
> + MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
> + 0xf1 /* SEMC_BA0 */
> + MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
> + 0xf1 /* SEMC_BA1 */
> + MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
> + 0xf1 /* SEMC_A10 */
> + MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
> + 0xf1 /* SEMC_CAS */
> + MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
> + 0xf1 /* SEMC_RAS */
> + MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
> + 0xf1 /* SEMC_CLK */
> + MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
> + 0xf1 /* SEMC_CKE */
> + MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
> + 0xf1 /* SEMC_WE */
> + MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
> + 0xf1 /* SEMC_CS0 */
> + MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
> + 0xf1 /* SEMC_D8 */
> + MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
> + 0xf1 /* SEMC_D9 */
> + MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
> + 0xf1 /* SEMC_D10 */
> + MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
> + 0xf1 /* SEMC_D11 */
> + MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
> + 0xf1 /* SEMC_D12 */
> + MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
> + 0xf1 /* SEMC_D13 */
> + MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
> + 0xf1 /* SEMC_D14 */
> + MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
> + 0xf1 /* SEMC_D15 */
> + MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
> + 0xf1 /* SEMC_DM1 */
> + MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
> + (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
> + >;
> u-boot,dm-spl;
> };
> };
> };
>
> +&pinctrl_lpuart1 {
Add diff:
compatible = "fsl,imxrt-lpuart";
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc0 {
Add diff:
compatible = "fsl,imxrt-usdhc";
I tested this
https://github.com/Mr-Bossman/u-boot/commit/42a7f430d761bb4d44f646a27649deda15352f2e
Some note for future, check if the compatibles are the same they arent
here so the soc.dtsi will be broken. Also wait a bit for other people to
resopnd to patches before sending out v2 because no one commented on the
other patches yet.
Thanks,
Jesse
> + u-boot,dm-spl;
> +};
> +
> &usdhc1 {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
> index fb2da3adfcf..6a9c10decf5 100644
> --- a/arch/arm/dts/imxrt1050-evk.dts
> +++ b/arch/arm/dts/imxrt1050-evk.dts
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Copyright (C) 2019
> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> @@ -6,7 +6,6 @@
>
> /dts-v1/;
> #include "imxrt1050.dtsi"
> -#include "imxrt1050-evk-u-boot.dtsi"
> #include "imxrt1050-pinfunc.h"
>
> / {
> @@ -14,210 +13,52 @@
> compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
>
> chosen {
> - bootargs = "root=/dev/ram";
> - stdout-path = "serial0:115200n8";
> - tick-timer = &gpt1;
> + stdout-path = &lpuart1;
> };
>
> - memory {
> + aliases {
> + gpio0 = &gpio1;
> + gpio1 = &gpio2;
> + gpio2 = &gpio3;
> + gpio3 = &gpio4;
> + gpio4 = &gpio5;
> + mmc0 = &usdhc1;
> + serial0 = &lpuart1;
> + };
> +
> + memory@80000000 {
> device_type = "memory";
> reg = <0x80000000 0x2000000>;
> };
> };
>
> -&lpuart1 { /* console */
> +&lpuart1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_lpuart1>;
> status = "okay";
> };
>
> -&semc {
> - /*
> - * Memory configuration from sdram datasheet IS42S16160J-6BLI
> - */
> - fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
> - MUX_CSX0_SDRAM_CS1
> - 0
> - 0
> - 0
> - 0>;
> - fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
> - BL_8
> - COL_9BITS
> - CL_3>;
> - fsl,sdram-timing = /bits/ 8 <0x2
> - 0x2
> - 0x9
> - 0x1
> - 0x5
> - 0x6
> -
> - 0x20
> - 0x09
> - 0x01
> - 0x00
> -
> - 0x04
> - 0x0A
> - 0x21
> - 0x50>;
> -
> - bank1: bank@0 {
> - fsl,base-address = <0x80000000>;
> - fsl,memory-size = <MEM_SIZE_32M>;
> - };
> -};
> -
> &iomuxc {
> pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_lpuart1>;
> -
> - imxrt1050-evk {
> - pinctrl_lpuart1: lpuart1grp {
> - fsl,pins = <
> - MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
> - 0xf1
> - MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
> - 0xf1
> - >;
> - };
> -
> - pinctrl_semc: semcgrp {
> - fsl,pins = <
> - MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
> - 0xf1 /* SEMC_D0 */
> - MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
> - 0xf1 /* SEMC_D1 */
> - MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
> - 0xf1 /* SEMC_D2 */
> - MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
> - 0xf1 /* SEMC_D3 */
> - MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
> - 0xf1 /* SEMC_D4 */
> - MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
> - 0xf1 /* SEMC_D5 */
> - MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
> - 0xf1 /* SEMC_D6 */
> - MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
> - 0xf1 /* SEMC_D7 */
> - MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
> - 0xf1 /* SEMC_DM0 */
> - MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> - 0xf1 /* SEMC_A0 */
> - MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
> - 0xf1 /* SEMC_A1 */
> - MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
> - 0xf1 /* SEMC_A2 */
> - MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
> - 0xf1 /* SEMC_A3 */
> - MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
> - 0xf1 /* SEMC_A4 */
> - MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
> - 0xf1 /* SEMC_A5 */
> - MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
> - 0xf1 /* SEMC_A6 */
> - MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
> - 0xf1 /* SEMC_A7 */
> - MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
> - 0xf1 /* SEMC_A8 */
> - MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
> - 0xf1 /* SEMC_A9 */
> - MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
> - 0xf1 /* SEMC_A11 */
> - MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
> - 0xf1 /* SEMC_A12 */
> - MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
> - 0xf1 /* SEMC_BA0 */
> - MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
> - 0xf1 /* SEMC_BA1 */
> - MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
> - 0xf1 /* SEMC_A10 */
> - MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
> - 0xf1 /* SEMC_CAS */
> - MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
> - 0xf1 /* SEMC_RAS */
> - MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
> - 0xf1 /* SEMC_CLK */
> - MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
> - 0xf1 /* SEMC_CKE */
> - MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
> - 0xf1 /* SEMC_WE */
> - MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
> - 0xf1 /* SEMC_CS0 */
> - MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
> - 0xf1 /* SEMC_D8 */
> - MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
> - 0xf1 /* SEMC_D9 */
> - MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
> - 0xf1 /* SEMC_D10 */
> - MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
> - 0xf1 /* SEMC_D11 */
> - MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
> - 0xf1 /* SEMC_D12 */
> - MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
> - 0xf1 /* SEMC_D13 */
> - MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
> - 0xf1 /* SEMC_D14 */
> - MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
> - 0xf1 /* SEMC_D15 */
> - MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
> - 0xf1 /* SEMC_DM1 */
> - MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
> - (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
> - >;
> - };
> -
> - pinctrl_usdhc0: usdhc0grp {
> - fsl,pins = <
> - MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
> - 0x1B000
> - MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
> - 0xB069
> - MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
> - 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
> - 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
> - 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
> - 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
> - 0x17061
> - MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
> - 0x17061
> - >;
> - };
> -
> - pinctrl_lcdif: lcdifgrp {
> - fsl,pins = <
> - MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
> - MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
> - MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
> - >;
> - };
> + pinctrl_lpuart1: lpuart1grp {
> + fsl,pins = <
> + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
> + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
> + >;
> };
> -};
>
> -&gpt1 {
> - status = "okay";
> + pinctrl_usdhc0: usdhc0grp {
> + fsl,pins = <
> + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
> + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
> + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
> + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
> + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
> + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
> + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
> + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
> + >;
> + };
> };
>
> &usdhc1 {
> @@ -226,42 +67,6 @@
> pinctrl-1 = <&pinctrl_usdhc0>;
> pinctrl-2 = <&pinctrl_usdhc0>;
> pinctrl-3 = <&pinctrl_usdhc0>;
> - status = "okay";
> -
> cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
> -};
> -
> -&lcdif {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_lcdif>;
> - display = <&display0>;
> - status = "okay";
> -
> - display0: display0 {
> - bits-per-pixel = <16>;
> - bus-width = <16>;
> -
> - display-timings {
> - timing0: timing0 {
> - clock-frequency = <9300000>;
> - hactive = <480>;
> - vactive = <272>;
> - hback-porch = <4>;
> - hfront-porch = <8>;
> - vback-porch = <4>;
> - vfront-porch = <8>;
> - hsync-len = <41>;
> - vsync-len = <10>;
> - de-active = <1>;
> - pixelclk-active = <0>;
> - hsync-active = <0>;
> - vsync-active = <0>;
> - };
> - };
> - };
> -};
> -
> -&usbotg1 {
> - dr_mode = "host";
> status = "okay";
> };
> diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h
> index a29031ab3de..22c14a3262a 100644
> --- a/arch/arm/dts/imxrt1050-pinfunc.h
> +++ b/arch/arm/dts/imxrt1050-pinfunc.h
> @@ -1,4 +1,4 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> /*
> * Copyright (C) 2019
> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
> index 09f4712af68..03e6a858a7b 100644
> --- a/arch/arm/dts/imxrt1050.dtsi
> +++ b/arch/arm/dts/imxrt1050.dtsi
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Copyright (C) 2019
> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> @@ -8,53 +8,37 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/imxrt1050-clock.h>
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/memory/imxrt-sdram.h>
>
> / {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - aliases {
> - display0 = &lcdif;
> - gpio0 = &gpio1;
> - gpio1 = &gpio2;
> - gpio2 = &gpio3;
> - gpio3 = &gpio4;
> - gpio4 = &gpio5;
> - mmc0 = &usdhc1;
> - serial0 = &lpuart1;
> - usbphy0 = &usbphy1;
> - };
> -
> clocks {
> osc: osc {
> - compatible = "fsl,imx-osc", "fixed-clock";
> + compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <24000000>;
> };
> - };
>
> - soc {
> - semc: semc@402f0000 {
> - compatible = "fsl,imxrt-semc";
> - reg = <0x402f0000 0x4000>;
> - clocks = <&clks IMXRT1050_CLK_SEMC>;
> - pinctrl-0 = <&pinctrl_semc>;
> - pinctrl-names = "default";
> - status = "okay";
> + osc3M: osc3M {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <3000000>;
> };
> + };
>
> + soc {
> lpuart1: serial@40184000 {
> - compatible = "fsl,imxrt-lpuart";
> + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
> reg = <0x40184000 0x4000>;
> - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <20>;
> clocks = <&clks IMXRT1050_CLK_LPUART1>;
> - clock-names = "per";
> + clock-names = "ipg";
> status = "disabled";
> };
>
> - iomuxc: iomuxc@401f8000 {
> - compatible = "fsl,imxrt-iomuxc";
> + iomuxc: pinctrl@401f8000 {
> + compatible = "fsl,imxrt1050-iomuxc";
> reg = <0x401f8000 0x4000>;
> fsl,mux_mask = <0x7>;
> };
> @@ -64,31 +48,61 @@
> reg = <0x400d8000 0x4000>;
> };
>
> - clks: ccm@400fc000 {
> + clks: clock-controller@400fc000 {
> compatible = "fsl,imxrt1050-ccm";
> reg = <0x400fc000 0x4000>;
> - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <95>, <96>;
> + clocks = <&osc>;
> + clock-names = "osc";
> #clock-cells = <1>;
> - };
> -
> - usdhc1: usdhc@402c0000 {
> - compatible = "fsl,imxrt-usdhc";
> - reg = <0x402c0000 0x10000>;
> - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clks IMXRT1050_CLK_USDHC1>;
> - clock-names = "per";
> + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
> + <&clks IMXRT1050_CLK_PLL1_BYPASS>,
> + <&clks IMXRT1050_CLK_PLL2_BYPASS>,
> + <&clks IMXRT1050_CLK_PLL3_BYPASS>,
> + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
> + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
> + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
> + <&clks IMXRT1050_CLK_PLL1_ARM>,
> + <&clks IMXRT1050_CLK_PLL2_SYS>,
> + <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
> + <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
> + <&clks IMXRT1050_CLK_PLL2_SYS>;
> + };
> +
> + edma1: dma-controller@400e8000 {
> + #dma-cells = <2>;
> + compatible = "fsl,imx7ulp-edma";
> + reg = <0x400e8000 0x4000>,
> + <0x400ec000 0x4000>;
> + dma-channels = <32>;
> + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
> + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
> + clock-names = "dma", "dmamux0";
> + clocks = <&clks IMXRT1050_CLK_DMA>,
> + <&clks IMXRT1050_CLK_DMA_MUX>;
> + };
> +
> + usdhc1: mmc@402c0000 {
> + compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
> + reg = <0x402c0000 0x4000>;
> + interrupts = <110>;
> + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
> + <&clks IMXRT1050_CLK_OSC>,
> + <&clks IMXRT1050_CLK_USDHC1>;
> + clock-names = "ipg", "ahb", "per";
> bus-width = <4>;
> + fsl,wp-controller;
> + no-1-8-v;
> + max-frequency = <4000000>;
> fsl,tuning-start-tap = <20>;
> - fsl,tuning-step= <2>;
> + fsl,tuning-step = <2>;
> status = "disabled";
> };
>
> gpio1: gpio@401b8000 {
> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> reg = <0x401b8000 0x4000>;
> - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <80>, <81>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -96,10 +110,9 @@
> };
>
> gpio2: gpio@401bc000 {
> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> reg = <0x401bc000 0x4000>;
> - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <82>, <83>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -107,10 +120,9 @@
> };
>
> gpio3: gpio@401c0000 {
> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> reg = <0x401c0000 0x4000>;
> - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <84>, <85>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -118,10 +130,9 @@
> };
>
> gpio4: gpio@401c4000 {
> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> reg = <0x401c4000 0x4000>;
> - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <86>, <87>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -129,60 +140,21 @@
> };
>
> gpio5: gpio@400c0000 {
> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> reg = <0x400c0000 0x4000>;
> - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <88>, <89>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> };
>
> - lcdif: lcdif@402b8000 {
> - compatible = "fsl,imxrt-lcdif";
> - reg = <0x402b8000 0x4000>;
> - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
> - <&clks IMXRT1050_CLK_LCDIF_APB>;
> - clock-names = "pix", "axi";
> - assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
> - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
> - status = "disabled";
> - };
> -
> - gpt1: gpt1@401ec000 {
> - compatible = "fsl,imxrt-gpt";
> + gpt: timer@401ec000 {
> + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
> reg = <0x401ec000 0x4000>;
> interrupts = <100>;
> - clocks = <&osc>;
> - status = "disabled";
> - };
> -
> - usbphy1: usbphy@400d9000 {
> - compatible = "fsl,imxrt-usbphy";
> - reg = <0x400d9000 0x1000>;
> - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> - usbmisc: usbmisc@402e0800 {
> - #index-cells = <1>;
> - compatible = "fsl,imxrt-usbmisc";
> - reg = <0x402e0800 0x200>;
> - clocks = <&clks IMXRT1050_CLK_USBOH3>;
> - };
> -
> - usbotg1: usb@402e0000 {
> - compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
> - reg = <0x402e0000 0x200>;
> - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clks IMXRT1050_CLK_USBOH3>;
> - fsl,usbphy = <&usbphy1>;
> - fsl,usbmisc = <&usbmisc 0>;
> - ahb-burst-config = <0x0>;
> - tx-burst-size-dword = <0x10>;
> - rx-burst-size-dword = <0x10>;
> - status = "disabled";
> + clocks = <&osc3M>;
> + clock-names = "per";
> };
> };
> };
> diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h
> index f74dbbcf937..93bef0832d1 100644
> --- a/include/dt-bindings/clock/imxrt1050-clock.h
> +++ b/include/dt-bindings/clock/imxrt1050-clock.h
> @@ -1,4 +1,4 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> /*
> * Copyright(C) 2019
> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> @@ -62,6 +62,11 @@
> #define IMXRT1050_CLK_PLL7_USB_HOST 53
> #define IMXRT1050_CLK_LCDIF_PIX 54
> #define IMXRT1050_CLK_USBOH3 55
> -#define IMXRT1050_CLK_END 56
> +#define IMXRT1050_CLK_IPG_PDOF 56
> +#define IMXRT1050_CLK_PER_CLK_SEL 57
> +#define IMXRT1050_CLK_PER_PDOF 58
> +#define IMXRT1050_CLK_DMA 59
> +#define IMXRT1050_CLK_DMA_MUX 60
> +#define IMXRT1050_CLK_END 61
>
> #endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/8] imxrt1050: synchronise device tree with linux
2022-08-28 6:50 ` Jesse Taube
@ 2022-10-22 12:57 ` Marcel Ziswiler
2022-10-24 1:39 ` Jesse Taube
0 siblings, 1 reply; 12+ messages in thread
From: Marcel Ziswiler @ 2022-10-22 12:57 UTC (permalink / raw)
To: u-boot, mr.bossman075; +Cc: festevam, giulio.benetti, uboot-imx, sbabic
Hi Jesse
Sorry, I kinda missed your reply and imx maintainership was quiet for quite some time. I am now preparing a v3
taking your feedback into account. Thanks!
On Sun, 2022-08-28 at 02:50 -0400, Jesse Taube wrote:
>
>
> On 8/26/22 14:31, Marcel Ziswiler wrote:
> > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> >
> > Synchronise device tree with linux v6.0-rc1.
> >
> > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> >
> > ---
> >
> > Changes in v2:
> > - imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
> >
> > arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 155 ++++++++++--
> > arch/arm/dts/imxrt1050-evk.dts | 257 +++-----------------
> > arch/arm/dts/imxrt1050-pinfunc.h | 2 +-
> > arch/arm/dts/imxrt1050.dtsi | 168 ++++++-------
> > include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
> > 5 files changed, 248 insertions(+), 343 deletions(-)
> >
> > diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> > index 617cece448a..7db53b19c2f 100644
> > --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> > +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> > @@ -4,6 +4,8 @@
> > * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> > */
> >
> > +#include <dt-bindings/memory/imxrt-sdram.h>
> > +
> #include "imxrt1050-pinfunc.h"
Okay.
> > / {
> > chosen {
> > u-boot,dm-spl;
> diff says `tick-timer = &gpt;` its important for boot
Okay.
> > @@ -15,6 +17,52 @@
> >
> > soc {
> > u-boot,dm-spl;
> > +
> > + semc@402f0000 {
> > + compatible = "fsl,imxrt-semc";
> > + clocks = <&clks IMXRT1050_CLK_SEMC>;
> > + pinctrl-0 = <&pinctrl_semc>;
> > + pinctrl-names = "default";
> > + reg = <0x402f0000 0x4000>;
> > + status = "okay";
> > + u-boot,dm-spl;
> I dont think this part under should go here tell me if im wrong. It
> should be move outside as a reference.
Not sure what you mean as this is the U-Boot specific device tree include file after all.
> > + /*
> > + * Memory configuration from sdram datasheet IS42S16160J-6BLI
> > + */
> > + fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
> > + MUX_CSX0_SDRAM_CS1
> > + 0
> > + 0
> > + 0
> > + 0>;
> > + fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
> > + BL_8
> > + COL_9BITS
> > + CL_3>;
> > + fsl,sdram-timing = /bits/ 8 <0x2
> > + 0x2
> > + 0x9
> > + 0x1
> > + 0x5
> > + 0x6
> > +
> > + 0x20
> > + 0x09
> > + 0x01
> > + 0x00
> > +
> > + 0x04
> > + 0x0A
> > + 0x21
> > + 0x50>;
> > +
> > + bank1: bank@0 {
> > + fsl,base-address = <0x80000000>;
> > + fsl,memory-size = <MEM_SIZE_32M>;
> > + u-boot,dm-spl;
> > + };
> > + };
> > };
> > };
> >
> > @@ -50,7 +98,7 @@
> > u-boot,dm-spl;
> > };
> >
> > -&gpt1 {
> > +&gpt {
> Add diff:
> clocks = <&osc>;
> compatible = "fsl,imxrt-gpt";
> status = "okay";
Okay.
> > u-boot,dm-spl;
> > };
> >
> > @@ -58,33 +106,108 @@
> > u-boot,dm-spl;
> > };
> >
> > -&semc {
> > - u-boot,dm-spl;
> > -
> > - bank1: bank@0 {
> > - u-boot,dm-spl;
> > - };
> > -};
> > -
> > &iomuxc {
> > u-boot,dm-spl;
> >
> > imxrt1050-evk {drop unneeded node ^^^
> > u-boot,dm-spl;
> > - pinctrl_lpuart1: lpuart1grp {
> > - u-boot,dm-spl;
> > - };
> >
> > pinctrl_semc: semcgrp {
> > - u-boot,dm-spl;
> > - };
> > -
> > - pinctrl_usdhc0: usdhc0grp {
> > + fsl,pins = <
> > + MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
> > + 0xf1 /* SEMC_D0 */
> > + MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
> > + 0xf1 /* SEMC_D1 */
> > + MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
> > + 0xf1 /* SEMC_D2 */
> > + MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
> > + 0xf1 /* SEMC_D3 */
> > + MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
> > + 0xf1 /* SEMC_D4 */
> > + MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
> > + 0xf1 /* SEMC_D5 */
> > + MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
> > + 0xf1 /* SEMC_D6 */
> > + MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
> > + 0xf1 /* SEMC_D7 */
> > + MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
> > + 0xf1 /* SEMC_DM0 */
> > + MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> > + 0xf1 /* SEMC_A0 */
> > + MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
> > + 0xf1 /* SEMC_A1 */
> > + MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
> > + 0xf1 /* SEMC_A2 */
> > + MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
> > + 0xf1 /* SEMC_A3 */
> > + MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
> > + 0xf1 /* SEMC_A4 */
> > + MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
> > + 0xf1 /* SEMC_A5 */
> > + MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
> > + 0xf1 /* SEMC_A6 */
> > + MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
> > + 0xf1 /* SEMC_A7 */
> > + MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
> > + 0xf1 /* SEMC_A8 */
> > + MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
> > + 0xf1 /* SEMC_A9 */
> > + MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
> > + 0xf1 /* SEMC_A11 */
> > + MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
> > + 0xf1 /* SEMC_A12 */
> > + MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
> > + 0xf1 /* SEMC_BA0 */
> > + MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
> > + 0xf1 /* SEMC_BA1 */
> > + MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
> > + 0xf1 /* SEMC_A10 */
> > + MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
> > + 0xf1 /* SEMC_CAS */
> > + MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
> > + 0xf1 /* SEMC_RAS */
> > + MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
> > + 0xf1 /* SEMC_CLK */
> > + MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
> > + 0xf1 /* SEMC_CKE */
> > + MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
> > + 0xf1 /* SEMC_WE */
> > + MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
> > + 0xf1 /* SEMC_CS0 */
> > + MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
> > + 0xf1 /* SEMC_D8 */
> > + MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
> > + 0xf1 /* SEMC_D9 */
> > + MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
> > + 0xf1 /* SEMC_D10 */
> > + MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
> > + 0xf1 /* SEMC_D11 */
> > + MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
> > + 0xf1 /* SEMC_D12 */
> > + MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
> > + 0xf1 /* SEMC_D13 */
> > + MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
> > + 0xf1 /* SEMC_D14 */
> > + MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
> > + 0xf1 /* SEMC_D15 */
> > + MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
> > + 0xf1 /* SEMC_DM1 */
> > + MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
> > + (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
> > + >;
> > u-boot,dm-spl;
> > };
> > };
> > };
> >
> > +&pinctrl_lpuart1 {
> Add diff:
> compatible = "fsl,imxrt-lpuart";
You probably meant that to go under the lpuart1 node but I got your point.
> > + u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_usdhc0 {
> Add diff:
> compatible = "fsl,imxrt-usdhc";
And this under the usdhc1 one.
> I tested this
> https://github.com/Mr-Bossman/u-boot/commit/42a7f430d761bb4d44f646a27649deda15352f2e
That commit seems totally different from any of this series. Not sure.
> Some note for future, check if the compatibles are the same they arent
> here so the soc.dtsi will be broken. Also wait a bit for other people to
> resopnd to patches before sending out v2 because no one commented on the
> other patches yet.
Sure, sure.
Cheers
Marcel
> Thanks,
> Jesse
> > + u-boot,dm-spl;
> > +};
> > +
> > &usdhc1 {
> > u-boot,dm-spl;
> > };
> > diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
> > index fb2da3adfcf..6a9c10decf5 100644
> > --- a/arch/arm/dts/imxrt1050-evk.dts
> > +++ b/arch/arm/dts/imxrt1050-evk.dts
> > @@ -1,4 +1,4 @@
> > -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > /*
> > * Copyright (C) 2019
> > * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> > @@ -6,7 +6,6 @@
> >
> > /dts-v1/;
> > #include "imxrt1050.dtsi"
> > -#include "imxrt1050-evk-u-boot.dtsi"
> > #include "imxrt1050-pinfunc.h"
> >
> > / {
> > @@ -14,210 +13,52 @@
> > compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
> >
> > chosen {
> > - bootargs = "root=/dev/ram";
> > - stdout-path = "serial0:115200n8";
> > - tick-timer = &gpt1;
> > + stdout-path = &lpuart1;
> > };
> >
> > - memory {
> > + aliases {
> > + gpio0 = &gpio1;
> > + gpio1 = &gpio2;
> > + gpio2 = &gpio3;
> > + gpio3 = &gpio4;
> > + gpio4 = &gpio5;
> > + mmc0 = &usdhc1;
> > + serial0 = &lpuart1;
> > + };
> > +
> > + memory@80000000 {
> > device_type = "memory";
> > reg = <0x80000000 0x2000000>;
> > };
> > };
> >
> > -&lpuart1 { /* console */
> > +&lpuart1 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_lpuart1>;
> > status = "okay";
> > };
> >
> > -&semc {
> > - /*
> > - * Memory configuration from sdram datasheet IS42S16160J-6BLI
> > - */
> > - fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
> > - MUX_CSX0_SDRAM_CS1
> > - 0
> > - 0
> > - 0
> > - 0>;
> > - fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
> > - BL_8
> > - COL_9BITS
> > - CL_3>;
> > - fsl,sdram-timing = /bits/ 8 <0x2
> > - 0x2
> > - 0x9
> > - 0x1
> > - 0x5
> > - 0x6
> > -
> > - 0x20
> > - 0x09
> > - 0x01
> > - 0x00
> > -
> > - 0x04
> > - 0x0A
> > - 0x21
> > - 0x50>;
> > -
> > - bank1: bank@0 {
> > - fsl,base-address = <0x80000000>;
> > - fsl,memory-size = <MEM_SIZE_32M>;
> > - };
> > -};
> > -
> > &iomuxc {
> > pinctrl-names = "default";
> > - pinctrl-0 = <&pinctrl_lpuart1>;
> > -
> > - imxrt1050-evk {
> > - pinctrl_lpuart1: lpuart1grp {
> > - fsl,pins = <
> > - MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
> > - 0xf1
> > - MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
> > - 0xf1
> > - >;
> > - };
> > -
> > - pinctrl_semc: semcgrp {
> > - fsl,pins = <
> > - MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
> > - 0xf1 /* SEMC_D0 */
> > - MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
> > - 0xf1 /* SEMC_D1 */
> > - MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
> > - 0xf1 /* SEMC_D2 */
> > - MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
> > - 0xf1 /* SEMC_D3 */
> > - MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
> > - 0xf1 /* SEMC_D4 */
> > - MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
> > - 0xf1 /* SEMC_D5 */
> > - MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
> > - 0xf1 /* SEMC_D6 */
> > - MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
> > - 0xf1 /* SEMC_D7 */
> > - MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
> > - 0xf1 /* SEMC_DM0 */
> > - MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
> > - 0xf1 /* SEMC_A0 */
> > - MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
> > - 0xf1 /* SEMC_A1 */
> > - MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
> > - 0xf1 /* SEMC_A2 */
> > - MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
> > - 0xf1 /* SEMC_A3 */
> > - MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
> > - 0xf1 /* SEMC_A4 */
> > - MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
> > - 0xf1 /* SEMC_A5 */
> > - MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
> > - 0xf1 /* SEMC_A6 */
> > - MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
> > - 0xf1 /* SEMC_A7 */
> > - MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
> > - 0xf1 /* SEMC_A8 */
> > - MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
> > - 0xf1 /* SEMC_A9 */
> > - MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
> > - 0xf1 /* SEMC_A11 */
> > - MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
> > - 0xf1 /* SEMC_A12 */
> > - MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
> > - 0xf1 /* SEMC_BA0 */
> > - MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
> > - 0xf1 /* SEMC_BA1 */
> > - MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
> > - 0xf1 /* SEMC_A10 */
> > - MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
> > - 0xf1 /* SEMC_CAS */
> > - MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
> > - 0xf1 /* SEMC_RAS */
> > - MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
> > - 0xf1 /* SEMC_CLK */
> > - MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
> > - 0xf1 /* SEMC_CKE */
> > - MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
> > - 0xf1 /* SEMC_WE */
> > - MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
> > - 0xf1 /* SEMC_CS0 */
> > - MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
> > - 0xf1 /* SEMC_D8 */
> > - MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
> > - 0xf1 /* SEMC_D9 */
> > - MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
> > - 0xf1 /* SEMC_D10 */
> > - MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
> > - 0xf1 /* SEMC_D11 */
> > - MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
> > - 0xf1 /* SEMC_D12 */
> > - MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
> > - 0xf1 /* SEMC_D13 */
> > - MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
> > - 0xf1 /* SEMC_D14 */
> > - MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
> > - 0xf1 /* SEMC_D15 */
> > - MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
> > - 0xf1 /* SEMC_DM1 */
> > - MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
> > - (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
> > - >;
> > - };
> > -
> > - pinctrl_usdhc0: usdhc0grp {
> > - fsl,pins = <
> > - MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
> > - 0x1B000
> > - MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
> > - 0xB069
> > - MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
> > - 0x17061
> > - MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
> > - 0x17061
> > - MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
> > - 0x17061
> > - MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
> > - 0x17061
> > - MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
> > - 0x17061
> > - MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
> > - 0x17061
> > - >;
> > - };
> > -
> > - pinctrl_lcdif: lcdifgrp {
> > - fsl,pins = <
> > - MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
> > - MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
> > - MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
> > - >;
> > - };
> > + pinctrl_lpuart1: lpuart1grp {
> > + fsl,pins = <
> > + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
> > + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
> > + >;
> > };
> > -};
> >
> > -&gpt1 {
> > - status = "okay";
> > + pinctrl_usdhc0: usdhc0grp {
> > + fsl,pins = <
> > + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
> > + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
> > + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
> > + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
> > + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
> > + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
> > + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
> > + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
> > + >;
> > + };
> > };
> >
> > &usdhc1 {
> > @@ -226,42 +67,6 @@
> > pinctrl-1 = <&pinctrl_usdhc0>;
> > pinctrl-2 = <&pinctrl_usdhc0>;
> > pinctrl-3 = <&pinctrl_usdhc0>;
> > - status = "okay";
> > -
> > cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
> > -};
> > -
> > -&lcdif {
> > - pinctrl-names = "default";
> > - pinctrl-0 = <&pinctrl_lcdif>;
> > - display = <&display0>;
> > - status = "okay";
> > -
> > - display0: display0 {
> > - bits-per-pixel = <16>;
> > - bus-width = <16>;
> > -
> > - display-timings {
> > - timing0: timing0 {
> > - clock-frequency = <9300000>;
> > - hactive = <480>;
> > - vactive = <272>;
> > - hback-porch = <4>;
> > - hfront-porch = <8>;
> > - vback-porch = <4>;
> > - vfront-porch = <8>;
> > - hsync-len = <41>;
> > - vsync-len = <10>;
> > - de-active = <1>;
> > - pixelclk-active = <0>;
> > - hsync-active = <0>;
> > - vsync-active = <0>;
> > - };
> > - };
> > - };
> > -};
> > -
> > -&usbotg1 {
> > - dr_mode = "host";
> > status = "okay";
> > };
> > diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h
> > index a29031ab3de..22c14a3262a 100644
> > --- a/arch/arm/dts/imxrt1050-pinfunc.h
> > +++ b/arch/arm/dts/imxrt1050-pinfunc.h
> > @@ -1,4 +1,4 @@
> > -/* SPDX-License-Identifier: GPL-2.0+ */
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > /*
> > * Copyright (C) 2019
> > * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> > diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
> > index 09f4712af68..03e6a858a7b 100644
> > --- a/arch/arm/dts/imxrt1050.dtsi
> > +++ b/arch/arm/dts/imxrt1050.dtsi
> > @@ -1,4 +1,4 @@
> > -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > /*
> > * Copyright (C) 2019
> > * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> > @@ -8,53 +8,37 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/clock/imxrt1050-clock.h>
> > #include <dt-bindings/gpio/gpio.h>
> > -#include <dt-bindings/memory/imxrt-sdram.h>
> >
> > / {
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > - aliases {
> > - display0 = &lcdif;
> > - gpio0 = &gpio1;
> > - gpio1 = &gpio2;
> > - gpio2 = &gpio3;
> > - gpio3 = &gpio4;
> > - gpio4 = &gpio5;
> > - mmc0 = &usdhc1;
> > - serial0 = &lpuart1;
> > - usbphy0 = &usbphy1;
> > - };
> > -
> > clocks {
> > osc: osc {
> > - compatible = "fsl,imx-osc", "fixed-clock";
> > + compatible = "fixed-clock";
> > #clock-cells = <0>;
> > clock-frequency = <24000000>;
> > };
> > - };
> >
> > - soc {
> > - semc: semc@402f0000 {
> > - compatible = "fsl,imxrt-semc";
> > - reg = <0x402f0000 0x4000>;
> > - clocks = <&clks IMXRT1050_CLK_SEMC>;
> > - pinctrl-0 = <&pinctrl_semc>;
> > - pinctrl-names = "default";
> > - status = "okay";
> > + osc3M: osc3M {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <3000000>;
> > };
> > + };
> >
> > + soc {
> > lpuart1: serial@40184000 {
> > - compatible = "fsl,imxrt-lpuart";
> > + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
> > reg = <0x40184000 0x4000>;
> > - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <20>;
> > clocks = <&clks IMXRT1050_CLK_LPUART1>;
> > - clock-names = "per";
> > + clock-names = "ipg";
> > status = "disabled";
> > };
> >
> > - iomuxc: iomuxc@401f8000 {
> > - compatible = "fsl,imxrt-iomuxc";
> > + iomuxc: pinctrl@401f8000 {
> > + compatible = "fsl,imxrt1050-iomuxc";
> > reg = <0x401f8000 0x4000>;
> > fsl,mux_mask = <0x7>;
> > };
> > @@ -64,31 +48,61 @@
> > reg = <0x400d8000 0x4000>;
> > };
> >
> > - clks: ccm@400fc000 {
> > + clks: clock-controller@400fc000 {
> > compatible = "fsl,imxrt1050-ccm";
> > reg = <0x400fc000 0x4000>;
> > - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <95>, <96>;
> > + clocks = <&osc>;
> > + clock-names = "osc";
> > #clock-cells = <1>;
> > - };
> > -
> > - usdhc1: usdhc@402c0000 {
> > - compatible = "fsl,imxrt-usdhc";
> > - reg = <0x402c0000 0x10000>;
> > - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clks IMXRT1050_CLK_USDHC1>;
> > - clock-names = "per";
> > + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
> > + <&clks IMXRT1050_CLK_PLL1_BYPASS>,
> > + <&clks IMXRT1050_CLK_PLL2_BYPASS>,
> > + <&clks IMXRT1050_CLK_PLL3_BYPASS>,
> > + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
> > + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
> > + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
> > + <&clks IMXRT1050_CLK_PLL1_ARM>,
> > + <&clks IMXRT1050_CLK_PLL2_SYS>,
> > + <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
> > + <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
> > + <&clks IMXRT1050_CLK_PLL2_SYS>;
> > + };
> > +
> > + edma1: dma-controller@400e8000 {
> > + #dma-cells = <2>;
> > + compatible = "fsl,imx7ulp-edma";
> > + reg = <0x400e8000 0x4000>,
> > + <0x400ec000 0x4000>;
> > + dma-channels = <32>;
> > + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
> > + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
> > + clock-names = "dma", "dmamux0";
> > + clocks = <&clks IMXRT1050_CLK_DMA>,
> > + <&clks IMXRT1050_CLK_DMA_MUX>;
> > + };
> > +
> > + usdhc1: mmc@402c0000 {
> > + compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
> > + reg = <0x402c0000 0x4000>;
> > + interrupts = <110>;
> > + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
> > + <&clks IMXRT1050_CLK_OSC>,
> > + <&clks IMXRT1050_CLK_USDHC1>;
> > + clock-names = "ipg", "ahb", "per";
> > bus-width = <4>;
> > + fsl,wp-controller;
> > + no-1-8-v;
> > + max-frequency = <4000000>;
> > fsl,tuning-start-tap = <20>;
> > - fsl,tuning-step= <2>;
> > + fsl,tuning-step = <2>;
> > status = "disabled";
> > };
> >
> > gpio1: gpio@401b8000 {
> > - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> > reg = <0x401b8000 0x4000>;
> > - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <80>, <81>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > @@ -96,10 +110,9 @@
> > };
> >
> > gpio2: gpio@401bc000 {
> > - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> > reg = <0x401bc000 0x4000>;
> > - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <82>, <83>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > @@ -107,10 +120,9 @@
> > };
> >
> > gpio3: gpio@401c0000 {
> > - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> > reg = <0x401c0000 0x4000>;
> > - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <84>, <85>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > @@ -118,10 +130,9 @@
> > };
> >
> > gpio4: gpio@401c4000 {
> > - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> > reg = <0x401c4000 0x4000>;
> > - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <86>, <87>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > @@ -129,60 +140,21 @@
> > };
> >
> > gpio5: gpio@400c0000 {
> > - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> > + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
> > reg = <0x400c0000 0x4000>;
> > - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <88>, <89>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > };
> >
> > - lcdif: lcdif@402b8000 {
> > - compatible = "fsl,imxrt-lcdif";
> > - reg = <0x402b8000 0x4000>;
> > - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
> > - <&clks IMXRT1050_CLK_LCDIF_APB>;
> > - clock-names = "pix", "axi";
> > - assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
> > - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
> > - status = "disabled";
> > - };
> > -
> > - gpt1: gpt1@401ec000 {
> > - compatible = "fsl,imxrt-gpt";
> > + gpt: timer@401ec000 {
> > + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
> > reg = <0x401ec000 0x4000>;
> > interrupts = <100>;
> > - clocks = <&osc>;
> > - status = "disabled";
> > - };
> > -
> > - usbphy1: usbphy@400d9000 {
> > - compatible = "fsl,imxrt-usbphy";
> > - reg = <0x400d9000 0x1000>;
> > - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> > - };
> > -
> > - usbmisc: usbmisc@402e0800 {
> > - #index-cells = <1>;
> > - compatible = "fsl,imxrt-usbmisc";
> > - reg = <0x402e0800 0x200>;
> > - clocks = <&clks IMXRT1050_CLK_USBOH3>;
> > - };
> > -
> > - usbotg1: usb@402e0000 {
> > - compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
> > - reg = <0x402e0000 0x200>;
> > - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clks IMXRT1050_CLK_USBOH3>;
> > - fsl,usbphy = <&usbphy1>;
> > - fsl,usbmisc = <&usbmisc 0>;
> > - ahb-burst-config = <0x0>;
> > - tx-burst-size-dword = <0x10>;
> > - rx-burst-size-dword = <0x10>;
> > - status = "disabled";
> > + clocks = <&osc3M>;
> > + clock-names = "per";
> > };
> > };
> > };
> > diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h
> > index f74dbbcf937..93bef0832d1 100644
> > --- a/include/dt-bindings/clock/imxrt1050-clock.h
> > +++ b/include/dt-bindings/clock/imxrt1050-clock.h
> > @@ -1,4 +1,4 @@
> > -/* SPDX-License-Identifier: GPL-2.0+ */
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > /*
> > * Copyright(C) 2019
> > * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
> > @@ -62,6 +62,11 @@
> > #define IMXRT1050_CLK_PLL7_USB_HOST 53
> > #define IMXRT1050_CLK_LCDIF_PIX 54
> > #define IMXRT1050_CLK_USBOH3 55
> > -#define IMXRT1050_CLK_END 56
> > +#define IMXRT1050_CLK_IPG_PDOF 56
> > +#define IMXRT1050_CLK_PER_CLK_SEL 57
> > +#define IMXRT1050_CLK_PER_PDOF 58
> > +#define IMXRT1050_CLK_DMA 59
> > +#define IMXRT1050_CLK_DMA_MUX 60
> > +#define IMXRT1050_CLK_END 61
> >
> > #endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/8] imxrt1050: synchronise device tree with linux
2022-10-22 12:57 ` Marcel Ziswiler
@ 2022-10-24 1:39 ` Jesse Taube
0 siblings, 0 replies; 12+ messages in thread
From: Jesse Taube @ 2022-10-24 1:39 UTC (permalink / raw)
To: Marcel Ziswiler, u-boot; +Cc: festevam, giulio.benetti, uboot-imx, sbabic
On 10/22/22 08:57, Marcel Ziswiler wrote:
> Hi Jesse
>
> Sorry, I kinda missed your reply and imx maintainership was quiet for quite some time. I am now preparing a v3
> taking your feedback into account. Thanks!
>
> On Sun, 2022-08-28 at 02:50 -0400, Jesse Taube wrote:
>>
>>
>> On 8/26/22 14:31, Marcel Ziswiler wrote:
>>> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>>
>>> Synchronise device tree with linux v6.0-rc1.
>>>
>>> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>>>
>>> ---
>>>
>>> Changes in v2:
>>> - imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
>>>
>>> arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 155 ++++++++++--
>>> arch/arm/dts/imxrt1050-evk.dts | 257 +++-----------------
>>> arch/arm/dts/imxrt1050-pinfunc.h | 2 +-
>>> arch/arm/dts/imxrt1050.dtsi | 168 ++++++-------
>>> include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
>>> 5 files changed, 248 insertions(+), 343 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>>> index 617cece448a..7db53b19c2f 100644
>>> --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>>> +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
>>> @@ -4,6 +4,8 @@
>>> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>>> */
>>>
>>> +#include <dt-bindings/memory/imxrt-sdram.h>
>>> +
>> #include "imxrt1050-pinfunc.h"
>
> Okay.
>
>>> / {
>>> chosen {
>>> u-boot,dm-spl;
>> diff says `tick-timer = &gpt;` its important for boot
>
> Okay.
>
>>> @@ -15,6 +17,52 @@
>>>
>>> soc {
>>> u-boot,dm-spl;
>>> +
>>> + semc@402f0000 {
>>> + compatible = "fsl,imxrt-semc";
>>> + clocks = <&clks IMXRT1050_CLK_SEMC>;
>>> + pinctrl-0 = <&pinctrl_semc>;
>>> + pinctrl-names = "default";
>>> + reg = <0x402f0000 0x4000>;
>>> + status = "okay";
>>> + u-boot,dm-spl;
>> I dont think this part under should go here tell me if im wrong. It
>> should be move outside as a reference.
>
> Not sure what you mean as this is the U-Boot specific device tree include file after all.
>
>>> + /*
>>> + * Memory configuration from sdram datasheet IS42S16160J-6BLI
>>> + */
>>> + fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
>>> + MUX_CSX0_SDRAM_CS1
>>> + 0
>>> + 0
>>> + 0
>>> + 0>;
>>> + fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
>>> + BL_8
>>> + COL_9BITS
>>> + CL_3>;
>>> + fsl,sdram-timing = /bits/ 8 <0x2
>>> + 0x2
>>> + 0x9
>>> + 0x1
>>> + 0x5
>>> + 0x6
>>> +
>>> + 0x20
>>> + 0x09
>>> + 0x01
>>> + 0x00
>>> +
>>> + 0x04
>>> + 0x0A
>>> + 0x21
>>> + 0x50>;
>>> +
>>> + bank1: bank@0 {
>>> + fsl,base-address = <0x80000000>;
>>> + fsl,memory-size = <MEM_SIZE_32M>;
>>> + u-boot,dm-spl;
>>> + };
>>> + };
>>> };
>>> };
>>>
>>> @@ -50,7 +98,7 @@
>>> u-boot,dm-spl;
>>> };
>>>
>>> -&gpt1 {
>>> +&gpt {
>> Add diff:
>> clocks = <&osc>;
>> compatible = "fsl,imxrt-gpt";
>> status = "okay";
>
> Okay.
>
>>> u-boot,dm-spl;
>>> };
>>>
>>> @@ -58,33 +106,108 @@
>>> u-boot,dm-spl;
>>> };
>>>
>>> -&semc {
>>> - u-boot,dm-spl;
>>> -
>>> - bank1: bank@0 {
>>> - u-boot,dm-spl;
>>> - };
>>> -};
>>> -
>>> &iomuxc {
>>> u-boot,dm-spl;
>>>
>>> imxrt1050-evk {drop unneeded node ^^^
>>> u-boot,dm-spl;
>>> - pinctrl_lpuart1: lpuart1grp {
>>> - u-boot,dm-spl;
>>> - };
>>>
>>> pinctrl_semc: semcgrp {
>>> - u-boot,dm-spl;
>>> - };
>>> -
>>> - pinctrl_usdhc0: usdhc0grp {
>>> + fsl,pins = <
>>> + MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
>>> + 0xf1 /* SEMC_D0 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
>>> + 0xf1 /* SEMC_D1 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
>>> + 0xf1 /* SEMC_D2 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
>>> + 0xf1 /* SEMC_D3 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
>>> + 0xf1 /* SEMC_D4 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
>>> + 0xf1 /* SEMC_D5 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
>>> + 0xf1 /* SEMC_D6 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
>>> + 0xf1 /* SEMC_D7 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
>>> + 0xf1 /* SEMC_DM0 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
>>> + 0xf1 /* SEMC_A0 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
>>> + 0xf1 /* SEMC_A1 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
>>> + 0xf1 /* SEMC_A2 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
>>> + 0xf1 /* SEMC_A3 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
>>> + 0xf1 /* SEMC_A4 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
>>> + 0xf1 /* SEMC_A5 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
>>> + 0xf1 /* SEMC_A6 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
>>> + 0xf1 /* SEMC_A7 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
>>> + 0xf1 /* SEMC_A8 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
>>> + 0xf1 /* SEMC_A9 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
>>> + 0xf1 /* SEMC_A11 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
>>> + 0xf1 /* SEMC_A12 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
>>> + 0xf1 /* SEMC_BA0 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
>>> + 0xf1 /* SEMC_BA1 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
>>> + 0xf1 /* SEMC_A10 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
>>> + 0xf1 /* SEMC_CAS */
>>> + MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
>>> + 0xf1 /* SEMC_RAS */
>>> + MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
>>> + 0xf1 /* SEMC_CLK */
>>> + MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
>>> + 0xf1 /* SEMC_CKE */
>>> + MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
>>> + 0xf1 /* SEMC_WE */
>>> + MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
>>> + 0xf1 /* SEMC_CS0 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
>>> + 0xf1 /* SEMC_D8 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
>>> + 0xf1 /* SEMC_D9 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
>>> + 0xf1 /* SEMC_D10 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
>>> + 0xf1 /* SEMC_D11 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
>>> + 0xf1 /* SEMC_D12 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
>>> + 0xf1 /* SEMC_D13 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
>>> + 0xf1 /* SEMC_D14 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
>>> + 0xf1 /* SEMC_D15 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
>>> + 0xf1 /* SEMC_DM1 */
>>> + MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
>>> + (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
>>> + >;
>>> u-boot,dm-spl;
>>> };
>>> };
>>> };
>>>
>>> +&pinctrl_lpuart1 {
>> Add diff:
>> compatible = "fsl,imxrt-lpuart";
>
> You probably meant that to go under the lpuart1 node but I got your point.
>
>>> + u-boot,dm-spl;
>>> +};
>>> +
>>> +&pinctrl_usdhc0 {
>> Add diff:
>> compatible = "fsl,imxrt-usdhc";
>
> And this under the usdhc1 one.
>
>> I tested this
>> https://github.com/Mr-Bossman/u-boot/commit/42a7f430d761bb4d44f646a27649deda15352f2e
>
> That commit seems totally different from any of this series. Not sure.
It's this patch with the changes nessasary to make it boot added on top.
Please sqash them into this patch and take notes as to the diff.
Everything that was removed by the syncing should be added into the
-u-boot.dts So pinctl for SMEC and SMEC timing need to be moved as well
as compatibles.
Thanks,
Jesse
>
>> Some note for future, check if the compatibles are the same they arent
>> here so the soc.dtsi will be broken. Also wait a bit for other people to
>> resopnd to patches before sending out v2 because no one commented on the
>> other patches yet.
>
> Sure, sure.
>
> Cheers
>
> Marcel
>
>> Thanks,
>> Jesse
>>> + u-boot,dm-spl;
>>> +};
>>> +
>>> &usdhc1 {
>>> u-boot,dm-spl;
>>> };
>>> diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
>>> index fb2da3adfcf..6a9c10decf5 100644
>>> --- a/arch/arm/dts/imxrt1050-evk.dts
>>> +++ b/arch/arm/dts/imxrt1050-evk.dts
>>> @@ -1,4 +1,4 @@
>>> -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> /*
>>> * Copyright (C) 2019
>>> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>>> @@ -6,7 +6,6 @@
>>>
>>> /dts-v1/;
>>> #include "imxrt1050.dtsi"
>>> -#include "imxrt1050-evk-u-boot.dtsi"
>>> #include "imxrt1050-pinfunc.h"
>>>
>>> / {
>>> @@ -14,210 +13,52 @@
>>> compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
>>>
>>> chosen {
>>> - bootargs = "root=/dev/ram";
>>> - stdout-path = "serial0:115200n8";
>>> - tick-timer = &gpt1;
>>> + stdout-path = &lpuart1;
>>> };
>>>
>>> - memory {
>>> + aliases {
>>> + gpio0 = &gpio1;
>>> + gpio1 = &gpio2;
>>> + gpio2 = &gpio3;
>>> + gpio3 = &gpio4;
>>> + gpio4 = &gpio5;
>>> + mmc0 = &usdhc1;
>>> + serial0 = &lpuart1;
>>> + };
>>> +
>>> + memory@80000000 {
>>> device_type = "memory";
>>> reg = <0x80000000 0x2000000>;
>>> };
>>> };
>>>
>>> -&lpuart1 { /* console */
>>> +&lpuart1 {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&pinctrl_lpuart1>;
>>> status = "okay";
>>> };
>>>
>>> -&semc {
>>> - /*
>>> - * Memory configuration from sdram datasheet IS42S16160J-6BLI
>>> - */
>>> - fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
>>> - MUX_CSX0_SDRAM_CS1
>>> - 0
>>> - 0
>>> - 0
>>> - 0>;
>>> - fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
>>> - BL_8
>>> - COL_9BITS
>>> - CL_3>;
>>> - fsl,sdram-timing = /bits/ 8 <0x2
>>> - 0x2
>>> - 0x9
>>> - 0x1
>>> - 0x5
>>> - 0x6
>>> -
>>> - 0x20
>>> - 0x09
>>> - 0x01
>>> - 0x00
>>> -
>>> - 0x04
>>> - 0x0A
>>> - 0x21
>>> - 0x50>;
>>> -
>>> - bank1: bank@0 {
>>> - fsl,base-address = <0x80000000>;
>>> - fsl,memory-size = <MEM_SIZE_32M>;
>>> - };
>>> -};
>>> -
>>> &iomuxc {
>>> pinctrl-names = "default";
>>> - pinctrl-0 = <&pinctrl_lpuart1>;
>>> -
>>> - imxrt1050-evk {
>>> - pinctrl_lpuart1: lpuart1grp {
>>> - fsl,pins = <
>>> - MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
>>> - 0xf1
>>> - MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
>>> - 0xf1
>>> - >;
>>> - };
>>> -
>>> - pinctrl_semc: semcgrp {
>>> - fsl,pins = <
>>> - MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
>>> - 0xf1 /* SEMC_D0 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
>>> - 0xf1 /* SEMC_D1 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
>>> - 0xf1 /* SEMC_D2 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
>>> - 0xf1 /* SEMC_D3 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
>>> - 0xf1 /* SEMC_D4 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
>>> - 0xf1 /* SEMC_D5 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
>>> - 0xf1 /* SEMC_D6 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
>>> - 0xf1 /* SEMC_D7 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
>>> - 0xf1 /* SEMC_DM0 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
>>> - 0xf1 /* SEMC_A0 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
>>> - 0xf1 /* SEMC_A1 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
>>> - 0xf1 /* SEMC_A2 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
>>> - 0xf1 /* SEMC_A3 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
>>> - 0xf1 /* SEMC_A4 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
>>> - 0xf1 /* SEMC_A5 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
>>> - 0xf1 /* SEMC_A6 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
>>> - 0xf1 /* SEMC_A7 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
>>> - 0xf1 /* SEMC_A8 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
>>> - 0xf1 /* SEMC_A9 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
>>> - 0xf1 /* SEMC_A11 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
>>> - 0xf1 /* SEMC_A12 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
>>> - 0xf1 /* SEMC_BA0 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
>>> - 0xf1 /* SEMC_BA1 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
>>> - 0xf1 /* SEMC_A10 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
>>> - 0xf1 /* SEMC_CAS */
>>> - MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
>>> - 0xf1 /* SEMC_RAS */
>>> - MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
>>> - 0xf1 /* SEMC_CLK */
>>> - MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
>>> - 0xf1 /* SEMC_CKE */
>>> - MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
>>> - 0xf1 /* SEMC_WE */
>>> - MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
>>> - 0xf1 /* SEMC_CS0 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
>>> - 0xf1 /* SEMC_D8 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
>>> - 0xf1 /* SEMC_D9 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
>>> - 0xf1 /* SEMC_D10 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
>>> - 0xf1 /* SEMC_D11 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
>>> - 0xf1 /* SEMC_D12 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
>>> - 0xf1 /* SEMC_D13 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
>>> - 0xf1 /* SEMC_D14 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
>>> - 0xf1 /* SEMC_D15 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
>>> - 0xf1 /* SEMC_DM1 */
>>> - MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
>>> - (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
>>> - >;
>>> - };
>>> -
>>> - pinctrl_usdhc0: usdhc0grp {
>>> - fsl,pins = <
>>> - MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
>>> - 0x1B000
>>> - MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
>>> - 0xB069
>>> - MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
>>> - 0x17061
>>> - MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
>>> - 0x17061
>>> - MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
>>> - 0x17061
>>> - MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
>>> - 0x17061
>>> - MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
>>> - 0x17061
>>> - MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
>>> - 0x17061
>>> - >;
>>> - };
>>> -
>>> - pinctrl_lcdif: lcdifgrp {
>>> - fsl,pins = <
>>> - MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
>>> - MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
>>> - MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
>>> - >;
>>> - };
>>> + pinctrl_lpuart1: lpuart1grp {
>>> + fsl,pins = <
>>> + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
>>> + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
>>> + >;
>>> };
>>> -};
>>>
>>> -&gpt1 {
>>> - status = "okay";
>>> + pinctrl_usdhc0: usdhc0grp {
>>> + fsl,pins = <
>>> + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
>>> + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
>>> + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
>>> + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
>>> + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
>>> + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
>>> + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
>>> + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
>>> + >;
>>> + };
>>> };
>>>
>>> &usdhc1 {
>>> @@ -226,42 +67,6 @@
>>> pinctrl-1 = <&pinctrl_usdhc0>;
>>> pinctrl-2 = <&pinctrl_usdhc0>;
>>> pinctrl-3 = <&pinctrl_usdhc0>;
>>> - status = "okay";
>>> -
>>> cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
>>> -};
>>> -
>>> -&lcdif {
>>> - pinctrl-names = "default";
>>> - pinctrl-0 = <&pinctrl_lcdif>;
>>> - display = <&display0>;
>>> - status = "okay";
>>> -
>>> - display0: display0 {
>>> - bits-per-pixel = <16>;
>>> - bus-width = <16>;
>>> -
>>> - display-timings {
>>> - timing0: timing0 {
>>> - clock-frequency = <9300000>;
>>> - hactive = <480>;
>>> - vactive = <272>;
>>> - hback-porch = <4>;
>>> - hfront-porch = <8>;
>>> - vback-porch = <4>;
>>> - vfront-porch = <8>;
>>> - hsync-len = <41>;
>>> - vsync-len = <10>;
>>> - de-active = <1>;
>>> - pixelclk-active = <0>;
>>> - hsync-active = <0>;
>>> - vsync-active = <0>;
>>> - };
>>> - };
>>> - };
>>> -};
>>> -
>>> -&usbotg1 {
>>> - dr_mode = "host";
>>> status = "okay";
>>> };
>>> diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h
>>> index a29031ab3de..22c14a3262a 100644
>>> --- a/arch/arm/dts/imxrt1050-pinfunc.h
>>> +++ b/arch/arm/dts/imxrt1050-pinfunc.h
>>> @@ -1,4 +1,4 @@
>>> -/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>> /*
>>> * Copyright (C) 2019
>>> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>>> diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
>>> index 09f4712af68..03e6a858a7b 100644
>>> --- a/arch/arm/dts/imxrt1050.dtsi
>>> +++ b/arch/arm/dts/imxrt1050.dtsi
>>> @@ -1,4 +1,4 @@
>>> -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> /*
>>> * Copyright (C) 2019
>>> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>>> @@ -8,53 +8,37 @@
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> #include <dt-bindings/clock/imxrt1050-clock.h>
>>> #include <dt-bindings/gpio/gpio.h>
>>> -#include <dt-bindings/memory/imxrt-sdram.h>
>>>
>>> / {
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>>
>>> - aliases {
>>> - display0 = &lcdif;
>>> - gpio0 = &gpio1;
>>> - gpio1 = &gpio2;
>>> - gpio2 = &gpio3;
>>> - gpio3 = &gpio4;
>>> - gpio4 = &gpio5;
>>> - mmc0 = &usdhc1;
>>> - serial0 = &lpuart1;
>>> - usbphy0 = &usbphy1;
>>> - };
>>> -
>>> clocks {
>>> osc: osc {
>>> - compatible = "fsl,imx-osc", "fixed-clock";
>>> + compatible = "fixed-clock";
>>> #clock-cells = <0>;
>>> clock-frequency = <24000000>;
>>> };
>>> - };
>>>
>>> - soc {
>>> - semc: semc@402f0000 {
>>> - compatible = "fsl,imxrt-semc";
>>> - reg = <0x402f0000 0x4000>;
>>> - clocks = <&clks IMXRT1050_CLK_SEMC>;
>>> - pinctrl-0 = <&pinctrl_semc>;
>>> - pinctrl-names = "default";
>>> - status = "okay";
>>> + osc3M: osc3M {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <3000000>;
>>> };
>>> + };
>>>
>>> + soc {
>>> lpuart1: serial@40184000 {
>>> - compatible = "fsl,imxrt-lpuart";
>>> + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
>>> reg = <0x40184000 0x4000>;
>>> - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupts = <20>;
>>> clocks = <&clks IMXRT1050_CLK_LPUART1>;
>>> - clock-names = "per";
>>> + clock-names = "ipg";
>>> status = "disabled";
>>> };
>>>
>>> - iomuxc: iomuxc@401f8000 {
>>> - compatible = "fsl,imxrt-iomuxc";
>>> + iomuxc: pinctrl@401f8000 {
>>> + compatible = "fsl,imxrt1050-iomuxc";
>>> reg = <0x401f8000 0x4000>;
>>> fsl,mux_mask = <0x7>;
>>> };
>>> @@ -64,31 +48,61 @@
>>> reg = <0x400d8000 0x4000>;
>>> };
>>>
>>> - clks: ccm@400fc000 {
>>> + clks: clock-controller@400fc000 {
>>> compatible = "fsl,imxrt1050-ccm";
>>> reg = <0x400fc000 0x4000>;
>>> - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
>>> - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupts = <95>, <96>;
>>> + clocks = <&osc>;
>>> + clock-names = "osc";
>>> #clock-cells = <1>;
>>> - };
>>> -
>>> - usdhc1: usdhc@402c0000 {
>>> - compatible = "fsl,imxrt-usdhc";
>>> - reg = <0x402c0000 0x10000>;
>>> - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
>>> - clocks = <&clks IMXRT1050_CLK_USDHC1>;
>>> - clock-names = "per";
>>> + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
>>> + <&clks IMXRT1050_CLK_PLL1_BYPASS>,
>>> + <&clks IMXRT1050_CLK_PLL2_BYPASS>,
>>> + <&clks IMXRT1050_CLK_PLL3_BYPASS>,
>>> + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
>>> + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
>>> + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
>>> + <&clks IMXRT1050_CLK_PLL1_ARM>,
>>> + <&clks IMXRT1050_CLK_PLL2_SYS>,
>>> + <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
>>> + <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
>>> + <&clks IMXRT1050_CLK_PLL2_SYS>;
>>> + };
>>> +
>>> + edma1: dma-controller@400e8000 {
>>> + #dma-cells = <2>;
>>> + compatible = "fsl,imx7ulp-edma";
>>> + reg = <0x400e8000 0x4000>,
>>> + <0x400ec000 0x4000>;
>>> + dma-channels = <32>;
>>> + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
>>> + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
>>> + clock-names = "dma", "dmamux0";
>>> + clocks = <&clks IMXRT1050_CLK_DMA>,
>>> + <&clks IMXRT1050_CLK_DMA_MUX>;
>>> + };
>>> +
>>> + usdhc1: mmc@402c0000 {
>>> + compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
>>> + reg = <0x402c0000 0x4000>;
>>> + interrupts = <110>;
>>> + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
>>> + <&clks IMXRT1050_CLK_OSC>,
>>> + <&clks IMXRT1050_CLK_USDHC1>;
>>> + clock-names = "ipg", "ahb", "per";
>>> bus-width = <4>;
>>> + fsl,wp-controller;
>>> + no-1-8-v;
>>> + max-frequency = <4000000>;
>>> fsl,tuning-start-tap = <20>;
>>> - fsl,tuning-step= <2>;
>>> + fsl,tuning-step = <2>;
>>> status = "disabled";
>>> };
>>>
>>> gpio1: gpio@401b8000 {
>>> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
>>> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
>>> reg = <0x401b8000 0x4000>;
>>> - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
>>> - <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupts = <80>, <81>;
>>> gpio-controller;
>>> #gpio-cells = <2>;
>>> interrupt-controller;
>>> @@ -96,10 +110,9 @@
>>> };
>>>
>>> gpio2: gpio@401bc000 {
>>> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
>>> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
>>> reg = <0x401bc000 0x4000>;
>>> - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
>>> - <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupts = <82>, <83>;
>>> gpio-controller;
>>> #gpio-cells = <2>;
>>> interrupt-controller;
>>> @@ -107,10 +120,9 @@
>>> };
>>>
>>> gpio3: gpio@401c0000 {
>>> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
>>> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
>>> reg = <0x401c0000 0x4000>;
>>> - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
>>> - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupts = <84>, <85>;
>>> gpio-controller;
>>> #gpio-cells = <2>;
>>> interrupt-controller;
>>> @@ -118,10 +130,9 @@
>>> };
>>>
>>> gpio4: gpio@401c4000 {
>>> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
>>> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
>>> reg = <0x401c4000 0x4000>;
>>> - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
>>> - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupts = <86>, <87>;
>>> gpio-controller;
>>> #gpio-cells = <2>;
>>> interrupt-controller;
>>> @@ -129,60 +140,21 @@
>>> };
>>>
>>> gpio5: gpio@400c0000 {
>>> - compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
>>> + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
>>> reg = <0x400c0000 0x4000>;
>>> - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
>>> - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupts = <88>, <89>;
>>> gpio-controller;
>>> #gpio-cells = <2>;
>>> interrupt-controller;
>>> #interrupt-cells = <2>;
>>> };
>>>
>>> - lcdif: lcdif@402b8000 {
>>> - compatible = "fsl,imxrt-lcdif";
>>> - reg = <0x402b8000 0x4000>;
>>> - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
>>> - clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
>>> - <&clks IMXRT1050_CLK_LCDIF_APB>;
>>> - clock-names = "pix", "axi";
>>> - assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
>>> - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
>>> - status = "disabled";
>>> - };
>>> -
>>> - gpt1: gpt1@401ec000 {
>>> - compatible = "fsl,imxrt-gpt";
>>> + gpt: timer@401ec000 {
>>> + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
>>> reg = <0x401ec000 0x4000>;
>>> interrupts = <100>;
>>> - clocks = <&osc>;
>>> - status = "disabled";
>>> - };
>>> -
>>> - usbphy1: usbphy@400d9000 {
>>> - compatible = "fsl,imxrt-usbphy";
>>> - reg = <0x400d9000 0x1000>;
>>> - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
>>> - };
>>> -
>>> - usbmisc: usbmisc@402e0800 {
>>> - #index-cells = <1>;
>>> - compatible = "fsl,imxrt-usbmisc";
>>> - reg = <0x402e0800 0x200>;
>>> - clocks = <&clks IMXRT1050_CLK_USBOH3>;
>>> - };
>>> -
>>> - usbotg1: usb@402e0000 {
>>> - compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
>>> - reg = <0x402e0000 0x200>;
>>> - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
>>> - clocks = <&clks IMXRT1050_CLK_USBOH3>;
>>> - fsl,usbphy = <&usbphy1>;
>>> - fsl,usbmisc = <&usbmisc 0>;
>>> - ahb-burst-config = <0x0>;
>>> - tx-burst-size-dword = <0x10>;
>>> - rx-burst-size-dword = <0x10>;
>>> - status = "disabled";
>>> + clocks = <&osc3M>;
>>> + clock-names = "per";
>>> };
>>> };
>>> };
>>> diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h
>>> index f74dbbcf937..93bef0832d1 100644
>>> --- a/include/dt-bindings/clock/imxrt1050-clock.h
>>> +++ b/include/dt-bindings/clock/imxrt1050-clock.h
>>> @@ -1,4 +1,4 @@
>>> -/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>> /*
>>> * Copyright(C) 2019
>>> * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
>>> @@ -62,6 +62,11 @@
>>> #define IMXRT1050_CLK_PLL7_USB_HOST 53
>>> #define IMXRT1050_CLK_LCDIF_PIX 54
>>> #define IMXRT1050_CLK_USBOH3 55
>>> -#define IMXRT1050_CLK_END 56
>>> +#define IMXRT1050_CLK_IPG_PDOF 56
>>> +#define IMXRT1050_CLK_PER_CLK_SEL 57
>>> +#define IMXRT1050_CLK_PER_PDOF 58
>>> +#define IMXRT1050_CLK_DMA 59
>>> +#define IMXRT1050_CLK_DMA_MUX 60
>>> +#define IMXRT1050_CLK_END 61
>>>
>>> #endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/8] imx8ulp: synchronise device tree with linux
2022-08-26 18:31 [PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1 Marcel Ziswiler
` (2 preceding siblings ...)
2022-08-26 18:31 ` [PATCH v2 3/8] imxrt1050: synchronise device tree with linux Marcel Ziswiler
@ 2022-08-26 18:31 ` Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 5/8] imx8mq: " Marcel Ziswiler
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Marcel Ziswiler @ 2022-08-26 18:31 UTC (permalink / raw)
To: u-boot
Cc: Fabio Estevam, Jesse Taube, Giulio Benetti, Marcel Ziswiler,
NXP i.MX U-Boot Team, Stefano Babic
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
Changes in v2:
- imx8ulp: Re-added s400_mu device tree node.
arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 15 +-
arch/arm/dts/imx8ulp-evk.dts | 191 +-----
arch/arm/dts/imx8ulp-pinfunc.h | 4 +-
arch/arm/dts/imx8ulp.dtsi | 564 +++++-------------
include/dt-bindings/clock/imx8ulp-clock.h | 49 +-
include/dt-bindings/power/imx8ulp-power.h | 26 +
include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++
7 files changed, 278 insertions(+), 630 deletions(-)
create mode 100644 include/dt-bindings/power/imx8ulp-power.h
create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index 7c1dab2acfc..ad264f271ec 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -3,7 +3,16 @@
* Copyright 2021 NXP
*/
-&{/soc@0} {
+/ {
+ mu@27020000 {
+ compatible = "fsl,imx8ulp-mu";
+ reg = <0 0x27020000 0 0x10000>;
+ status = "okay";
+ u-boot,dm-spl;
+ };
+};
+
+&soc {
u-boot,dm-spl;
};
@@ -23,10 +32,6 @@
u-boot,dm-spl;
};
-&s400_mu {
- u-boot,dm-spl;
-};
-
&lpuart5 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts
index da09ff48ff8..33e84c4e9ed 100644
--- a/arch/arm/dts/imx8ulp-evk.dts
+++ b/arch/arm/dts/imx8ulp-evk.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
@@ -8,17 +8,16 @@
#include "imx8ulp.dtsi"
/ {
- model = "FSL i.MX8ULP EVK";
+ model = "NXP i.MX8ULP EVK";
compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
chosen {
stdout-path = &lpuart5;
- bootargs = "console=ttyLP1,115200 earlycon";
};
- usdhc2_pwrseq: usdhc2_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>;
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
};
};
@@ -30,24 +29,25 @@
status = "okay";
};
+&usdhc0 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ non-removable;
+ bus-width = <8>;
+ status = "okay";
+};
+
&iomuxc1 {
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
- MX8ULP_PAD_PTF14__LPUART5_TX 0x03
- MX8ULP_PAD_PTF15__LPUART5_RX 0x03
- >;
- };
-
- pinctrl_lpi2c7: lpi2c7grp {
- fsl,pins = <
- MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27
- MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27
+ MX8ULP_PAD_PTF14__LPUART5_TX 0x3
+ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
- MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43
MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
MX8ULP_PAD_PTD10__SDHC0_D0 0x43
@@ -61,163 +61,4 @@
MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
>;
};
-
- pinctrl_usdhc2_pte: usdhc2ptegrp {
- fsl,pins = <
- MX8ULP_PAD_PTE1__SDHC2_D0 0x43
- MX8ULP_PAD_PTE0__SDHC2_D1 0x43
- MX8ULP_PAD_PTE5__SDHC2_D2 0x43
- MX8ULP_PAD_PTE4__SDHC2_D3 0x43
- MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042
- MX8ULP_PAD_PTE3__SDHC2_CMD 0x43
- MX8ULP_PAD_PTE7__PTE7 0x10003
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
- MX8ULP_PAD_PTE15__ENET0_MDC 0x43
- MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
- MX8ULP_PAD_PTE17__ENET0_RXER 0x43
- MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
- MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
- MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
- MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
- MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
- MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043
- MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043
- >;
- };
-
- pinctrl_usbotg0_id: otg0idgrp {
- fsl,pins = <
- MX8ULP_PAD_PTF2__USB0_ID 0x10003
- >;
- };
-
- pinctrl_usbotg1_id: otg1idgrp {
- fsl,pins = <
- MX8ULP_PAD_PTD23__USB1_ID 0x10003
- >;
- };
-};
-
-&usdhc0 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc0>;
- pinctrl-1 = <&pinctrl_usdhc0>;
- pinctrl-2 = <&pinctrl_usdhc0>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc2_pte>;
- pinctrl-1 = <&pinctrl_usdhc2_pte>;
- pinctrl-2 = <&pinctrl_usdhc2_pte>;
- pinctrl-3 = <&pinctrl_usdhc2_pte>;
- mmc-pwrseq = <&usdhc2_pwrseq>;
- max-frequency = <100000000>;
- bus-width = <4>;
- keep-power-in-suspend;
- non-removable;
- wakeup-source;
- status = "okay";
-
- wifi_wake_host {
- compatible = "nxp,wifi-wake-host";
- interrupt-parent = <&gpioe>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "host-wake";
- };
-};
-
-&lpi2c7 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpi2c7>;
- status = "okay";
-
- pcal6408: gpio@21 {
- compatible = "ti,tca6408";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&flexspi0 {
- status = "okay";
-
- flash0: atxp032@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <66000000>;
- };
-};
-
-&flexspi2 {
- status = "okay";
-
- flash1: mt35xu512aba@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- spi-nor,ddr-quad-read-dummy = <8>;
- };
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "rmii";
- phy-handle = <ðphy>;
- status = "okay";
-
- phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy: ethernet-phy@1 {
- reg = <1>;
- micrel,led-mode = <1>;
- };
- };
-};
-
-&usbotg0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg0_id>;
- srp-disable;
- hnp-disable;
- adp-disable;
- status = "okay";
-};
-
-&usbphy0 {
- fsl,tx-d-cal = <88>;
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_id>;
- srp-disable;
- hnp-disable;
- adp-disable;
- status = "okay";
-};
-
-&usbphy1 {
- fsl,tx-d-cal = <88>;
};
diff --git a/arch/arm/dts/imx8ulp-pinfunc.h b/arch/arm/dts/imx8ulp-pinfunc.h
index c21c3b644e5..b204ac79b44 100644
--- a/arch/arm/dts/imx8ulp-pinfunc.h
+++ b/arch/arm/dts/imx8ulp-pinfunc.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
- * Copyright 2020 NXP
+ * Copyright 2021 NXP
*/
#ifndef __DTS_IMX8ULP_PINFUNC_H
diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi
index d3b16bd2feb..60c1b018bf0 100644
--- a/arch/arm/dts/imx8ulp.dtsi
+++ b/arch/arm/dts/imx8ulp.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
@@ -6,6 +6,8 @@
#include <dt-bindings/clock/imx8ulp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/imx8ulp-power.h>
+
#include "imx8ulp-pinfunc.h"
/ {
@@ -17,46 +19,25 @@
gpio0 = &gpiod;
gpio1 = &gpioe;
gpio2 = &gpiof;
- serial0 = &lpuart5;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
- spi0 = &flexspi0;
- spi2 = &flexspi2;
- ethernet0 = &fec;
- i2c7 = &lpi2c7;
- usbphy0 = &usbphy0;
- usb0 = &usbotg0;
- usbphy1 = &usbphy1;
- usb1 = &usbotg1;
+ serial0 = &lpuart4;
+ serial1 = &lpuart5;
+ serial2 = &lpuart6;
+ serial3 = &lpuart7;
};
- cpus: cpus {
+ cpus {
#address-cells = <2>;
#size-cells = <0>;
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP: cpu-sleep {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010033>;
- local-timer-stop;
- entry-latency-us = <1000>;
- exit-latency-us = <700>;
- min-residency-us = <2700>;
- wakeup-latency-us = <1500>;
- };
- };
-
- /* We have 1 clusters with 4 Cortex-A35 cores */
A35_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
};
A35_1: cpu@1 {
@@ -65,7 +46,6 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
};
A35_L2: l2-cache0 {
@@ -73,37 +53,6 @@
};
};
- a35_opp_table: opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-504000000 {
- opp-hz = /bits/ 64 <504000000>;
- opp-microvolt = <800000>;
- clock-latency-ns = <150000>;
- };
-
- opp-744000000 {
- opp-hz = /bits/ 64 <744000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <150000>;
- };
-
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1000000>;
- clock-latency-ns = <150000>;
- opp-suspend;
- };
- };
-
- s400_mu: mu@27020000 {
- u-boot,dm-spl;
- compatible = "fsl,imx8ulp-mu";
- reg = <0 0x27020000 0 0x10000>;
- status = "okay";
- };
-
gic: interrupt-controller@2d400000 {
compatible = "arm,gic-v3";
reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
@@ -154,7 +103,7 @@
#clock-cells = <0>;
};
- sram@0x2201f000 {
+ sram@2201f000 {
compatible = "mmio-sram";
reg = <0x0 0x2201f000 0x0 0x1000>;
@@ -162,10 +111,9 @@
#size-cells = <1>;
ranges = <0 0x0 0x2201f000 0x1000>;
- /* TODO: split or unify */
- scmi_pd: scmi_pd@0 {
+ scmi_buf: scmi-buf@0 {
compatible = "arm,scmi-shmem";
- reg = <0x0 0x200>;
+ reg = <0x0 0x400>;
};
};
@@ -175,42 +123,25 @@
arm,smc-id = <0xc20000fe>;
#address-cells = <1>;
#size-cells = <0>;
- shmem = <&scmi_pd>;
+ shmem = <&scmi_buf>;
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
- scmi_perf: protocol@13 {
- reg = <0x13>;
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
};
};
};
- soc@0 {
+ soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x80000000>;
-
- per_bridge0: bus@28000000 {
- compatible = "simple-bus";
- reg = <0x28000000 0x800000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- flexspi0: flexspi@28039000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nxp,imx8ulp-fspi";
- reg = <0x28039000 0x10000>,
- <0x04000000 0x7ffffff>;
- reg-names = "fspi_base", "fspi_mmap";
- status = "disabled";
- };
- };
+ ranges = <0x0 0x0 0x0 0x40000000>;
per_bridge3: bus@29000000 {
compatible = "simple-bus";
@@ -219,119 +150,13 @@
#size-cells = <1>;
ranges;
- edma1: dma-controller@29010000 {
- compatible = "fsl,imx8ulp-edma";
- reg = <0x29010000 0x10000>,
- <0x29020000 0x10000>, <0x29030000 0x10000>,
- <0x29040000 0x10000>, <0x29050000 0x10000>,
- <0x29060000 0x10000>, <0x29070000 0x10000>,
- <0x29080000 0x10000>, <0x29090000 0x10000>,
- <0x290a0000 0x10000>, <0x290b0000 0x10000>,
- <0x290c0000 0x10000>, <0x290d0000 0x10000>,
- <0x290e0000 0x10000>, <0x290f0000 0x10000>,
- <0x29100000 0x10000>, <0x29110000 0x10000>,
- <0x29120000 0x10000>, <0x29130000 0x10000>,
- <0x29140000 0x10000>, <0x29150000 0x10000>,
- <0x29160000 0x10000>, <0x29170000 0x10000>,
- <0x29180000 0x10000>, <0x29190000 0x10000>,
- <0x291a0000 0x10000>, <0x291b0000 0x10000>,
- <0x291c0000 0x10000>, <0x291d0000 0x10000>,
- <0x291e0000 0x10000>, <0x291f0000 0x10000>,
- <0x29200000 0x10000>, <0x29210000 0x10000>;
- #dma-cells = <3>;
- dma-channels = <32>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx",
- "edma1-chan2-tx", "edma1-chan3-tx",
- "edma1-chan4-tx", "edma1-chan5-tx",
- "edma1-chan6-tx", "edma1-chan7-tx",
- "edma1-chan8-tx", "edma1-chan9-tx",
- "edma1-chan10-tx", "edma1-chan11-tx",
- "edma1-chan12-tx", "edma1-chan13-tx",
- "edma1-chan14-tx", "edma1-chan15-tx",
- "edma1-chan16-tx", "edma1-chan17-tx",
- "edma1-chan18-tx", "edma1-chan19-tx",
- "edma1-chan20-tx", "edma1-chan21-tx",
- "edma1-chan22-tx", "edma1-chan23-tx",
- "edma1-chan24-tx", "edma1-chan25-tx",
- "edma1-chan26-tx", "edma1-chan27-tx",
- "edma1-chan28-tx", "edma1-chan29-tx",
- "edma1-chan30-tx", "edma1-chan31-tx";
- clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>,
- <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>;
- clock-names = "edma-mp-clk",
- "edma1-chan0-clk", "edma1-chan1-clk",
- "edma1-chan2-clk", "edma1-chan3-clk",
- "edma1-chan4-clk", "edma1-chan5-clk",
- "edma1-chan6-clk", "edma1-chan7-clk",
- "edma1-chan8-clk", "edma1-chan9-clk",
- "edma1-chan10-clk", "edma1-chan11-clk",
- "edma1-chan12-clk", "edma1-chan13-clk",
- "edma1-chan14-clk", "edma1-chan15-clk",
- "edma1-chan16-clk", "edma1-chan17-clk",
- "edma1-chan18-clk", "edma1-chan19-clk",
- "edma1-chan20-clk", "edma1-chan21-clk",
- "edma1-chan22-clk", "edma1-chan23-clk",
- "edma1-chan24-clk", "edma1-chan25-clk",
- "edma1-chan26-clk", "edma1-chan27-clk",
- "edma1-chan28-clk", "edma1-chan29-clk",
- "edma1-chan30-clk", "edma1-chan31-clk";
- status = "okay";
- };
-
wdog3: watchdog@292a0000 {
compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
reg = <0x292a0000 0x10000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
- assigned-clocks-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
timeout-sec = <40>;
};
@@ -356,6 +181,33 @@
clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
<&pcc3 IMX8ULP_CLK_TPM5>;
clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ lpi2c4: i2c@29370000 {
+ compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x29370000 0x10000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
+ <&pcc3 IMX8ULP_CLK_LPI2C4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ lpi2c5: i2c@29380000 {
+ compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x29380000 0x10000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
+ <&pcc3 IMX8ULP_CLK_LPI2C5>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
};
lpuart4: serial@29390000 {
@@ -370,10 +222,41 @@
lpuart5: serial@293a0000 {
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x293a0000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
clock-names = "ipg";
status = "disabled";
};
+
+ lpspi4: spi@293b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
+ reg = <0x293b0000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
+ <&pcc3 IMX8ULP_CLK_LPSPI4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-rates = <16000000>;
+ status = "disabled";
+ };
+
+ lpspi5: spi@293c0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
+ reg = <0x293c0000 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
+ <&pcc3 IMX8ULP_CLK_LPSPI5>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-rates = <16000000>;
+ status = "disabled";
+ };
};
per_bridge4: bus@29800000 {
@@ -389,75 +272,81 @@
#clock-cells = <1>;
};
- lpi2c6: lpi2c6@29840000 {
+ lpi2c6: i2c@29840000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29840000 0x10000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
<&pcc4 IMX8ULP_CLK_LPI2C6>;
clock-names = "per", "ipg";
+ assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-rates = <48000000>;
status = "disabled";
};
- lpi2c7: lpi2c7@29850000 {
+ lpi2c7: i2c@29850000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29850000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
<&pcc4 IMX8ULP_CLK_LPI2C7>;
clock-names = "per", "ipg";
+ assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-rates = <48000000>;
status = "disabled";
};
- flexspi2: flexspi@29810000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nxp,imx8ulp-fspi";
- reg = <0x29810000 0x10000>,
- <0x60000000 0xfffffff>;
- reg-names = "fspi_base", "fspi_mmap";
+ lpuart6: serial@29860000 {
+ compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x29860000 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
+ clock-names = "ipg";
status = "disabled";
};
- flexspi2_nand: flexspi2_nand@29810000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx8-fspi-nand";
- reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
- reg-names = "FlexSPI", "FlexSPI-memory";
+ lpuart7: serial@29870000 {
+ compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x29870000 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
+ clock-names = "ipg";
status = "disabled";
};
iomuxc1: pinctrl@298c0000 {
compatible = "fsl,imx8ulp-iomuxc1";
reg = <0x298c0000 0x10000>;
- fsl,mux_mask = <0xf00>;
};
usdhc0: mmc@298d0000 {
- compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
+ compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
reg = <0x298d0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
- <&cgc1 IMX8ULP_CLK_DUMMY>,
+ clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+ <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
usdhc1: mmc@298e0000 {
- compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
+ compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
reg = <0x298e0000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
- <&cgc1 IMX8ULP_CLK_DUMMY>,
+ clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -470,117 +359,40 @@
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>;
- assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
- assigned-clock-rates = <396000000>, <396000000>;
+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
-
- usbotg0: usb@29900000 {
- compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
- "fsl,imx27-usb";
- reg = <0x29900000 0x200>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_USB0>;
- fsl,usbphy = <&usbphy0>;
- fsl,usbmisc = <&usbmisc0 0>;
- ahb-burst-config = <0x0>;
- tx-burst-size-dword = <0x8>;
- rx-burst-size-dword = <0x8>;
- status = "disabled";
- };
-
- usbmisc0: usbmisc@29900200 {
- #index-cells = <1>;
- compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
- "fsl,imx6q-usbmisc";
- reg = <0x29900200 0x200>;
- };
-
- usbphy0: usbphy@29910000 {
- compatible = "fsl,imx8ulp-usbphy",
- "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
- reg = <0x29910000 0x1000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
- };
-
- usbotg1: usb@29920000 {
- compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
- "fsl,imx27-usb";
- reg = <0x29920000 0x200>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_USB1>;
- fsl,usbphy = <&usbphy1>;
- fsl,usbmisc = <&usbmisc1 0>;
- ahb-burst-config = <0x0>;
- tx-burst-size-dword = <0x8>;
- rx-burst-size-dword = <0x8>;
- status = "disabled";
- };
-
- usbmisc1: usbmisc@29920200 {
- #index-cells = <1>;
- compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
- "fsl,imx6q-usbmisc";
- reg = <0x29920200 0x200>;
- };
-
- usbphy1: usbphy@29930000 {
- compatible = "fsl,imx8ulp-usbphy",
- "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
- reg = <0x29930000 0x1000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
- };
-
- fec: ethernet@29950000 {
- compatible = "fsl,imx8ulp-fec", "fsl,imx6sx-fec";
- reg = <0x29950000 0x10000>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_ENET>,
- <&pcc4 IMX8ULP_CLK_ENET>,
- <&cgc1 IMX8ULP_CLK_ENETSTAMP_SEL>,
- <&pcc4 IMX8ULP_CLK_ENET>,
- <&pcc4 IMX8ULP_CLK_ENET>;
- clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref", "enet_out";
- fsl,num-tx-queues = <3>;
- fsl,num-rx-queues = <3>;
- status = "disabled";
- };
-
};
- gpioe: gpio@2d000000 {
- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
- reg = <0x2d000080 0x1000 0x2d000040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
- <&pcc4 IMX8ULP_CLK_PCTLE>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 32 24>;
+ gpioe: gpio@2d000080 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
+ <&pcc4 IMX8ULP_CLK_PCTLE>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 32 24>;
};
- gpiof: gpio@2d010000 {
- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
- reg = <0x2d010080 0x1000 0x2d010040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
- <&pcc4 IMX8ULP_CLK_PCTLF>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 64 24>;
+ gpiof: gpio@2d010080 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
+ <&pcc4 IMX8ULP_CLK_PCTLF>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 64 32>;
};
per_bridge5: bus@2d800000 {
@@ -590,112 +402,6 @@
#size-cells = <1>;
ranges;
- edma2: dma-controller@2d800000 {
- compatible = "fsl,imx8ulp-edma";
- reg = <0x2d800000 0x10000>,
- <0x2d810000 0x10000>, <0x2d820000 0x10000>,
- <0x2d830000 0x10000>, <0x2d840000 0x10000>,
- <0x2d850000 0x10000>, <0x2d860000 0x10000>,
- <0x2d870000 0x10000>, <0x2d880000 0x10000>,
- <0x2d890000 0x10000>, <0x2d8a0000 0x10000>,
- <0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>,
- <0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>,
- <0x2d8f0000 0x10000>, <0x2d900000 0x10000>,
- <0x2d910000 0x10000>, <0x2d920000 0x10000>,
- <0x2d930000 0x10000>, <0x2d940000 0x10000>,
- <0x2d950000 0x10000>, <0x2d960000 0x10000>,
- <0x2d970000 0x10000>, <0x2d980000 0x10000>,
- <0x2d990000 0x10000>, <0x2d9a0000 0x10000>,
- <0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>,
- <0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>,
- <0x2d9f0000 0x10000>, <0x2da00000 0x10000>;
- #dma-cells = <3>;
- dma-channels = <32>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx",
- "edma2-chan2-tx", "edma2-chan3-tx",
- "edma2-chan4-tx", "edma2-chan5-tx",
- "edma2-chan6-tx", "edma2-chan7-tx",
- "edma2-chan8-tx", "edma2-chan9-tx",
- "edma2-chan10-tx", "edma2-chan11-tx",
- "edma2-chan12-tx", "edma2-chan13-tx",
- "edma2-chan14-tx", "edma2-chan15-tx",
- "edma2-chan16-tx", "edma2-chan17-tx",
- "edma2-chan18-tx", "edma2-chan19-tx",
- "edma2-chan20-tx", "edma2-chan21-tx",
- "edma2-chan22-tx", "edma2-chan23-tx",
- "edma2-chan24-tx", "edma2-chan25-tx",
- "edma2-chan26-tx", "edma2-chan27-tx",
- "edma2-chan28-tx", "edma2-chan29-tx",
- "edma2-chan30-tx", "edma2-chan31-tx";
- clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>,
- <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>;
- clock-names = "edma-mp-clk",
- "edma2-chan0-clk", "edma2-chan1-clk",
- "edma2-chan2-clk", "edma2-chan3-clk",
- "edma2-chan4-clk", "edma2-chan5-clk",
- "edma2-chan6-clk", "edma2-chan7-clk",
- "edma2-chan8-clk", "edma2-chan9-clk",
- "edma2-chan10-clk", "edma2-chan11-clk",
- "edma2-chan12-clk", "edma2-chan13-clk",
- "edma2-chan14-clk", "edma2-chan15-clk",
- "edma2-chan16-clk", "edma2-chan17-clk",
- "edma2-chan18-clk", "edma2-chan19-clk",
- "edma2-chan20-clk", "edma2-chan21-clk",
- "edma2-chan22-clk", "edma2-chan23-clk",
- "edma2-chan24-clk", "edma2-chan25-clk",
- "edma2-chan26-clk", "edma2-chan27-clk",
- "edma2-chan28-clk", "edma2-chan29-clk",
- "edma2-chan30-clk", "edma2-chan31-clk";
- status = "okay";
- };
-
cgc2: clock-controller@2da60000 {
compatible = "fsl,imx8ulp-cgc2";
reg = <0x2da60000 0x10000>;
@@ -711,9 +417,9 @@
};
};
- gpiod: gpio@2e200000 {
- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
- reg = <0x2e200080 0x1000 0x2e200040 0x40>;
+ gpiod: gpio@2e200080 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
index 49166a18300..827404fadf5 100644
--- a/include/dt-bindings/clock/imx8ulp-clock.h
+++ b/include/dt-bindings/clock/imx8ulp-clock.h
@@ -1,16 +1,14 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
- * Copyright 2020 NXP
+ * Copyright 2021 NXP
*/
#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
#define __DT_BINDINGS_CLOCK_IMX8ULP_H
#define IMX8ULP_CLK_DUMMY 0
-#define IMX8ULP_CLK_ROSC 1
-#define IMX8ULP_CLK_FROSC 2
-#define IMX8ULP_CLK_LPOSC 3
-#define IMX8ULP_CLK_SOSC 4
+
+/* CGC1 */
#define IMX8ULP_CLK_SPLL2 5
#define IMX8ULP_CLK_SPLL3 6
#define IMX8ULP_CLK_A35_SEL 7
@@ -57,14 +55,15 @@
#define IMX8ULP_CLK_FROSC_DIV1_GATE 48
#define IMX8ULP_CLK_FROSC_DIV2_GATE 49
#define IMX8ULP_CLK_FROSC_DIV3_GATE 50
-#define IMX8ULP_CLK_ENETSTAMP_SEL 51
-#define IMX8ULP_CLK_SAI4_SEL 52
-#define IMX8ULP_CLK_SAI5_SEL 53
-#define IMX8ULP_CLK_AUD_CLK1 54
-#define IMX8ULP_CLK_ARM 55
+#define IMX8ULP_CLK_SAI4_SEL 51
+#define IMX8ULP_CLK_SAI5_SEL 52
+#define IMX8ULP_CLK_AUD_CLK1 53
+#define IMX8ULP_CLK_ARM 54
+#define IMX8ULP_CLK_ENET_TS_SEL 55
#define IMX8ULP_CLK_CGC1_END 56
+/* CGC2 */
#define IMX8ULP_CLK_PLL4_PRE_SEL 0
#define IMX8ULP_CLK_PLL4 1
#define IMX8ULP_CLK_PLL4_VCODIV 2
@@ -110,8 +109,12 @@
#define IMX8ULP_CLK_SAI6_SEL 42
#define IMX8ULP_CLK_SAI7_SEL 43
#define IMX8ULP_CLK_SPDIF_SEL 44
+#define IMX8ULP_CLK_HIFI_SEL 45
+#define IMX8ULP_CLK_HIFI_DIVCORE 46
+#define IMX8ULP_CLK_HIFI_DIVPLAT 47
+#define IMX8ULP_CLK_DSI_PHY_REF 48
-#define IMX8ULP_CLK_CGC2_END 45
+#define IMX8ULP_CLK_CGC2_END 49
/* PCC3 */
#define IMX8ULP_CLK_WDOG3 0
@@ -160,9 +163,12 @@
#define IMX8ULP_CLK_DMA1_CH29 43
#define IMX8ULP_CLK_DMA1_CH30 44
#define IMX8ULP_CLK_DMA1_CH31 45
+#define IMX8ULP_CLK_MU3_A 46
+#define IMX8ULP_CLK_MU0_B 47
-#define IMX8ULP_CLK_PCC3_END 46
+#define IMX8ULP_CLK_PCC3_END 48
+/* PCC4 */
#define IMX8ULP_CLK_FLEXSPI2 0
#define IMX8ULP_CLK_TPM6 1
#define IMX8ULP_CLK_TPM7 2
@@ -189,24 +195,25 @@
#define IMX8ULP_CLK_PCC4_END 23
+/* PCC5 */
#define IMX8ULP_CLK_TPM8 0
#define IMX8ULP_CLK_SAI6 1
#define IMX8ULP_CLK_SAI7 2
#define IMX8ULP_CLK_SPDIF 3
-#define IMX8ULP_CLK_ISI 4
+#define IMX8ULP_CLK_ISI 4
#define IMX8ULP_CLK_CSI_REGS 5
#define IMX8ULP_CLK_PCTLD 6
-#define IMX8ULP_CLK_CSI 7
-#define IMX8ULP_CLK_DSI 8
+#define IMX8ULP_CLK_CSI 7
+#define IMX8ULP_CLK_DSI 8
#define IMX8ULP_CLK_WDOG5 9
#define IMX8ULP_CLK_EPDC 10
-#define IMX8ULP_CLK_PXP 11
+#define IMX8ULP_CLK_PXP 11
#define IMX8ULP_CLK_SFA2 12
#define IMX8ULP_CLK_GPU2D 13
#define IMX8ULP_CLK_GPU3D 14
#define IMX8ULP_CLK_DC_NANO 15
#define IMX8ULP_CLK_CSI_CLK_UI 16
-#define IMX8ULP_CLK_CSI_CLK_ESC 17
+#define IMX8ULP_CLK_CSI_CLK_ESC 17
#define IMX8ULP_CLK_RGPIOD 18
#define IMX8ULP_CLK_DMA2_MP 19
#define IMX8ULP_CLK_DMA2_CH0 20
@@ -241,7 +248,11 @@
#define IMX8ULP_CLK_DMA2_CH29 49
#define IMX8ULP_CLK_DMA2_CH30 50
#define IMX8ULP_CLK_DMA2_CH31 51
+#define IMX8ULP_CLK_MU2_B 52
+#define IMX8ULP_CLK_MU3_B 53
+#define IMX8ULP_CLK_AVD_SIM 54
+#define IMX8ULP_CLK_DSI_TX_ESC 55
-#define IMX8ULP_CLK_PCC5_END 52
+#define IMX8ULP_CLK_PCC5_END 56
#endif
diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h
new file mode 100644
index 00000000000..a556b2e96df
--- /dev/null
+++ b/include/dt-bindings/power/imx8ulp-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__
+#define __DT_BINDINGS_IMX8ULP_POWER_H__
+
+#define IMX8ULP_PD_DMA1 0
+#define IMX8ULP_PD_FLEXSPI2 1
+#define IMX8ULP_PD_USB0 2
+#define IMX8ULP_PD_USDHC0 3
+#define IMX8ULP_PD_USDHC1 4
+#define IMX8ULP_PD_USDHC2_USB1 5
+#define IMX8ULP_PD_DCNANO 6
+#define IMX8ULP_PD_EPDC 7
+#define IMX8ULP_PD_DMA2 8
+#define IMX8ULP_PD_GPU2D 9
+#define IMX8ULP_PD_GPU3D 10
+#define IMX8ULP_PD_HIFI4 11
+#define IMX8ULP_PD_ISI 12
+#define IMX8ULP_PD_MIPI_CSI 13
+#define IMX8ULP_PD_MIPI_DSI 14
+#define IMX8ULP_PD_PXP 15
+
+#endif
diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h
new file mode 100644
index 00000000000..e99a4735c3c
--- /dev/null
+++ b/include/dt-bindings/reset/imx8ulp-pcc-reset.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
+#define DT_BINDING_PCC_RESET_IMX8ULP_H
+
+/* PCC3 */
+#define PCC3_WDOG3_SWRST 0
+#define PCC3_WDOG4_SWRST 1
+#define PCC3_LPIT1_SWRST 2
+#define PCC3_TPM4_SWRST 3
+#define PCC3_TPM5_SWRST 4
+#define PCC3_FLEXIO1_SWRST 5
+#define PCC3_I3C2_SWRST 6
+#define PCC3_LPI2C4_SWRST 7
+#define PCC3_LPI2C5_SWRST 8
+#define PCC3_LPUART4_SWRST 9
+#define PCC3_LPUART5_SWRST 10
+#define PCC3_LPSPI4_SWRST 11
+#define PCC3_LPSPI5_SWRST 12
+
+/* PCC4 */
+#define PCC4_FLEXSPI2_SWRST 0
+#define PCC4_TPM6_SWRST 1
+#define PCC4_TPM7_SWRST 2
+#define PCC4_LPI2C6_SWRST 3
+#define PCC4_LPI2C7_SWRST 4
+#define PCC4_LPUART6_SWRST 5
+#define PCC4_LPUART7_SWRST 6
+#define PCC4_SAI4_SWRST 7
+#define PCC4_SAI5_SWRST 8
+#define PCC4_USDHC0_SWRST 9
+#define PCC4_USDHC1_SWRST 10
+#define PCC4_USDHC2_SWRST 11
+#define PCC4_USB0_SWRST 12
+#define PCC4_USB0_PHY_SWRST 13
+#define PCC4_USB1_SWRST 14
+#define PCC4_USB1_PHY_SWRST 15
+#define PCC4_ENET_SWRST 16
+
+/* PCC5 */
+#define PCC5_TPM8_SWRST 0
+#define PCC5_SAI6_SWRST 1
+#define PCC5_SAI7_SWRST 2
+#define PCC5_SPDIF_SWRST 3
+#define PCC5_ISI_SWRST 4
+#define PCC5_CSI_REGS_SWRST 5
+#define PCC5_CSI_SWRST 6
+#define PCC5_DSI_SWRST 7
+#define PCC5_WDOG5_SWRST 8
+#define PCC5_EPDC_SWRST 9
+#define PCC5_PXP_SWRST 10
+#define PCC5_GPU2D_SWRST 11
+#define PCC5_GPU3D_SWRST 12
+#define PCC5_DC_NANO_SWRST 13
+
+#endif /*DT_BINDING_RESET_IMX8ULP_H */
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 5/8] imx8mq: synchronise device tree with linux
2022-08-26 18:31 [PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1 Marcel Ziswiler
` (3 preceding siblings ...)
2022-08-26 18:31 ` [PATCH v2 4/8] imx8ulp: " Marcel Ziswiler
@ 2022-08-26 18:31 ` Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 6/8] imx8mp: " Marcel Ziswiler
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Marcel Ziswiler @ 2022-08-26 18:31 UTC (permalink / raw)
To: u-boot
Cc: Fabio Estevam, Jesse Taube, Giulio Benetti, Marcel Ziswiler,
NXP i.MX U-Boot Team, Stefano Babic
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
(no changes since v1)
arch/arm/dts/imx8mq-evk.dts | 43 +++++++++++++++++
arch/arm/dts/imx8mq-u-boot.dtsi | 10 ++--
arch/arm/dts/imx8mq.dtsi | 15 +++---
include/dt-bindings/reset/imx8mq-reset.h | 61 +++++++++++++-----------
4 files changed, 88 insertions(+), 41 deletions(-)
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 99fed35168e..82387b9cb80 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -71,12 +71,36 @@
linux,autosuspend-period = <125>;
};
+ audio_codec_bt_sco: audio-codec-bt-sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&audio_codec_bt_sco 1>;
+ };
+ };
+
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
@@ -386,6 +410,16 @@
status = "okay";
};
+&sai3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -548,6 +582,15 @@
>;
};
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index e8b5f83706e..e6448ab8ad3 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -10,23 +10,23 @@
};
-&{/soc@0} {
+&soc {
u-boot,dm-spl;
};
-&{/soc@0/bus@30000000} {
+&aips1 {
u-boot,dm-spl;
};
-&{/soc@0/bus@30400000} {
+&aips2 {
u-boot,dm-spl;
};
-&{/soc@0/bus@30800000} {
+&aips3 {
u-boot,dm-spl;
};
-&{/soc@0/bus@32c00000} {
+&aips4 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 49eadb081b1..e9f0cdd10ab 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -94,7 +94,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency= <133000000>;
+ clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -320,7 +320,7 @@
arm,no-tick-in-suspend;
};
- soc@0 {
+ soc: soc@0 {
compatible = "fsl,imx8mq-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -329,7 +329,7 @@
nvmem-cells = <&imx8mq_uid>;
nvmem-cell-names = "soc_unique_id";
- bus@30000000 { /* AIPS1 */
+ aips1: bus@30000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
#address-cells = <1>;
@@ -507,7 +507,7 @@
<0x00030005 0x00000053>,
<0x00030006 0x0000005f>,
<0x00030007 0x00000071>;
- #thermal-sensor-cells = <1>;
+ #thermal-sensor-cells = <1>;
};
wdog1: watchdog@30280000 {
@@ -784,7 +784,7 @@
};
};
- bus@30400000 { /* AIPS2 */
+ aips2: bus@30400000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30400000 0x400000>;
#address-cells = <1>;
@@ -844,7 +844,7 @@
};
};
- bus@30800000 { /* AIPS3 */
+ aips3: bus@30800000 { /* AIPS3 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30800000 0x400000>;
#address-cells = <1>;
@@ -1018,6 +1018,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
sec_jr1: jr@2000 {
@@ -1369,7 +1370,7 @@
};
};
- bus@32c00000 { /* AIPS4 */
+ aips4: bus@32c00000 { /* AIPS4 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
#address-cells = <1>;
diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
index 9a301082d36..705870693ec 100755
--- a/include/dt-bindings/reset/imx8mq-reset.h
+++ b/include/dt-bindings/reset/imx8mq-reset.h
@@ -28,37 +28,40 @@
#define IMX8MQ_RESET_A53_L2RESET 17
#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
#define IMX8MQ_RESET_OTG1_PHY_RESET 19
-#define IMX8MQ_RESET_OTG2_PHY_RESET 20
-#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
-#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
-#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
-#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
-#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
-#define IMX8MQ_RESET_PCIEPHY 26
-#define IMX8MQ_RESET_PCIEPHY_PERST 27
-#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
-#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
-#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */
#define IMX8MQ_RESET_DISP_RESET 31
#define IMX8MQ_RESET_GPU_RESET 32
-#define IMX8MQ_RESET_VPU_RESET 33
-#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_DDRC1_PRST 44
-#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
-#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
-#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */
+#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */
+#define IMX8MQ_RESET_SW_M4C_RST 50
+#define IMX8MQ_RESET_SW_M4P_RST 51
+#define IMX8MQ_RESET_M4_ENABLE 52
-#define IMX8MQ_RESET_NUM 50
+#define IMX8MQ_RESET_NUM 53
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 6/8] imx8mp: synchronise device tree with linux
2022-08-26 18:31 [PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1 Marcel Ziswiler
` (4 preceding siblings ...)
2022-08-26 18:31 ` [PATCH v2 5/8] imx8mq: " Marcel Ziswiler
@ 2022-08-26 18:31 ` Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 7/8] imx8mn: " Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 8/8] imx8mm: " Marcel Ziswiler
7 siblings, 0 replies; 12+ messages in thread
From: Marcel Ziswiler @ 2022-08-26 18:31 UTC (permalink / raw)
To: u-boot
Cc: Fabio Estevam, Jesse Taube, Giulio Benetti, Marcel Ziswiler,
Marek Vasut, NXP i.MX U-Boot Team, Stefano Babic, Teresa Remmet,
Tim Harvey
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
(no changes since v1)
arch/arm/dts/imx8mp-dhcom-pdk2.dts | 27 +++--
arch/arm/dts/imx8mp-dhcom-som.dtsi | 20 +---
arch/arm/dts/imx8mp-evk.dts | 126 +++++++++++---------
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 48 ++++----
arch/arm/dts/imx8mp-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mp-venice-gw74xx.dts | 116 +++++++++---------
arch/arm/dts/imx8mp-verdin.dtsi | 14 ++-
arch/arm/dts/imx8mp.dtsi | 33 ++++-
include/dt-bindings/clock/imx8mp-clock.h | 13 +-
include/dt-bindings/power/imx8mp-power.h | 15 ++-
include/dt-bindings/reset/imx8mp-reset.h | 50 ++++++++
11 files changed, 284 insertions(+), 180 deletions(-)
create mode 100644 include/dt-bindings/reset/imx8mp-reset.h
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
index e95abfb3e89..2ca2ede2e94 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -19,7 +19,6 @@
};
gpio-keys {
- #size-cells = <0>;
compatible = "gpio-keys";
button-0 {
@@ -62,7 +61,7 @@
led {
compatible = "gpio-leds";
- led-5 {
+ led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@@ -71,7 +70,7 @@
pinctrl-names = "default";
};
- led-6 {
+ led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@@ -80,7 +79,7 @@
pinctrl-names = "default";
};
- led-7 {
+ led-2 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@@ -89,7 +88,7 @@
pinctrl-names = "default";
};
- led-8 {
+ led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@@ -118,10 +117,11 @@
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
compatible = "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpio4>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ max-speed = <100>;
reg = <7>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
@@ -138,7 +138,6 @@
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
txen-skew-ps = <0>;
- max-speed = <100>;
};
};
};
@@ -150,3 +149,15 @@
&usb3_1 {
fsl,over-current-active-low;
};
+
+&iomuxc {
+ /*
+ * GPIO_A,B,C,D are connected to buttons.
+ * GPIO_E,F,H,I are connected to LEDs.
+ * GPIO_M is connected to CLKOUT2.
+ */
+ pinctrl-0 = <&pinctrl_hog_base
+ &pinctrl_dhcom_g &pinctrl_dhcom_j
+ &pinctrl_dhcom_k &pinctrl_dhcom_l
+ &pinctrl_dhcom_int>;
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index 63cc6c92c41..a616eb37800 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
*/
@@ -224,10 +224,6 @@
};
&i2c3 {
- /*
- * iMX8MP 1P33A Errata ERR007805
- * I2C is limited to 384 kHz due to SoC bug.
- */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
@@ -393,10 +389,6 @@
};
&i2c4 {
- /*
- * iMX8MP 1P33A Errata ERR007805
- * I2C is limited to 384 kHz due to SoC bug.
- */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
@@ -407,10 +399,6 @@
};
&i2c5 { /* HDMI EDID bus */
- /*
- * iMX8MP 1P33A Errata ERR007805
- * I2C is limited to 384 kHz due to SoC bug.
- */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c5>;
@@ -802,8 +790,8 @@
pinctrl_i2c5: dhcom-i2c5-grp {
fsl,pins = <
- MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x40000084
- MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x40000084
+ MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
+ MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
>;
};
@@ -830,7 +818,7 @@
pinctrl_rtc: dhcom-rtc-grp {
fsl,pins = <
/* RTC_#INT Interrupt */
- MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6
+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080
>;
};
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index 4c3ac4214a2..f6b017ab5f5 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -67,18 +67,20 @@
};
};
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <®_can1_stby>;
- status = "okay";
+&A53_0 {
+ cpu-supply = <®_arm>;
};
-&flexcan2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_can2_stby>;
- status = "disabled";/* can2 pin conflict with pdm */
+&A53_1 {
+ cpu-supply = <®_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_arm>;
};
&eqos {
@@ -197,6 +199,20 @@
};
};
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_can1_stby>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_can2_stby>;
+ status = "disabled";/* can2 pin conflict with pdm */
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -221,7 +237,7 @@
regulator-ramp-delay = <3125>;
};
- BUCK2 {
+ reg_arm: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1025000>;
@@ -395,41 +411,41 @@
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
- MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
>;
};
@@ -461,28 +477,28 @@
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins = <
- MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
- MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
+ MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
+ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>;
};
@@ -500,20 +516,20 @@
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19
+ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
>;
};
@@ -525,7 +541,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
@@ -537,7 +553,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
@@ -549,7 +565,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
index 984a6b9ded8..6aa720bafe2 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
@@ -116,48 +116,48 @@
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
- MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
+ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
>;
};
@@ -175,7 +175,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
@@ -187,7 +187,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
@@ -199,7 +199,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
};
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index adb24cccc3b..ddced009903 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -10,7 +10,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts
index 101d3114760..521215520a0 100644
--- a/arch/arm/dts/imx8mp-venice-gw74xx.dts
+++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts
@@ -622,15 +622,15 @@
pinctrl_hog: hoggrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */
- MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */
- MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */
- MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */
- MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */
- MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */
- MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */
- MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */
+ MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
+ MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
+ MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */
+ MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */
+ MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
+ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
+ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
+ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
+ MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
@@ -639,47 +639,47 @@
pinctrl_accel: accelgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159
+ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
- MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */
- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
+ MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
- MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141
- MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
+ MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
+ MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
>;
};
@@ -692,61 +692,61 @@
pinctrl_gsc: gscgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159
+ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
- MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>;
};
pinctrl_ksz: kszgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */
- MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
+ MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
>;
};
pinctrl_gpio_leds: ledgrp {
fsl,pins = <
- MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19
- MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19
+ MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
+ MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141
+ MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
>;
};
@@ -758,13 +758,13 @@
pinctrl_reg_usb2: regusb2grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141
+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
>;
};
pinctrl_reg_wifi: regwifigrp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119
+ MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
>;
};
@@ -811,7 +811,7 @@
pinctrl_uart3_gpio: uart3gpiogrp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119
+ MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
>;
};
diff --git a/arch/arm/dts/imx8mp-verdin.dtsi b/arch/arm/dts/imx8mp-verdin.dtsi
index 68100a17263..900eae8e448 100644
--- a/arch/arm/dts/imx8mp-verdin.dtsi
+++ b/arch/arm/dts/imx8mp-verdin.dtsi
@@ -49,7 +49,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
- wakeup {
+ button-wakeup {
debounce-interval = <10>;
/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
@@ -146,6 +146,14 @@
};
};
+&cpu_alert0 {
+ temperature = <95000>;
+};
+
+&cpu_crit0 {
+ temperature = <105000>;
+};
+
/* Verdin SPI_1 */
&ecspi1 {
#address-cells = <1>;
@@ -619,7 +627,7 @@
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reg = <0x4a>;
/* Verdin GPIO_2 (SODIMM 208) */
- reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "disabled";
};
};
@@ -696,7 +704,7 @@
pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
reg = <0x4a>;
/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
- reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
status = "disabled";
};
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index d9542dfff83..fe178b7d063 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -195,7 +195,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency= <133000000>;
+ clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -293,7 +293,7 @@
arm,no-tick-in-suspend;
};
- soc@0 {
+ soc: soc@0 {
compatible = "fsl,imx8mp-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -595,7 +595,7 @@
pgc_ispdwp: power-domain@18 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
- clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
};
};
};
@@ -791,6 +791,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
sec_jr1: jr@2000 {
@@ -903,7 +904,7 @@
<&clk IMX8MP_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -917,7 +918,7 @@
<&clk IMX8MP_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -931,7 +932,7 @@
<&clk IMX8MP_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -1018,6 +1019,26 @@
};
};
+ noc: interconnect@32700000 {
+ compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
+ reg = <0x32700000 0x100000>;
+ clocks = <&clk IMX8MP_CLK_NOC>;
+ #interconnect-cells = <1>;
+ operating-points-v2 = <&noc_opp_table>;
+
+ noc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200M {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+
+ opp-1000M {
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+ };
+ };
+
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index e8d68fbb6e3..9d5cc2ddde8 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -117,7 +117,6 @@
#define IMX8MP_CLK_AUDIO_AHB 108
#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
#define IMX8MP_CLK_IPG_ROOT 110
-#define IMX8MP_CLK_IPG_AUDIO_ROOT 111
#define IMX8MP_CLK_DRAM_ALT 112
#define IMX8MP_CLK_DRAM_APB 113
#define IMX8MP_CLK_VPU_G1 114
@@ -125,7 +124,6 @@
#define IMX8MP_CLK_CAN1 116
#define IMX8MP_CLK_CAN2 117
#define IMX8MP_CLK_MEMREPAIR 118
-#define IMX8MP_CLK_PCIE_PHY 119
#define IMX8MP_CLK_PCIE_AUX 120
#define IMX8MP_CLK_I2C5 121
#define IMX8MP_CLK_I2C6 122
@@ -182,8 +180,6 @@
#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
#define IMX8MP_CLK_MEDIA_LDB 174
#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
-#define IMX8MP_CLK_PCIE2_CTRL 176
-#define IMX8MP_CLK_PCIE2_PHY 177
#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
#define IMX8MP_CLK_ECSPI3 179
#define IMX8MP_CLK_PDM 180
@@ -321,8 +317,15 @@
#define IMX8MP_CLK_AUDIO_AXI 310
#define IMX8MP_CLK_HSIO_AXI 311
#define IMX8MP_CLK_MEDIA_ISP 312
+#define IMX8MP_CLK_MEDIA_DISP2_PIX 313
+#define IMX8MP_CLK_CLKOUT1_SEL 314
+#define IMX8MP_CLK_CLKOUT1_DIV 315
+#define IMX8MP_CLK_CLKOUT1 316
+#define IMX8MP_CLK_CLKOUT2_SEL 317
+#define IMX8MP_CLK_CLKOUT2_DIV 318
+#define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 313
+#define IMX8MP_CLK_END 320
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 3f72bf7818f..7789bcca322 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -38,9 +38,16 @@
#define IMX8MP_MEDIABLK_PD_ISI 3
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
-#define IMX8MP_MEDIABLK_PD_ISP2 6
-#define IMX8MP_MEDIABLK_PD_ISP1 7
-#define IMX8MP_MEDIABLK_PD_DWE 8
-#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9
+#define IMX8MP_MEDIABLK_PD_ISP 6
+#define IMX8MP_MEDIABLK_PD_DWE 7
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
+
+#define IMX8MP_HDMIBLK_PD_IRQSTEER 0
+#define IMX8MP_HDMIBLK_PD_LCDIF 1
+#define IMX8MP_HDMIBLK_PD_PAI 2
+#define IMX8MP_HDMIBLK_PD_PVI 3
+#define IMX8MP_HDMIBLK_PD_TRNG 4
+#define IMX8MP_HDMIBLK_PD_HDMI_TX 5
+#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6
#endif
diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h
new file mode 100644
index 00000000000..2e8c9104b66
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mp-reset.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef DT_BINDING_RESET_IMX8MP_H
+#define DT_BINDING_RESET_IMX8MP_H
+
+#define IMX8MP_RESET_A53_CORE_POR_RESET0 0
+#define IMX8MP_RESET_A53_CORE_POR_RESET1 1
+#define IMX8MP_RESET_A53_CORE_POR_RESET2 2
+#define IMX8MP_RESET_A53_CORE_POR_RESET3 3
+#define IMX8MP_RESET_A53_CORE_RESET0 4
+#define IMX8MP_RESET_A53_CORE_RESET1 5
+#define IMX8MP_RESET_A53_CORE_RESET2 6
+#define IMX8MP_RESET_A53_CORE_RESET3 7
+#define IMX8MP_RESET_A53_DBG_RESET0 8
+#define IMX8MP_RESET_A53_DBG_RESET1 9
+#define IMX8MP_RESET_A53_DBG_RESET2 10
+#define IMX8MP_RESET_A53_DBG_RESET3 11
+#define IMX8MP_RESET_A53_ETM_RESET0 12
+#define IMX8MP_RESET_A53_ETM_RESET1 13
+#define IMX8MP_RESET_A53_ETM_RESET2 14
+#define IMX8MP_RESET_A53_ETM_RESET3 15
+#define IMX8MP_RESET_A53_SOC_DBG_RESET 16
+#define IMX8MP_RESET_A53_L2RESET 17
+#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18
+#define IMX8MP_RESET_OTG1_PHY_RESET 19
+#define IMX8MP_RESET_OTG2_PHY_RESET 20
+#define IMX8MP_RESET_SUPERMIX_RESET 21
+#define IMX8MP_RESET_AUDIOMIX_RESET 22
+#define IMX8MP_RESET_MLMIX_RESET 23
+#define IMX8MP_RESET_PCIEPHY 24
+#define IMX8MP_RESET_PCIEPHY_PERST 25
+#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26
+#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27
+#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28
+#define IMX8MP_RESET_MEDIA_RESET 29
+#define IMX8MP_RESET_GPU2D_RESET 30
+#define IMX8MP_RESET_GPU3D_RESET 31
+#define IMX8MP_RESET_GPU_RESET 32
+#define IMX8MP_RESET_VPU_RESET 33
+#define IMX8MP_RESET_VPU_G1_RESET 34
+#define IMX8MP_RESET_VPU_G2_RESET 35
+#define IMX8MP_RESET_VPUVC8KE_RESET 36
+#define IMX8MP_RESET_NOC_RESET 37
+
+#define IMX8MP_RESET_NUM 38
+
+#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 7/8] imx8mn: synchronise device tree with linux
2022-08-26 18:31 [PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1 Marcel Ziswiler
` (5 preceding siblings ...)
2022-08-26 18:31 ` [PATCH v2 6/8] imx8mp: " Marcel Ziswiler
@ 2022-08-26 18:31 ` Marcel Ziswiler
2022-08-26 18:31 ` [PATCH v2 8/8] imx8mm: " Marcel Ziswiler
7 siblings, 0 replies; 12+ messages in thread
From: Marcel Ziswiler @ 2022-08-26 18:31 UTC (permalink / raw)
To: u-boot
Cc: Fabio Estevam, Jesse Taube, Giulio Benetti, Marcel Ziswiler,
Ariel D'Alessandro, Michael Trimarchi, NXP i.MX U-Boot Team,
Stefano Babic, Tim Harvey
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
(no changes since v1)
arch/arm/dts/imx8mn-beacon-baseboard.dtsi | 4 +-
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 2 +-
.../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 2 +-
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mn-evk.dtsi | 45 ++++++++++++++++++-
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mn-var-som-symphony.dts | 6 +--
arch/arm/dts/imx8mn-venice-gw7902.dts | 8 ++--
arch/arm/dts/imx8mn-venice-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mn.dtsi | 13 +++---
include/dt-bindings/interconnect/imx8mn.h | 41 +++++++++++++++++
11 files changed, 106 insertions(+), 21 deletions(-)
create mode 100644 include/dt-bindings/interconnect/imx8mn.h
diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
index 02f37dcda7e..9e82069c941 100644
--- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
@@ -146,7 +146,7 @@
};
&easrc {
- fsl,asrc-rate = <48000>;
+ fsl,asrc-rate = <48000>;
status = "okay";
};
@@ -182,7 +182,7 @@
&usbotg1 {
vbus-supply = <®_usb_otg_vbus>;
disable-over-current;
- dr_mode="otg";
+ dr_mode = "otg";
status = "okay";
};
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 5f839524028..6d8ba4c39af 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -15,7 +15,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index c4ae7ca4f31..8312b64bcc0 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -16,7 +16,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 78773c198e4..edd9b959d09 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -21,7 +21,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi
index d1f6cccfa00..261c3654007 100644
--- a/arch/arm/dts/imx8mn-evk.dtsi
+++ b/arch/arm/dts/imx8mn-evk.dtsi
@@ -47,6 +47,11 @@
linux,autosuspend-period = <125>;
};
+ audio_codec_bt_sco: audio-codec-bt-sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
@@ -57,6 +62,25 @@
clock-names = "mclk";
};
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&audio_codec_bt_sco 1>;
+ };
+ };
+
sound-wm8524 {
compatible = "fsl,imx-audio-wm8524";
model = "wm8524-audio";
@@ -78,7 +102,7 @@
};
&easrc {
- fsl,asrc-rate = <48000>;
+ fsl,asrc-rate = <48000>;
status = "okay";
};
@@ -183,6 +207,16 @@
};
};
+&sai2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -354,6 +388,15 @@
>;
};
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
+ MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
+ >;
+ };
+
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index ed1ab10ded3..28fcb10e595 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -15,7 +15,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts b/arch/arm/dts/imx8mn-var-som-symphony.dts
index f61c48776cf..3ed7021a487 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
@@ -26,19 +26,19 @@
gpio-keys {
compatible = "gpio-keys";
- back {
+ key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
- home {
+ key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
- menu {
+ key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts
index 367a232675a..636f8602b97 100644
--- a/arch/arm/dts/imx8mn-venice-gw7902.dts
+++ b/arch/arm/dts/imx8mn-venice-gw7902.dts
@@ -39,13 +39,13 @@
gpio-keys {
compatible = "gpio-keys";
- user-pb {
+ key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
- user-pb1x {
+ key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@@ -59,14 +59,14 @@
interrupts = <1>;
};
- eeprom-wp {
+ key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
- tamper {
+ key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index 9fb38714523..1f4993cb670 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -15,7 +15,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
index e41e1d56f98..0c71b740a31 100644
--- a/arch/arm/dts/imx8mn.dtsi
+++ b/arch/arm/dts/imx8mn.dtsi
@@ -212,7 +212,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency= <133000000>;
+ clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -269,7 +269,7 @@
arm,no-tick-in-suspend;
};
- soc@0 {
+ soc: soc@0 {
compatible = "fsl,imx8mn-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -422,7 +422,7 @@
"ctx2_rx", "ctx2_tx",
"ctx3_rx", "ctx3_tx";
firmware-name = "imx/easrc/easrc-imx8mn.bin";
- fsl,asrc-rate = <8000>;
+ fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
status = "disabled";
};
@@ -857,6 +857,7 @@
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
sec_jr1: jr@2000 {
@@ -941,7 +942,7 @@
<&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -955,7 +956,7 @@
<&clk IMX8MN_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -969,7 +970,7 @@
<&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h
new file mode 100644
index 00000000000..307b977100b
--- /dev/null
+++ b/include/dt-bindings/interconnect/imx8mn.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Interconnect framework driver for i.MX SoC
+ *
+ * Copyright (c) 2019-2020, NXP
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H
+#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H
+
+#define IMX8MN_ICN_NOC 1
+#define IMX8MN_ICS_DRAM 2
+#define IMX8MN_ICS_OCRAM 3
+#define IMX8MN_ICM_A53 4
+
+#define IMX8MN_ICM_GPU 5
+#define IMX8MN_ICN_GPU 6
+
+#define IMX8MN_ICM_CSI1 7
+#define IMX8MN_ICM_CSI2 8
+#define IMX8MN_ICM_ISI 9
+#define IMX8MN_ICM_LCDIF 10
+#define IMX8MN_ICN_MIPI 11
+
+#define IMX8MN_ICM_USB 12
+
+#define IMX8MN_ICM_SDMA2 13
+#define IMX8MN_ICM_SDMA3 14
+#define IMX8MN_ICN_AUDIO 15
+
+#define IMX8MN_ICN_ENET 16
+#define IMX8MN_ICM_ENET 17
+
+#define IMX8MN_ICM_NAND 18
+#define IMX8MN_ICM_SDMA1 19
+#define IMX8MN_ICM_USDHC1 20
+#define IMX8MN_ICM_USDHC2 21
+#define IMX8MN_ICM_USDHC3 22
+#define IMX8MN_ICN_MAIN 23
+
+#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 8/8] imx8mm: synchronise device tree with linux
2022-08-26 18:31 [PATCH v2 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1 Marcel Ziswiler
` (6 preceding siblings ...)
2022-08-26 18:31 ` [PATCH v2 7/8] imx8mn: " Marcel Ziswiler
@ 2022-08-26 18:31 ` Marcel Ziswiler
7 siblings, 0 replies; 12+ messages in thread
From: Marcel Ziswiler @ 2022-08-26 18:31 UTC (permalink / raw)
To: u-boot
Cc: Fabio Estevam, Jesse Taube, Giulio Benetti, Marcel Ziswiler,
NXP i.MX U-Boot Team, Stefano Babic, Tim Harvey
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
(no changes since v1)
arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 4 +-
arch/arm/dts/imx8mm-evk.dtsi | 43 +++++++++++++++++++
arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 12 +++---
arch/arm/dts/imx8mm-mx8menlo.dts | 4 +-
arch/arm/dts/imx8mm-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mm-venice-gw700x.dtsi | 24 +++++------
arch/arm/dts/imx8mm-venice-gw7901.dts | 8 ++--
arch/arm/dts/imx8mm-venice-gw7902.dts | 10 ++---
arch/arm/dts/imx8mm-venice-gw7903.dts | 6 +--
arch/arm/dts/imx8mm-verdin.dtsi | 10 ++++-
include/dt-bindings/interconnect/imx8mm.h | 50 +++++++++++++++++++++++
11 files changed, 137 insertions(+), 36 deletions(-)
create mode 100644 include/dt-bindings/interconnect/imx8mm.h
diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
index f338a886d81..03266bd90a0 100644
--- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
@@ -285,14 +285,14 @@
&usbotg1 {
vbus-supply = <®_usbotg1>;
disable-over-current;
- dr_mode="otg";
+ dr_mode = "otg";
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
disable-over-current;
- dr_mode="host";
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index c42b966f7a6..7d6317d95b1 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -75,6 +75,11 @@
linux,autosuspend-period = <125>;
};
+ audio_codec_bt_sco: audio-codec-bt-sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
@@ -83,6 +88,25 @@
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
};
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&audio_codec_bt_sco 1>;
+ };
+ };
+
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
@@ -346,6 +370,16 @@
status = "okay";
};
+&sai2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -494,6 +528,15 @@
>;
};
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
+ >;
+ };
+
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
index b40148d728e..9e6170d9394 100644
--- a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
+++ b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
@@ -84,42 +84,42 @@
};
reg_buck1: buck1 {
- regulator-min-microvolt = <400000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck2: buck2 {
- regulator-min-microvolt = <400000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck3: buck3 {
- regulator-min-microvolt = <400000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck4: buck4 {
- regulator-min-microvolt = <400000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck5: buck5 {
- regulator-min-microvolt = <400000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck6: buck6 {
- regulator-min-microvolt = <400000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
diff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-mx8menlo.dts
index 92eaf4ef456..c97f4e06ae5 100644
--- a/arch/arm/dts/imx8mm-mx8menlo.dts
+++ b/arch/arm/dts/imx8mm-mx8menlo.dts
@@ -20,13 +20,13 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- user1 {
+ led-1 {
label = "TestLed601";
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
- user2 {
+ led-2 {
label = "TestLed602";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index f792b421e89..05fd3e6aac1 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -9,7 +9,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
index 00f86cada30..66a0d103c90 100644
--- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
@@ -16,13 +16,13 @@
gpio-keys {
compatible = "gpio-keys";
- user-pb {
+ key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
- user-pb1x {
+ key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@@ -36,14 +36,14 @@
interrupts = <1>;
};
- eeprom-wp {
+ key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
- tamper {
+ key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
@@ -286,8 +286,8 @@
regulator-name = "buck1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
- regulator-min-microamp = <3800000>;
- regulator-max-microamp = <6800000>;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
regulator-boot-on;
regulator-always-on;
};
@@ -297,8 +297,8 @@
regulator-name = "buck2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
- regulator-min-microamp = <2200000>;
- regulator-max-microamp = <5200000>;
+ regulator-min-microamp = <2200000>;
+ regulator-max-microamp = <5200000>;
regulator-boot-on;
regulator-always-on;
};
@@ -308,8 +308,8 @@
regulator-name = "buck3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
- regulator-min-microamp = <3800000>;
- regulator-max-microamp = <6800000>;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
regulator-always-on;
};
@@ -318,8 +318,8 @@
regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-min-microamp = <2200000>;
- regulator-max-microamp = <5200000>;
+ regulator-min-microamp = <2200000>;
+ regulator-max-microamp = <5200000>;
regulator-boot-on;
regulator-always-on;
};
diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts
index 24737e89038..35fb929e7bc 100644
--- a/arch/arm/dts/imx8mm-venice-gw7901.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7901.dts
@@ -38,13 +38,13 @@
gpio-keys {
compatible = "gpio-keys";
- user-pb {
+ key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
- user-pb1x {
+ key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@@ -58,14 +58,14 @@
interrupts = <1>;
};
- eeprom-wp {
+ key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
- tamper {
+ key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts
index 407ab4592b4..6dc5eda2d25 100644
--- a/arch/arm/dts/imx8mm-venice-gw7902.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7902.dts
@@ -42,13 +42,13 @@
gpio-keys {
compatible = "gpio-keys";
- user-pb {
+ key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
- user-pb1x {
+ key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@@ -62,14 +62,14 @@
interrupts = <1>;
};
- eeprom-wp {
+ key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
- tamper {
+ key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
@@ -651,7 +651,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts
index a7dae9bd4c1..a65761a53f2 100644
--- a/arch/arm/dts/imx8mm-venice-gw7903.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7903.dts
@@ -33,13 +33,13 @@
gpio-keys {
compatible = "gpio-keys";
- user-pb {
+ key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
- user-pb1x {
+ key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
@@ -53,7 +53,7 @@
interrupts = <1>;
};
- eeprom-wp {
+ key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
diff --git a/arch/arm/dts/imx8mm-verdin.dtsi b/arch/arm/dts/imx8mm-verdin.dtsi
index eafa88d980b..d1b4582f44c 100644
--- a/arch/arm/dts/imx8mm-verdin.dtsi
+++ b/arch/arm/dts/imx8mm-verdin.dtsi
@@ -43,7 +43,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
- wakeup {
+ key-wakeup {
debounce-interval = <10>;
/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
@@ -154,6 +154,14 @@
cpu-supply = <®_vdd_arm>;
};
+&cpu_alert0 {
+ temperature = <95000>;
+};
+
+&cpu_crit0 {
+ temperature = <105000>;
+};
+
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h
new file mode 100644
index 00000000000..8f10bb06cb5
--- /dev/null
+++ b/include/dt-bindings/interconnect/imx8mm.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Interconnect framework driver for i.MX SoC
+ *
+ * Copyright (c) 2019, BayLibre
+ * Copyright (c) 2019-2020, NXP
+ * Author: Alexandre Bailon <abailon@baylibre.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H
+#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H
+
+#define IMX8MM_ICN_NOC 1
+#define IMX8MM_ICS_DRAM 2
+#define IMX8MM_ICS_OCRAM 3
+#define IMX8MM_ICM_A53 4
+
+#define IMX8MM_ICM_VPU_H1 5
+#define IMX8MM_ICM_VPU_G1 6
+#define IMX8MM_ICM_VPU_G2 7
+#define IMX8MM_ICN_VIDEO 8
+
+#define IMX8MM_ICM_GPU2D 9
+#define IMX8MM_ICM_GPU3D 10
+#define IMX8MM_ICN_GPU 11
+
+#define IMX8MM_ICM_CSI 12
+#define IMX8MM_ICM_LCDIF 13
+#define IMX8MM_ICN_MIPI 14
+
+#define IMX8MM_ICM_USB1 15
+#define IMX8MM_ICM_USB2 16
+#define IMX8MM_ICM_PCIE 17
+#define IMX8MM_ICN_HSIO 18
+
+#define IMX8MM_ICM_SDMA2 19
+#define IMX8MM_ICM_SDMA3 20
+#define IMX8MM_ICN_AUDIO 21
+
+#define IMX8MM_ICN_ENET 22
+#define IMX8MM_ICM_ENET 23
+
+#define IMX8MM_ICN_MAIN 24
+#define IMX8MM_ICM_NAND 25
+#define IMX8MM_ICM_SDMA1 26
+#define IMX8MM_ICM_USDHC1 27
+#define IMX8MM_ICM_USDHC2 28
+#define IMX8MM_ICM_USDHC3 29
+
+#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread