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* [PATCH] arch: arm : mach-socfpga: Add mailbox command for HPS execution stage notification
@ 2022-08-30 14:25 Jit Loon Lim
  0 siblings, 0 replies; 3+ messages in thread
From: Jit Loon Lim @ 2022-08-30 14:25 UTC (permalink / raw)
  To: u-boot
  Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
	Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
	Hazim, Sieu Mun Tang, Jit Loon Lim, Chin Liang See

From: Chin Liang See <chin.liang.see@intel.com>

Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device
Manager (SDM) on the stage of HPS code execution. In general, there
are three main code execution stages: First Stage Boot Loader (FSBL)
which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot,
and the Operating System which is Linux

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++
 arch/arm/mach-socfpga/mailbox_s10.c              | 6 ++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index fbaf11597e..87af6f1cfe 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define MBOX_QSPI_CLOSE		51
 #define MBOX_QSPI_DIRECT	59
 #define MBOX_REBOOT_HPS		71
+#define MBOX_HPS_STAGE_NOTIFY		93
 
 /* Mailbox registers */
 #define MBOX_CIN			0	/* command valid offset */
@@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
 #define RCF_PIN_STATUS_NSTATUS				BIT(31)
 
+/* Defines for HPS_STAGE_NOTIFY */
+#define HPS_EXECUTION_STATE_FSBL	0
+#define HPS_EXECUTION_STATE_SSBL	1
+#define HPS_EXECUTION_STATE_OS	2
+
 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
 		  u32 *resp_buf_len, u32 *resp_buf);
 int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
@@ -182,6 +188,7 @@ int mbox_qspi_open(void);
 #endif
 
 int mbox_reset_cold(void);
+int mbox_hps_stage_notify(u32 execution_stage);
 int mbox_get_fpga_config_status(u32 cmd);
 int mbox_get_fpga_config_status_psci(u32 cmd);
 #endif /* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 101af23855..e86d9bf214 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
 					  urgent, resp_buf_len, resp_buf);
 }
 
+int mbox_hps_stage_notify(u32 execution_stage)
+{
+	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY,
+			     MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL);
+}
+
 int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
 {
 	return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* RE: [PATCH] arch: arm: mach-socfpga: Add mailbox command for HPS execution stage notification
  2022-08-30 17:15 [PATCH] arch: arm: " Jit Loon Lim
@ 2022-09-09  4:02 ` Chee, Tien Fong
  0 siblings, 0 replies; 3+ messages in thread
From: Chee, Tien Fong @ 2022-09-09  4:02 UTC (permalink / raw)
  To: Lim, Jit Loon, u-boot
  Cc: Jagan Teki, Vignesh R, Vasut, Marek, Simon, Hea, Kok Kiang, Lim,
	Elly Siew Chin, Kho, Sin Hui, Lokanathan, Raaj, Maniyam, Dinesh,
	Ng, Boon Khai, Yuslaimi, Alif Zakuan, Chong, Teik Heng, Zamri,
	Muhammad Hazim Izzat, Tang, Sieu Mun, Chin Liang See

> -----Original Message-----
> From: Lim, Jit Loon <jit.loon.lim@intel.com>
> Sent: Wednesday, 31 August, 2022 1:16 AM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki <jagan@amarulasolutions.com>; Vignesh R <vigneshr@ti.com>;
> Vasut, Marek <marex@denx.de>; Simon <simon.k.r.goldschmidt@gmail.com>;
> Chee, Tien Fong <tien.fong.chee@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>; Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>;
> Kho, Sin Hui <sin.hui.kho@intel.com>; Lokanathan, Raaj
> <raaj.lokanathan@intel.com>; Maniyam, Dinesh <dinesh.maniyam@intel.com>;
> Ng, Boon Khai <boon.khai.ng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Chong, Teik Heng
> <teik.heng.chong@intel.com>; Zamri, Muhammad Hazim Izzat
> <muhammad.hazim.izzat.zamri@intel.com>; Tang, Sieu Mun
> <sieu.mun.tang@intel.com>; Lim, Jit Loon <jit.loon.lim@intel.com>; Chin Liang
> See <chin.liang.see@intel.com>
> Subject: [PATCH] arch: arm: mach-socfpga: Add mailbox command for HPS
> execution stage notification
> 
> From: Chin Liang See <chin.liang.see@intel.com>
> 
> Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device
> Manager (SDM) on the stage of HPS code execution. In general, there are three
> main code execution stages: First Stage Boot Loader (FSBL) which is U-Boot SPL,
> Second Stage Boot Loader (SSBL) which is U-Boot, and the Operating System
> which is Linux
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++
>  arch/arm/mach-socfpga/mailbox_s10.c              | 6 ++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> index fbaf11597e..87af6f1cfe 100644
> --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
> @@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
>  #define MBOX_QSPI_CLOSE		51
>  #define MBOX_QSPI_DIRECT	59
>  #define MBOX_REBOOT_HPS		71
> +#define MBOX_HPS_STAGE_NOTIFY		93
> 
>  /* Mailbox registers */
>  #define MBOX_CIN			0	/* command valid offset */
> @@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE {
>  #define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
>  #define RCF_PIN_STATUS_NSTATUS				BIT(31)
> 
> +/* Defines for HPS_STAGE_NOTIFY */
> +#define HPS_EXECUTION_STATE_FSBL	0
> +#define HPS_EXECUTION_STATE_SSBL	1
> +#define HPS_EXECUTION_STATE_OS	2
> +
>  int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
>  		  u32 *resp_buf_len, u32 *resp_buf);
>  int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@
> -182,6 +188,7 @@ int mbox_qspi_open(void);  #endif
> 
>  int mbox_reset_cold(void);
> +int mbox_hps_stage_notify(u32 execution_stage);
>  int mbox_get_fpga_config_status(u32 cmd);  int
> mbox_get_fpga_config_status_psci(u32 cmd);  #endif /* _MAILBOX_S10_H_ */
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-
> socfpga/mailbox_s10.c
> index 101af23855..e86d9bf214 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8
> is_indirect, u32 len,
>  					  urgent, resp_buf_len, resp_buf);  }
> 
> +int mbox_hps_stage_notify(u32 execution_stage) {
> +	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY,
> +			     MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0,
> NULL); }
> +
>  int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)  {
>  	return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
> --
> 2.26.2

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards
Tien Fong


^ permalink raw reply	[flat|nested] 3+ messages in thread
* [PATCH] arch: arm: mach-socfpga: Add mailbox command for HPS execution stage notification
@ 2022-08-30 17:15 Jit Loon Lim
  2022-09-09  4:02 ` Chee, Tien Fong
  0 siblings, 1 reply; 3+ messages in thread
From: Jit Loon Lim @ 2022-08-30 17:15 UTC (permalink / raw)
  To: u-boot
  Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
	Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
	Hazim, Sieu Mun Tang, Jit Loon Lim, Chin Liang See

From: Chin Liang See <chin.liang.see@intel.com>

Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device
Manager (SDM) on the stage of HPS code execution. In general, there
are three main code execution stages: First Stage Boot Loader (FSBL)
which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot,
and the Operating System which is Linux

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++
 arch/arm/mach-socfpga/mailbox_s10.c              | 6 ++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index fbaf11597e..87af6f1cfe 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define MBOX_QSPI_CLOSE		51
 #define MBOX_QSPI_DIRECT	59
 #define MBOX_REBOOT_HPS		71
+#define MBOX_HPS_STAGE_NOTIFY		93
 
 /* Mailbox registers */
 #define MBOX_CIN			0	/* command valid offset */
@@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
 #define RCF_PIN_STATUS_NSTATUS				BIT(31)
 
+/* Defines for HPS_STAGE_NOTIFY */
+#define HPS_EXECUTION_STATE_FSBL	0
+#define HPS_EXECUTION_STATE_SSBL	1
+#define HPS_EXECUTION_STATE_OS	2
+
 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
 		  u32 *resp_buf_len, u32 *resp_buf);
 int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
@@ -182,6 +188,7 @@ int mbox_qspi_open(void);
 #endif
 
 int mbox_reset_cold(void);
+int mbox_hps_stage_notify(u32 execution_stage);
 int mbox_get_fpga_config_status(u32 cmd);
 int mbox_get_fpga_config_status_psci(u32 cmd);
 #endif /* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 101af23855..e86d9bf214 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
 					  urgent, resp_buf_len, resp_buf);
 }
 
+int mbox_hps_stage_notify(u32 execution_stage)
+{
+	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY,
+			     MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL);
+}
+
 int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
 {
 	return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-09-09  4:03 UTC | newest]

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2022-08-30 14:25 [PATCH] arch: arm : mach-socfpga: Add mailbox command for HPS execution stage notification Jit Loon Lim
2022-08-30 17:15 [PATCH] arch: arm: " Jit Loon Lim
2022-09-09  4:02 ` Chee, Tien Fong

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