[PATCH 0/3] *** SUBJECT HERE ***

[PATCH 0/3] *** SUBJECT HERE ***

[Jit Loon Lim]

*** BLURB HERE ***

Chee Hong Ang (3):
  arch: arm: mach-socfpga: Add a backup copy of .data section for SoC64
    SPL
  configs: socfpga: Specify new linker script specific to SoC64 SPL
  arch: arm: mach-socfpga: Reload SoC64 SPL state after warm reset

 arch/arm/mach-socfpga/lowlevel_init_soc64.S | 37 ++++++++
 arch/arm/mach-socfpga/u-boot-spl-soc64.lds  | 93 +++++++++++++++++++++
 configs/socfpga_agilex_defconfig            |  1 +
 configs/socfpga_stratix10_defconfig         |  1 +
 4 files changed, 132 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds

-- 
2.26.2

[PATCH 1/3] arch: arm: mach-socfpga: Add a backup copy of .data section for SoC64 SPL

[Jit Loon Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Add a new .data section for preserving the original state of the
.data section of SoC64 SPL. This new .data section is required to
make SPL reentrant after warm reset.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 93 ++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds

diff --git a/arch/arm/mach-socfpga/u-boot-spl-soc64.lds b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds
new file mode 100644
index 0000000000..05c441c088
--- /dev/null
+++ b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2018
+ * Intel Corporation <www.intel.com>
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+	.text : {
+		. = ALIGN(8);
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	} >.sram
+
+	.rodata : {
+		. = ALIGN(8);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} >.sram
+
+	.data : {
+		. = ALIGN(8);
+		/* Run time .data section starting at this location */
+		__data_start = .;
+		*(.data*)
+		/* Run time .data section ending at this location */
+		__data_end = .;
+	} >.sram
+
+	. = ALIGN(8);
+	/* Preserve original .data section starting at this location */
+	__preserve_data_start = .;
+	. = __preserve_data_start + (__data_end - __data_start);
+	/* Preserve original .data section ending at this location */
+	__preserve_data_end = .;
+
+	. = ALIGN(8);
+	.u_boot_list . : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} >.sram
+
+	.image_copy_end : {
+		. = ALIGN(8);
+		*(.__image_copy_end)
+	} >.sram
+
+	.end : {
+		. = ALIGN(8);
+		*(.__end)
+	} >.sram
+
+	_image_binary_end = .;
+
+	.bss_start (NOLOAD) : {
+		. = ALIGN(8);
+		KEEP(*(.__bss_start));
+	} >.sdram
+
+	.bss (NOLOAD) : {
+		*(.bss*)
+		 . = ALIGN(8);
+	} >.sdram
+
+	.bss_end (NOLOAD) : {
+		KEEP(*(.__bss_end));
+	} >.sdram
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
-- 
2.26.2

[PATCH 2/3] configs: socfpga: Specify new linker script specific to SoC64 SPL

[Jit Loon Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Specify new linker script for SoC64 SPL to ensure SPL is reentrant
after warm reset.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 configs/socfpga_agilex_defconfig    | 1 +
 configs/socfpga_stratix10_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index e2d869610c..59dcb8da8f 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_COUNTER_FREQUENCY=400000000
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_TEXT_BASE=0x1000
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 07e9f20a41..98d01f1428 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_COUNTER_FREQUENCY=400000000
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_TEXT_BASE=0x1000
-- 
2.26.2

[PATCH 3/3] arch: arm: mach-socfpga: Reload SoC64 SPL state after warm reset

[Jit Loon Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

When the system boot from cold reset, SPL will copy its .data section
into this backup section to keep an original copy of .data section.
When the system has been warm reset, SPL will reload the original .data
section from this backup section to restore the original state of SPL.
This is required to make sure SPL still run in fresh state after
warm reset.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 arch/arm/mach-socfpga/lowlevel_init_soc64.S | 37 +++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
index 875927cc4d..07adf62ea8 100644
--- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S
+++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
@@ -71,6 +71,43 @@ lowlevel_in_el1:
 #endif /* CONFIG_ARMV8_MULTIENTRY */
 
 2:
+
+#ifdef CONFIG_SPL_BUILD
+	branch_if_slave x0, 3f
+
+	/* Check rstmgr.stat for warm reset status */
+	ldr	x1, =SOCFPGA_RSTMGR_ADDRESS
+	ldr	x0, [x1]
+	/* Check whether any L4 watchdogs or MPUs had triggered warm reset */
+	ldr	x2, =0x000F0F00
+	ands	x0, x0, x2
+	/*
+	 * If current Reset Manager's status is warm reset just reload the
+	 * .data section by copying the data from data preserve section.
+	 * Otherwise, copy the .data section to the data preserve section to
+	 * keep an original copy of .data section. This ensure SPL is
+	 * reentrant after warm reset.
+	 */
+	b.ne	reload_data_section
+	/* Copy from .data to preserved .data to backup the SPL state */
+	ldr	x0, =__data_start
+	ldr	x1, =__preserve_data_start
+	ldr	x2, =__preserve_data_end
+	b	copy_loop
+reload_data_section:
+	/* Copy from preserved .data to .data to restore the SPL state */
+	ldr	x0, =__preserve_data_start
+	ldr	x1, =__data_start
+	ldr	x2, =__data_end
+copy_loop:
+	ldr	w3, [x0]
+	add	x0, x0, #4
+	str	w3, [x1]
+	add	x1, x1, #4
+	cmp	x1, x2
+	b.ne	copy_loop
+3:
+#endif
 	mov	lr, x29			/* Restore LR */
 	ret
 ENDPROC(lowlevel_init)
-- 
2.26.2