From: Nikita Shubin <nikita.shubin@maquefel.me>
To: u-boot@lists.denx.de
Cc: linux@yadro.com, Sean Anderson <seanga2@gmail.com>,
Rick Chen <rickchen36@gmail.com>,
Nikita Shubin <n.shubin@yadro.com>,
Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
Simon Glass <sjg@chromium.org>, Bin Meng <bmeng.cn@gmail.com>,
Ilias Apalodimas <ilias.apalodimas@linaro.org>,
Heinrich Schuchardt <xypron.glpk@gmx.de>
Subject: [PATCH v3] spl: introduce SPL_XIP to config
Date: Fri, 2 Sep 2022 11:47:39 +0300 [thread overview]
Message-ID: <20220902084739.23813-1-nikita.shubin@maquefel.me> (raw)
In-Reply-To: <CAN5B=e+ZCUFMDyPBqvZ_stVSfzG7DiHYkmCXZysrhuJdNmzTEQ@mail.gmail.com>
From: Nikita Shubin <n.shubin@yadro.com>
U-Boot and SPL don't necessary share the same location, so we might end
with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory.
In case of non XIP boot mode, we rely on such variables as "hart_lottery"
and "available_harts_lock" which we use as atomics.
The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL,
so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes.
This adds an option special for SPL to behave it in XIP manner and we don't
use hart_lottery and available_harts_lock, during start proccess.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
---
v2->v3:
Rick Chen:
- move SPL_XIP to arch/riscv/Kconfig right after XIP
- change ae350_spl defconfig's to use SPL_XIP instead of XIP
---
arch/riscv/Kconfig | 7 +++++++
arch/riscv/cpu/cpu.c | 2 +-
arch/riscv/cpu/start.S | 4 ++--
arch/riscv/include/asm/global_data.h | 2 +-
arch/riscv/lib/asm-offsets.c | 2 +-
arch/riscv/lib/smp.c | 2 +-
configs/ae350_rv32_spl_xip_defconfig | 2 +-
configs/ae350_rv64_spl_xip_defconfig | 2 +-
8 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 78e964db12..c042506a64 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -269,6 +269,13 @@ config XIP
from a NOR flash memory without copying the code to ram.
Say yes here if U-Boot boots from flash directly.
+config SPL_XIP
+ bool "Enable XIP mode for SPL"
+ help
+ If SPL starts in read-only memory (XIP for example) then we shouldn't
+ rely on lock variables (for example hart_lottery and available_harts_lock),
+ this affects only SPL, other stages should proceed as non-XIP.
+
config SHOW_REGS
bool "Show registers on unhandled exception"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 3ffcbbd23f..0f323b26b3 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -19,7 +19,7 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
u32 hart_lottery __section(".data") = 0;
/*
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index b7f21ab63e..de9d078da1 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -122,7 +122,7 @@ call_board_init_f_0:
call_harts_early_init:
jal harts_early_init
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
@@ -152,7 +152,7 @@ call_harts_early_init:
/* save the boot hart id to global_data */
SREG tp, GD_BOOT_HART(gp)
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
la t0, available_harts_lock
amoswap.w.rl zero, zero, 0(t0)
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 095484a635..b3c79e1760 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,7 @@ struct arch_global_data {
#if CONFIG_IS_ENABLED(SMP)
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
ulong available_harts;
#endif
};
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f1fe089b3d..c4f48c8373 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -16,7 +16,7 @@ int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
#endif
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index ba992100ad..f8b756291f 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -45,7 +45,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
continue;
}
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index c7b6ea4730..67c1e35c55 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -11,7 +11,7 @@ CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
-CONFIG_XIP=y
+CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index a197c97736..baee9bfe4a 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -12,7 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
-CONFIG_XIP=y
+CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70
--
2.35.1
next prev parent reply other threads:[~2022-09-02 8:47 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-11 9:37 [RFC PATCH 0/1] spl: introduce SPL_XIP to config Nikita Shubin
2022-08-11 9:37 ` [RFC PATCH 1/1] " Nikita Shubin
2022-08-13 4:35 ` Sean Anderson
2022-08-15 7:27 ` Nikita Shubin
2022-08-23 4:25 ` Sean Anderson
2022-08-26 8:44 ` [PATCH] " Nikita Shubin
2022-08-26 14:10 ` Sean Anderson
2022-08-31 7:25 ` [PATCH v2] " Nikita Shubin
[not found] ` <HK0PR03MB2994C85219E6217F7F9F4A05C17A9@HK0PR03MB2994.apcprd03.prod.outlook.com>
2022-09-02 7:25 ` Rick Chen
2022-09-02 8:42 ` Nikita Shubin
2022-09-02 8:47 ` Nikita Shubin [this message]
[not found] ` <HK0PR03MB29942A55774ED60C5568E72CC17F9@HK0PR03MB2994.apcprd03.prod.outlook.com>
2022-09-08 0:45 ` [PATCH v3] " Rick Chen
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