* [PATCH v2 0/5] Add ethernet driver for StarFive JH7110 SoC
@ 2023-03-29 10:27 Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy Yanhong Wang
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Yanhong Wang @ 2023-03-29 10:27 UTC (permalink / raw)
To: u-boot, Rick Chen, Leo, Joe Hershberger, Ramon Fried; +Cc: Yanhong Wang
This series adds ethernet support for the StarFive JH7110 RISC-V SoC.
The series includes PHY and MAC drivers. The PHY model is
YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20
(from Synopsys DesignWare).
The implementation of the phy driver is ported from linux, but it
has been adjusted for the u-boot framework.
The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A
and 1.3B boards and works normally.
For more information and support,you can visit RVspace wiki[1].
This patchset should be applied after the patchset [2].
[1] https://wiki.rvspace.org/
[2] https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yanhong.wang@starfivetech.com/
v2:
- Reworded the phy driver. Added platform private data struct to save the
configuration data read from dts.
- Reworded the MAC driver. Added platform private data struct to save the
configuration data read from dts.
Previous versions:
v1 - https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yanhong.wang@starfivetech.com/
Yanhong Wang (5):
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
net: dwc_eth_qos: Add StarFive ethernet driver glue layer
riscv: dts: jh7110: Add ethernet device tree nodes
riscv: dts: starfive: Add phy clock delay configuration for StarFive
VisionFive2 board
configs: starfive: Enable ethernet configuration for StarFive
VisionFive 2
.../jh7110-starfive-visionfive-2-v1.2a.dts | 13 +
.../jh7110-starfive-visionfive-2-v1.3b.dts | 27 ++
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 ++
arch/riscv/dts/jh7110.dtsi | 69 +++
configs/starfive_visionfive2_12a_defconfig | 12 +-
configs/starfive_visionfive2_13b_defconfig | 12 +-
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 ++++++++++
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 450 ++++++++++++++++++
drivers/net/phy/phy.c | 4 +-
include/phy.h | 1 +
16 files changed, 890 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
create mode 100644 drivers/net/phy/motorcomm.c
base-commit: d7c2e87a0b8025314ae7dd62a8add292b7524e0b
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
2023-03-29 10:27 [PATCH v2 0/5] Add ethernet driver for StarFive JH7110 SoC Yanhong Wang
@ 2023-03-29 10:27 ` Yanhong Wang
2023-04-02 7:36 ` Ramon Fried
2023-03-29 10:27 ` [PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer Yanhong Wang
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Yanhong Wang @ 2023-03-29 10:27 UTC (permalink / raw)
To: u-boot, Rick Chen, Leo, Joe Hershberger, Ramon Fried; +Cc: Yanhong Wang
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
verified the driver on StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 450 ++++++++++++++++++++++++++++++++++++
drivers/net/phy/phy.c | 4 +-
include/phy.h | 1 +
5 files changed, 461 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/phy/motorcomm.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 5eaff053a0..aba718566a 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -212,6 +212,12 @@ config PHY_MICREL_KSZ8XXX
endif # PHY_MICREL
+config PHY_MOTORCOMM
+ tristate "Motorcomm PHYs"
+ help
+ Enables support for Motorcomm network PHYs.
+ Currently supports the YT8531 Gigabit Ethernet PHYs.
+
config PHY_MSCC
bool "Microsemi Corp Ethernet PHYs support"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index d38e99e717..e9523fed2e 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MARVELL) += marvell.o
obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
+obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
new file mode 100644
index 0000000000..6e37700adc
--- /dev/null
+++ b/drivers/net/phy/motorcomm.c
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Motorcomm 8531 PHY driver.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <phy.h>
+#include <linux/bitfield.h>
+
+#define PHY_ID_YT8531 0x4f51e91b
+#define PHY_ID_MASK GENMASK(31, 0)
+
+/* Extended Register's Address Offset Register */
+#define YTPHY_PAGE_SELECT 0x1E
+
+/* Extended Register's Data Register */
+#define YTPHY_PAGE_DATA 0x1F
+
+#define YTPHY_SYNCE_CFG_REG 0xA012
+
+#define YTPHY_DTS_OUTPUT_CLK_DIS 0
+#define YTPHY_DTS_OUTPUT_CLK_25M 25000000
+#define YTPHY_DTS_OUTPUT_CLK_125M 125000000
+
+#define YT8531_SCR_SYNCE_ENABLE BIT(6)
+/* 1b0 output 25m clock *default*
+ * 1b1 output 125m clock
+ */
+#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4)
+#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1)
+#define YT8531_SCR_CLK_SRC_PLL_125M 0
+#define YT8531_SCR_CLK_SRC_UTP_RX 1
+#define YT8531_SCR_CLK_SRC_SDS_RX 2
+#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3
+#define YT8531_SCR_CLK_SRC_REF_25M 4
+#define YT8531_SCR_CLK_SRC_SSC_25M 5
+
+/* 1b0 use original tx_clk_rgmii *default*
+ * 1b1 use inverted tx_clk_rgmii.
+ */
+#define YT8531_RC1R_TX_CLK_SEL_INVERTED BIT(14)
+#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10)
+#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4)
+#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0)
+#define YT8531_RC1R_RGMII_0_000_NS 0
+#define YT8531_RC1R_RGMII_0_150_NS 1
+#define YT8531_RC1R_RGMII_0_300_NS 2
+#define YT8531_RC1R_RGMII_0_450_NS 3
+#define YT8531_RC1R_RGMII_0_600_NS 4
+#define YT8531_RC1R_RGMII_0_750_NS 5
+#define YT8531_RC1R_RGMII_0_900_NS 6
+#define YT8531_RC1R_RGMII_1_050_NS 7
+#define YT8531_RC1R_RGMII_1_200_NS 8
+#define YT8531_RC1R_RGMII_1_350_NS 9
+#define YT8531_RC1R_RGMII_1_500_NS 10
+#define YT8531_RC1R_RGMII_1_650_NS 11
+#define YT8531_RC1R_RGMII_1_800_NS 12
+#define YT8531_RC1R_RGMII_1_950_NS 13
+#define YT8531_RC1R_RGMII_2_100_NS 14
+#define YT8531_RC1R_RGMII_2_250_NS 15
+
+/* Phy gmii clock gating Register */
+#define YT8531_CLOCK_GATING_REG 0xC
+#define YT8531_CGR_RX_CLK_EN BIT(12)
+
+/* Specific Status Register */
+#define YTPHY_SPECIFIC_STATUS_REG 0x11
+#define YTPHY_DUPLEX_MASK BIT(13)
+#define YTPHY_DUPLEX_SHIFT 13
+#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14)
+#define YTPHY_SPEED_MODE_SHIFT 14
+
+#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27
+#define YT8531_ESC1R_SLEEP_SW BIT(15)
+#define YT8531_ESC1R_PLLON_SLP BIT(14)
+
+#define YT8531_RGMII_CONFIG1_REG 0xA003
+
+#define YT8531_CHIP_CONFIG_REG 0xA001
+#define YT8531_CCR_SW_RST BIT(15)
+/* 1b0 disable 1.9ns rxc clock delay *default*
+ * 1b1 enable 1.9ns rxc clock delay
+ */
+#define YT8531_CCR_RXC_DLY_EN BIT(8)
+#define YT8531_CCR_RXC_DLY_1_900_NS 1900
+
+/* bits in struct ytphy_plat_priv->flag */
+#define TX_CLK_ADJ_ENABLED BIT(0)
+#define AUTO_SLEEP_DISABLED BIT(1)
+#define KEEP_PLL_ENABLED BIT(2)
+#define TX_CLK_10_INVERTED BIT(3)
+#define TX_CLK_100_INVERTED BIT(4)
+#define TX_CLK_1000_INVERTED BIT(5)
+
+struct ytphy_plat_priv {
+ u32 rx_delay_ps;
+ u32 tx_delay_ps;
+ u32 clk_out_frequency;
+ u32 flag;
+};
+
+/**
+ * struct ytphy_cfg_reg_map - map a config value to a register value
+ * @cfg: value in device configuration
+ * @reg: value in the register
+ */
+struct ytphy_cfg_reg_map {
+ u32 cfg;
+ u32 reg;
+};
+
+static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = {
+ /* for tx delay / rx delay with YT8531_CCR_RXC_DLY_EN is not set. */
+ { 0, YT8531_RC1R_RGMII_0_000_NS },
+ { 150, YT8531_RC1R_RGMII_0_150_NS },
+ { 300, YT8531_RC1R_RGMII_0_300_NS },
+ { 450, YT8531_RC1R_RGMII_0_450_NS },
+ { 600, YT8531_RC1R_RGMII_0_600_NS },
+ { 750, YT8531_RC1R_RGMII_0_750_NS },
+ { 900, YT8531_RC1R_RGMII_0_900_NS },
+ { 1050, YT8531_RC1R_RGMII_1_050_NS },
+ { 1200, YT8531_RC1R_RGMII_1_200_NS },
+ { 1350, YT8531_RC1R_RGMII_1_350_NS },
+ { 1500, YT8531_RC1R_RGMII_1_500_NS },
+ { 1650, YT8531_RC1R_RGMII_1_650_NS },
+ { 1800, YT8531_RC1R_RGMII_1_800_NS },
+ { 1950, YT8531_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */
+ { 2100, YT8531_RC1R_RGMII_2_100_NS },
+ { 2250, YT8531_RC1R_RGMII_2_250_NS },
+
+ /* only for rx delay with YT8531_CCR_RXC_DLY_EN is set. */
+ { 0 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_000_NS },
+ { 150 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_150_NS },
+ { 300 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_300_NS },
+ { 450 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_450_NS },
+ { 600 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_600_NS },
+ { 750 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_750_NS },
+ { 900 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_900_NS },
+ { 1050 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_050_NS },
+ { 1200 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_200_NS },
+ { 1350 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_350_NS },
+ { 1500 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_500_NS },
+ { 1650 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_650_NS },
+ { 1800 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_800_NS },
+ { 1950 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_950_NS },
+ { 2100 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_2_100_NS },
+ { 2250 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_2_250_NS }
+};
+
+static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
+ u32 val,
+ u16 *rxc_dly_en)
+{
+ int tb_size = ARRAY_SIZE(ytphy_rgmii_delays);
+ int tb_size_half = tb_size / 2;
+ int i;
+
+ /* when rxc_dly_en is NULL, it is get the delay for tx, only half of
+ * tb_size is valid.
+ */
+ if (!rxc_dly_en)
+ tb_size = tb_size_half;
+
+ for (i = 0; i < tb_size; i++) {
+ if (ytphy_rgmii_delays[i].cfg == val) {
+ if (rxc_dly_en && i < tb_size_half)
+ *rxc_dly_en = 0;
+ return ytphy_rgmii_delays[i].reg;
+ }
+ }
+
+ pr_warn("Unsupported value %d, using default (%u)\n",
+ val, YT8531_RC1R_RGMII_1_950_NS);
+
+ /* when rxc_dly_en is not NULL, it is get the delay for rx.
+ * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps,
+ * so YT8531_CCR_RXC_DLY_EN should not be set.
+ */
+ if (rxc_dly_en)
+ *rxc_dly_en = 0;
+
+ return YT8531_RC1R_RGMII_1_950_NS;
+}
+
+static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
+ u16 set)
+{
+ int ret;
+
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_SELECT, regnum);
+ if (ret < 0)
+ return ret;
+
+ return phy_modify(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_DATA, mask, set);
+}
+
+static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
+{
+ struct ytphy_plat_priv *priv = phydev->priv;
+ u16 rxc_dly_en = YT8531_CCR_RXC_DLY_EN;
+ u32 rx_reg, tx_reg;
+ u16 mask, val = 0;
+ int ret;
+
+ rx_reg = ytphy_get_delay_reg_value(phydev, priv->rx_delay_ps,
+ &rxc_dly_en);
+ tx_reg = ytphy_get_delay_reg_value(phydev, priv->tx_delay_ps,
+ NULL);
+
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ rxc_dly_en = 0;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ rxc_dly_en = 0;
+ val |= FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg) |
+ FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
+ break;
+ default: /* do not support other modes */
+ return -EOPNOTSUPP;
+ }
+
+ ret = ytphy_modify_ext(phydev, YT8531_CHIP_CONFIG_REG,
+ YT8531_CCR_RXC_DLY_EN, rxc_dly_en);
+ if (ret < 0)
+ return ret;
+
+ /* Generally, it is not necessary to adjust YT8531_RC1R_FE_TX_DELAY */
+ mask = YT8531_RC1R_RX_DELAY_MASK | YT8531_RC1R_GE_TX_DELAY_MASK;
+ return ytphy_modify_ext(phydev, YT8531_RGMII_CONFIG1_REG, mask, val);
+}
+
+static int yt8531_parse_status(struct phy_device *phydev)
+{
+ int val;
+ int speed, speed_mode;
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, YTPHY_SPECIFIC_STATUS_REG);
+ if (val < 0)
+ return val;
+
+ speed_mode = (val & YTPHY_SPEED_MODE_MASK) >> YTPHY_SPEED_MODE_SHIFT;
+ switch (speed_mode) {
+ case 2:
+ speed = SPEED_1000;
+ break;
+ case 1:
+ speed = SPEED_100;
+ break;
+ default:
+ speed = SPEED_10;
+ break;
+ }
+
+ phydev->speed = speed;
+ phydev->duplex = (val & YTPHY_DUPLEX_MASK) >> YTPHY_DUPLEX_SHIFT;
+
+ return 0;
+}
+
+static int yt8531_startup(struct phy_device *phydev)
+{
+ struct ytphy_plat_priv *priv = phydev->priv;
+ u16 val = 0;
+ int ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ ret = yt8531_parse_status(phydev);
+ if (ret)
+ return ret;
+
+ if (phydev->speed < 0)
+ return -EINVAL;
+
+ if (!(priv->flag & TX_CLK_ADJ_ENABLED))
+ return 0;
+
+ switch (phydev->speed) {
+ case SPEED_1000:
+ if (priv->flag & TX_CLK_1000_INVERTED)
+ val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
+ break;
+ case SPEED_100:
+ if (priv->flag & TX_CLK_100_INVERTED)
+ val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
+ break;
+ case SPEED_10:
+ if (priv->flag & TX_CLK_10_INVERTED)
+ val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
+ break;
+ default:
+ printf("UNKNOWN SPEED\n");
+ return -EINVAL;
+ }
+
+ ret = ytphy_modify_ext(phydev, YT8531_RGMII_CONFIG1_REG,
+ YT8531_RC1R_TX_CLK_SEL_INVERTED, val);
+ if (ret < 0)
+ pr_warn("Modify TX_CLK_SEL err:%d\n", ret);
+
+ return 0;
+}
+
+static void ytphy_dt_parse(struct phy_device *phydev)
+{
+ struct ytphy_plat_priv *priv = phydev->priv;
+ int ret;
+
+ ret = ofnode_read_u32(phydev->node, "motorcomm,clk-out-frequency-hz",
+ &priv->clk_out_frequency);
+ if (ret < 0)
+ priv->clk_out_frequency = YTPHY_DTS_OUTPUT_CLK_DIS;
+
+ ret = ofnode_read_u32(phydev->node, "rx-internal-delay-ps",
+ &priv->rx_delay_ps);
+ if (ret < 0)
+ priv->rx_delay_ps = YT8531_RC1R_RGMII_1_950_NS;
+
+ ret = ofnode_read_u32(phydev->node, "tx-internal-delay-ps",
+ &priv->tx_delay_ps);
+ if (ret < 0)
+ priv->tx_delay_ps = YT8531_RC1R_RGMII_1_950_NS;
+
+ if (ofnode_read_bool(phydev->node, "motorcomm,auto-sleep-disabled"))
+ priv->flag |= AUTO_SLEEP_DISABLED;
+
+ if (ofnode_read_bool(phydev->node, "motorcomm,keep-pll-enabled"))
+ priv->flag |= KEEP_PLL_ENABLED;
+
+ if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-adj-enabled"))
+ priv->flag |= TX_CLK_ADJ_ENABLED;
+
+ if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-10-inverted"))
+ priv->flag |= TX_CLK_10_INVERTED;
+
+ if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-100-inverted"))
+ priv->flag |= TX_CLK_100_INVERTED;
+
+ if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-1000-inverted"))
+ priv->flag |= TX_CLK_1000_INVERTED;
+}
+
+static int yt8531_config(struct phy_device *phydev)
+{
+ struct ytphy_plat_priv *priv = phydev->priv;
+ u16 mask, val;
+ int ret;
+
+ ret = genphy_config_aneg(phydev);
+ if (ret < 0)
+ return ret;
+
+ ytphy_dt_parse(phydev);
+ switch (priv->clk_out_frequency) {
+ case YTPHY_DTS_OUTPUT_CLK_DIS:
+ mask = YT8531_SCR_SYNCE_ENABLE;
+ val = 0;
+ break;
+ case YTPHY_DTS_OUTPUT_CLK_25M:
+ mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
+ YT8531_SCR_CLK_FRE_SEL_125M;
+ val = YT8531_SCR_SYNCE_ENABLE |
+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
+ YT8531_SCR_CLK_SRC_REF_25M);
+ break;
+ case YTPHY_DTS_OUTPUT_CLK_125M:
+ mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
+ YT8531_SCR_CLK_FRE_SEL_125M;
+ val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M |
+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
+ YT8531_SCR_CLK_SRC_PLL_125M);
+ break;
+ default:
+ pr_warn("Freq err:%u\n", priv->clk_out_frequency);
+ return -EINVAL;
+ }
+
+ ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask,
+ val);
+ if (ret < 0)
+ return ret;
+
+ ret = ytphy_rgmii_clk_delay_config(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (priv->flag & AUTO_SLEEP_DISABLED) {
+ /* disable auto sleep */
+ ret = ytphy_modify_ext(phydev,
+ YT8531_EXTREG_SLEEP_CONTROL1_REG,
+ YT8531_ESC1R_SLEEP_SW, 0);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (priv->flag & KEEP_PLL_ENABLED) {
+ /* enable RXC clock when no wire plug */
+ ret = ytphy_modify_ext(phydev,
+ YT8531_CLOCK_GATING_REG,
+ YT8531_CGR_RX_CLK_EN, 0);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int yt8531_probe(struct phy_device *phydev)
+{
+ struct ytphy_plat_priv *priv;
+
+ priv = calloc(1, sizeof(struct ytphy_plat_priv));
+ if (!priv)
+ return -ENOMEM;
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static struct phy_driver motorcomm8531_driver = {
+ .name = "YT8531 Gigabit Ethernet",
+ .uid = PHY_ID_YT8531,
+ .mask = PHY_ID_MASK,
+ .features = PHY_GBIT_FEATURES,
+ .probe = &yt8531_probe,
+ .config = &yt8531_config,
+ .startup = &yt8531_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_motorcomm_init(void)
+{
+ phy_register(&motorcomm8531_driver);
+
+ return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 80230b907c..78bde61798 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -570,6 +570,9 @@ int phy_init(void)
#endif
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
phy_xilinx_gmii2rgmii_init();
+#endif
+#ifdef CONFIG_PHY_MOTORCOMM
+ phy_motorcomm_init();
#endif
genphy_init();
@@ -755,7 +758,6 @@ static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
int r = get_phy_id(bus, addr, devad, &phy_id);
-
/*
* If the PHY ID is flat 0 we ignore it. There are C45 PHYs
* that return all 0s for C22 reads (like Aquantia AQR112) and
diff --git a/include/phy.h b/include/phy.h
index 87aa86c2e7..f7bb2fe0af 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -344,6 +344,7 @@ int phy_mscc_init(void);
int phy_fixed_init(void);
int phy_ncsi_init(void);
int phy_xilinx_gmii2rgmii_init(void);
+int phy_motorcomm_init(void);
int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
2023-03-29 10:27 [PATCH v2 0/5] Add ethernet driver for StarFive JH7110 SoC Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy Yanhong Wang
@ 2023-03-29 10:27 ` Yanhong Wang
2023-03-29 20:02 ` Simon Glass
2023-03-29 10:27 ` [PATCH v2 3/5] riscv: dts: jh7110: Add ethernet device tree nodes Yanhong Wang
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Yanhong Wang @ 2023-03-29 10:27 UTC (permalink / raw)
To: u-boot, Rick Chen, Leo, Joe Hershberger, Ramon Fried; +Cc: Yanhong Wang
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
---
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 +++++++++++++++++++++++++++++
5 files changed, 264 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ceadee98a1..161289d00f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 75daa5e694..69af678757 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 112deb546d..9aecd56e73 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1718,6 +1718,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)&eqos_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)&eqos_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 0000000000..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+#include <asm/gpio.h>
+#include <clk.h>
+#include <dm.h>
+#include <eth_phy.h>
+#include <net.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+struct starfive_platform_data {
+ struct regmap *regmap;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ phy_interface_t interface;
+ u32 offset;
+ u32 shift;
+ bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (data->interface) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+ 2, 0, &args);
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ data->offset = args.args[0];
+ data->shift = args.args[1];
+ data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(data->regmap)) {
+ ret = PTR_ERR(data->regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct clk *pclk, *c;
+ ulong rate;
+ int ret;
+
+ /* Generally, the rgmii_tx clock is provided by the internal clock,
+ * which needs to match the corresponding clock frequency according
+ * to different speeds. If the rgmii_tx clock is provided by the
+ * external rgmii_rxin, there is no need to configure the clock
+ * internally, because rgmii_rxin will be adaptively adjusted.
+ */
+ if (data->tx_use_rgmii_clk)
+ return 0;
+
+ switch (eqos->phy->speed) {
+ case SPEED_1000:
+ rate = 125 * 1000 * 1000;
+ break;
+ case SPEED_100:
+ rate = 25 * 1000 * 1000;
+ break;
+ case SPEED_10:
+ rate = 2.5 * 1000 * 1000;
+ break;
+ default:
+ pr_err("invalid speed %d", eqos->phy->speed);
+ return -EINVAL;
+ }
+
+ /* eqos->clk_tx clock has no set rate operation, so just set the parent
+ * clock rate directly
+ */
+ ret = clk_get_by_id(eqos->clk_tx.id, &c);
+ if (ret)
+ return ret;
+
+ pclk = clk_get_parent(c);
+ if (pclk) {
+ ret = clk_set_rate(pclk, rate);
+ if (ret < 0) {
+ pr_err("jh7110 (clk_tx, %lu) failed: %d", rate, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static ulong eqos_get_tick_clk_rate_jh7110(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ return clk_get_rate(&eqos->clk_tx);
+}
+
+static int eqos_start_clks_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+
+ return clk_enable_bulk(&data->clks);
+}
+
+static int eqos_stop_clks_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+
+ return clk_disable_bulk(&data->clks);
+}
+
+static int eqos_start_resets_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+
+ return reset_deassert_bulk(&data->resets);
+}
+
+static int eqos_stop_resets_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+
+ return reset_assert_bulk(&data->resets);
+}
+
+static int eqos_remove_resources_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+
+ reset_assert_bulk(&data->resets);
+ clk_disable_bulk(&data->clks);
+
+ return 0;
+}
+
+static int eqos_probe_resources_jh7110(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data;
+ int ret;
+
+ data = calloc(1, sizeof(struct starfive_platform_data));
+ if (!data)
+ return -ENOMEM;
+
+ pdata->priv_pdata = data;
+ data->interface = eqos->config->interface(dev);
+ if (data->interface == PHY_INTERFACE_MODE_NA) {
+ pr_err("Invalid PHY interface\n");
+ return -EINVAL;
+ }
+
+ ret = reset_get_bulk(dev, &data->resets);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_bulk(dev, &data->clks);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_name(dev, "gtx", &eqos->clk_tx);
+ if (ret)
+ return ret;
+
+ data->tx_use_rgmii_clk = dev_read_bool(dev, "starfive,tx-use-rgmii-clk");
+
+ return eqos_interface_init_jh7110(dev);
+}
+
+static struct eqos_ops eqos_jh7110_ops = {
+ .eqos_inval_desc = eqos_inval_desc_generic,
+ .eqos_flush_desc = eqos_flush_desc_generic,
+ .eqos_inval_buffer = eqos_inval_buffer_generic,
+ .eqos_flush_buffer = eqos_flush_buffer_generic,
+ .eqos_probe_resources = eqos_probe_resources_jh7110,
+ .eqos_remove_resources = eqos_remove_resources_jh7110,
+ .eqos_stop_resets = eqos_stop_resets_jh7110,
+ .eqos_start_resets = eqos_start_resets_jh7110,
+ .eqos_stop_clks = eqos_stop_clks_jh7110,
+ .eqos_start_clks = eqos_start_clks_jh7110,
+ .eqos_calibrate_pads = eqos_null_ops,
+ .eqos_disable_calibration = eqos_null_ops,
+ .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
+ .eqos_get_enetaddr = eqos_null_ops,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
+};
+
+/* mdio_wait: There is no need to wait after setting the MAC_MDIO_Address register
+ * swr_wait: Software reset bit must be read at least 4 CSR clock cycles
+ * after it is written to 1.
+ * config_mac: Enable rx queue to DCB mode.
+ * config_mac_mdio: CSR clock range is 250-300 Mhz.
+ * axi_bus_width: The width of the data bus is 64 bit.
+ */
+struct eqos_config __maybe_unused eqos_jh7110_config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 0,
+ .swr_wait = 4,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+ .axi_bus_width = EQOS_AXI_WIDTH_64,
+ .interface = dev_read_phy_mode,
+ .ops = &eqos_jh7110_ops
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/5] riscv: dts: jh7110: Add ethernet device tree nodes
2023-03-29 10:27 [PATCH v2 0/5] Add ethernet driver for StarFive JH7110 SoC Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer Yanhong Wang
@ 2023-03-29 10:27 ` Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 4/5] riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 5/5] configs: starfive: Enable ethernet configuration for StarFive VisionFive 2 Yanhong Wang
4 siblings, 0 replies; 9+ messages in thread
From: Yanhong Wang @ 2023-03-29 10:27 UTC (permalink / raw)
To: u-boot, Rick Chen, Leo, Joe Hershberger, Ramon Fried; +Cc: Yanhong Wang
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
---
arch/riscv/dts/jh7110.dtsi | 69 ++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..58e332e9d7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
#clock-cells = <0>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <4>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -539,6 +546,68 @@
status = "disabled";
};
+ gmac0: ethernet@16030000 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x16030000 0x0 0x10000>;
+ clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
+ <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
+ <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
+ <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
+ <&aoncrg JH7110_AONRST_GMAC0_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <7>, <6>, <5>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <&aon_syscon 0xc 0x12>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@16040000 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x16040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
+ <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
+ <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
+ <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
+ <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
+ <&syscrg JH7110_SYSRST_GMAC1_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <78>, <77>, <76>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <&sys_syscon 0x90 0x2>;
+ status = "disabled";
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 4/5] riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board
2023-03-29 10:27 [PATCH v2 0/5] Add ethernet driver for StarFive JH7110 SoC Yanhong Wang
` (2 preceding siblings ...)
2023-03-29 10:27 ` [PATCH v2 3/5] riscv: dts: jh7110: Add ethernet device tree nodes Yanhong Wang
@ 2023-03-29 10:27 ` Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 5/5] configs: starfive: Enable ethernet configuration for StarFive VisionFive 2 Yanhong Wang
4 siblings, 0 replies; 9+ messages in thread
From: Yanhong Wang @ 2023-03-29 10:27 UTC (permalink / raw)
To: u-boot, Rick Chen, Leo, Joe Hershberger, Ramon Fried; +Cc: Yanhong Wang
The StarFive VisionFive2 board include 1.2A and 1.3B version.
v1.3B uses motorcomm YT8531(rgmii-id phy) x2, phy clock need delay and
inverse configurations.
v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs phy clock
delay configurations.
v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and
tx to external clock sources.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
---
.../jh7110-starfive-visionfive-2-v1.2a.dts | 13 +++++++
.../jh7110-starfive-visionfive-2-v1.3b.dts | 27 +++++++++++++++
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 +++++++++++++++++++
3 files changed, 74 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
index b9d26d7af7..918e77220a 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -10,3 +10,16 @@
model = "StarFive VisionFive 2 v1.2A";
compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
};
+
+&gmac1 {
+ phy-mode = "rmii";
+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
+ <&syscrg JH7110_SYSCLK_GMAC1_RX>;
+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
+ <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
+};
+
+&phy0 {
+ rx-internal-delay-ps = <1900>;
+ tx-internal-delay-ps = <1350>;
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
index 3b3b3453a1..0fcd6ab80f 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -10,3 +10,30 @@
model = "StarFive VisionFive 2 v1.3B";
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
};
+
+&gmac0 {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+};
+
+&gmac1 {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
+};
+
+&phy0 {
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-100-inverted;
+ motorcomm,tx-clk-1000-inverted;
+ rx-internal-delay-ps = <1900>;
+ tx-internal-delay-ps = <1500>;
+};
+
+&phy1 {
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-100-inverted;
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..3c1148ae2d 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 = &i2c2;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <&osc>;
assigned-clock-rates = <0>;
};
+
+&gmac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 5/5] configs: starfive: Enable ethernet configuration for StarFive VisionFive 2
2023-03-29 10:27 [PATCH v2 0/5] Add ethernet driver for StarFive JH7110 SoC Yanhong Wang
` (3 preceding siblings ...)
2023-03-29 10:27 ` [PATCH v2 4/5] riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board Yanhong Wang
@ 2023-03-29 10:27 ` Yanhong Wang
4 siblings, 0 replies; 9+ messages in thread
From: Yanhong Wang @ 2023-03-29 10:27 UTC (permalink / raw)
To: u-boot, Rick Chen, Leo, Joe Hershberger, Ramon Fried; +Cc: Yanhong Wang
Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet
function for StarFive VisionFive 2 board,including versions 1.2A and
1.3B.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
---
configs/starfive_visionfive2_12a_defconfig | 12 +++++++++++-
configs/starfive_visionfive2_13b_defconfig | 12 +++++++++++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/configs/starfive_visionfive2_12a_defconfig b/configs/starfive_visionfive2_12a_defconfig
index e0f98292ff..1340701c69 100644
--- a/configs/starfive_visionfive2_12a_defconfig
+++ b/configs/starfive_visionfive2_12a_defconfig
@@ -21,8 +21,8 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
@@ -52,6 +52,9 @@ CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_STARFIVE=y
+CONFIG_RGMII=y
+CONFIG_RMII=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
diff --git a/configs/starfive_visionfive2_13b_defconfig b/configs/starfive_visionfive2_13b_defconfig
index 550d0ff3ab..a6415a6cde 100644
--- a/configs/starfive_visionfive2_13b_defconfig
+++ b/configs/starfive_visionfive2_13b_defconfig
@@ -21,8 +21,8 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
@@ -52,6 +52,9 @@ CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_STARFIVE=y
+CONFIG_RGMII=y
+CONFIG_RMII=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
2023-03-29 10:27 ` [PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer Yanhong Wang
@ 2023-03-29 20:02 ` Simon Glass
2023-03-30 2:03 ` yanhong wang
0 siblings, 1 reply; 9+ messages in thread
From: Simon Glass @ 2023-03-29 20:02 UTC (permalink / raw)
To: Yanhong Wang; +Cc: u-boot, Rick Chen, Leo, Joe Hershberger, Ramon Fried
Hi Yanhong,
On Wed, 29 Mar 2023 at 23:29, Yanhong Wang
<yanhong.wang@starfivetech.com> wrote:
>
> The StarFive ETHQOS hardware has its own clock and reset,so add a
> corresponding glue driver to configure them.
>
> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
> ---
> drivers/net/Kconfig | 7 +
> drivers/net/Makefile | 1 +
> drivers/net/dwc_eth_qos.c | 6 +
> drivers/net/dwc_eth_qos.h | 1 +
> drivers/net/dwc_eth_qos_starfive.c | 249 +++++++++++++++++++++++++++++
> 5 files changed, 264 insertions(+)
> create mode 100644 drivers/net/dwc_eth_qos_starfive.c
>
[..]
> +static struct eqos_ops eqos_jh7110_ops = {
> + .eqos_inval_desc = eqos_inval_desc_generic,
> + .eqos_flush_desc = eqos_flush_desc_generic,
> + .eqos_inval_buffer = eqos_inval_buffer_generic,
> + .eqos_flush_buffer = eqos_flush_buffer_generic,
> + .eqos_probe_resources = eqos_probe_resources_jh7110,
> + .eqos_remove_resources = eqos_remove_resources_jh7110,
> + .eqos_stop_resets = eqos_stop_resets_jh7110,
> + .eqos_start_resets = eqos_start_resets_jh7110,
> + .eqos_stop_clks = eqos_stop_clks_jh7110,
> + .eqos_start_clks = eqos_start_clks_jh7110,
> + .eqos_calibrate_pads = eqos_null_ops,
> + .eqos_disable_calibration = eqos_null_ops,
> + .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
> + .eqos_get_enetaddr = eqos_null_ops,
> + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
> +};
What is eqos_ops? Why is this layer needed in U-Boot?
Can you not use driver model directly?
Regards,
Simon
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
2023-03-29 20:02 ` Simon Glass
@ 2023-03-30 2:03 ` yanhong wang
0 siblings, 0 replies; 9+ messages in thread
From: yanhong wang @ 2023-03-30 2:03 UTC (permalink / raw)
To: Simon Glass; +Cc: u-boot, Rick Chen, Leo, Joe Hershberger, Ramon Fried
On 2023/3/30 4:02, Simon Glass wrote:
> Hi Yanhong,
>
> On Wed, 29 Mar 2023 at 23:29, Yanhong Wang
> <yanhong.wang@starfivetech.com> wrote:
>>
>> The StarFive ETHQOS hardware has its own clock and reset,so add a
>> corresponding glue driver to configure them.
>>
>> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
>> ---
>> drivers/net/Kconfig | 7 +
>> drivers/net/Makefile | 1 +
>> drivers/net/dwc_eth_qos.c | 6 +
>> drivers/net/dwc_eth_qos.h | 1 +
>> drivers/net/dwc_eth_qos_starfive.c | 249 +++++++++++++++++++++++++++++
>> 5 files changed, 264 insertions(+)
>> create mode 100644 drivers/net/dwc_eth_qos_starfive.c
>>
>
> [..]
>
>> +static struct eqos_ops eqos_jh7110_ops = {
>> + .eqos_inval_desc = eqos_inval_desc_generic,
>> + .eqos_flush_desc = eqos_flush_desc_generic,
>> + .eqos_inval_buffer = eqos_inval_buffer_generic,
>> + .eqos_flush_buffer = eqos_flush_buffer_generic,
>> + .eqos_probe_resources = eqos_probe_resources_jh7110,
>> + .eqos_remove_resources = eqos_remove_resources_jh7110,
>> + .eqos_stop_resets = eqos_stop_resets_jh7110,
>> + .eqos_start_resets = eqos_start_resets_jh7110,
>> + .eqos_stop_clks = eqos_stop_clks_jh7110,
>> + .eqos_start_clks = eqos_start_clks_jh7110,
>> + .eqos_calibrate_pads = eqos_null_ops,
>> + .eqos_disable_calibration = eqos_null_ops,
>> + .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
>> + .eqos_get_enetaddr = eqos_null_ops,
>> + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
>> +};
>
> What is eqos_ops? Why is this layer needed in U-Boot?
>
The JH7110 uses the Synopsys Designware Ethernet QOS (Quality Of Service) IP block,
the driver implementation uses 'dwc_eth_qos.c,' but there are some differences
in clock and reset, so there is a corresponding glue layer. This glue layer references
the implementation of 'dwc_eth_qos_imx.c' and 'dwc_eth_qos_qcom.c'.
> Can you not use driver model directly?
> If you use the driver model directly, many of the implementations are the same
as "dwc_eth_qos.c", so to avoid duplicate implementations, just add the glue layer.
> Regards,
> Simon
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
2023-03-29 10:27 ` [PATCH v2 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy Yanhong Wang
@ 2023-04-02 7:36 ` Ramon Fried
0 siblings, 0 replies; 9+ messages in thread
From: Ramon Fried @ 2023-04-02 7:36 UTC (permalink / raw)
To: Yanhong Wang; +Cc: u-boot, Rick Chen, Leo, Joe Hershberger
On Wed, Mar 29, 2023 at 1:27 PM Yanhong Wang
<yanhong.wang@starfivetech.com> wrote:
>
> Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
> verified the driver on StarFive VisionFive2 board.
>
> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
> ---
> drivers/net/phy/Kconfig | 6 +
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/motorcomm.c | 450 ++++++++++++++++++++++++++++++++++++
> drivers/net/phy/phy.c | 4 +-
> include/phy.h | 1 +
> 5 files changed, 461 insertions(+), 1 deletion(-)
> create mode 100644 drivers/net/phy/motorcomm.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 5eaff053a0..aba718566a 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -212,6 +212,12 @@ config PHY_MICREL_KSZ8XXX
>
> endif # PHY_MICREL
>
> +config PHY_MOTORCOMM
> + tristate "Motorcomm PHYs"
> + help
> + Enables support for Motorcomm network PHYs.
> + Currently supports the YT8531 Gigabit Ethernet PHYs.
> +
> config PHY_MSCC
> bool "Microsemi Corp Ethernet PHYs support"
>
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index d38e99e717..e9523fed2e 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MARVELL) += marvell.o
> obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
> obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
> obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
> +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
> obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
> obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
> obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
> diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
> new file mode 100644
> index 0000000000..6e37700adc
> --- /dev/null
> +++ b/drivers/net/phy/motorcomm.c
> @@ -0,0 +1,450 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Motorcomm 8531 PHY driver.
> + *
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <malloc.h>
> +#include <phy.h>
> +#include <linux/bitfield.h>
> +
> +#define PHY_ID_YT8531 0x4f51e91b
> +#define PHY_ID_MASK GENMASK(31, 0)
> +
> +/* Extended Register's Address Offset Register */
> +#define YTPHY_PAGE_SELECT 0x1E
> +
> +/* Extended Register's Data Register */
> +#define YTPHY_PAGE_DATA 0x1F
> +
> +#define YTPHY_SYNCE_CFG_REG 0xA012
> +
> +#define YTPHY_DTS_OUTPUT_CLK_DIS 0
> +#define YTPHY_DTS_OUTPUT_CLK_25M 25000000
> +#define YTPHY_DTS_OUTPUT_CLK_125M 125000000
> +
> +#define YT8531_SCR_SYNCE_ENABLE BIT(6)
> +/* 1b0 output 25m clock *default*
> + * 1b1 output 125m clock
> + */
> +#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4)
> +#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1)
> +#define YT8531_SCR_CLK_SRC_PLL_125M 0
> +#define YT8531_SCR_CLK_SRC_UTP_RX 1
> +#define YT8531_SCR_CLK_SRC_SDS_RX 2
> +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3
> +#define YT8531_SCR_CLK_SRC_REF_25M 4
> +#define YT8531_SCR_CLK_SRC_SSC_25M 5
> +
> +/* 1b0 use original tx_clk_rgmii *default*
> + * 1b1 use inverted tx_clk_rgmii.
> + */
> +#define YT8531_RC1R_TX_CLK_SEL_INVERTED BIT(14)
> +#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10)
> +#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4)
> +#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0)
> +#define YT8531_RC1R_RGMII_0_000_NS 0
> +#define YT8531_RC1R_RGMII_0_150_NS 1
> +#define YT8531_RC1R_RGMII_0_300_NS 2
> +#define YT8531_RC1R_RGMII_0_450_NS 3
> +#define YT8531_RC1R_RGMII_0_600_NS 4
> +#define YT8531_RC1R_RGMII_0_750_NS 5
> +#define YT8531_RC1R_RGMII_0_900_NS 6
> +#define YT8531_RC1R_RGMII_1_050_NS 7
> +#define YT8531_RC1R_RGMII_1_200_NS 8
> +#define YT8531_RC1R_RGMII_1_350_NS 9
> +#define YT8531_RC1R_RGMII_1_500_NS 10
> +#define YT8531_RC1R_RGMII_1_650_NS 11
> +#define YT8531_RC1R_RGMII_1_800_NS 12
> +#define YT8531_RC1R_RGMII_1_950_NS 13
> +#define YT8531_RC1R_RGMII_2_100_NS 14
> +#define YT8531_RC1R_RGMII_2_250_NS 15
> +
> +/* Phy gmii clock gating Register */
> +#define YT8531_CLOCK_GATING_REG 0xC
> +#define YT8531_CGR_RX_CLK_EN BIT(12)
> +
> +/* Specific Status Register */
> +#define YTPHY_SPECIFIC_STATUS_REG 0x11
> +#define YTPHY_DUPLEX_MASK BIT(13)
> +#define YTPHY_DUPLEX_SHIFT 13
> +#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14)
> +#define YTPHY_SPEED_MODE_SHIFT 14
> +
> +#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27
> +#define YT8531_ESC1R_SLEEP_SW BIT(15)
> +#define YT8531_ESC1R_PLLON_SLP BIT(14)
> +
> +#define YT8531_RGMII_CONFIG1_REG 0xA003
> +
> +#define YT8531_CHIP_CONFIG_REG 0xA001
> +#define YT8531_CCR_SW_RST BIT(15)
> +/* 1b0 disable 1.9ns rxc clock delay *default*
> + * 1b1 enable 1.9ns rxc clock delay
> + */
> +#define YT8531_CCR_RXC_DLY_EN BIT(8)
> +#define YT8531_CCR_RXC_DLY_1_900_NS 1900
> +
> +/* bits in struct ytphy_plat_priv->flag */
> +#define TX_CLK_ADJ_ENABLED BIT(0)
> +#define AUTO_SLEEP_DISABLED BIT(1)
> +#define KEEP_PLL_ENABLED BIT(2)
> +#define TX_CLK_10_INVERTED BIT(3)
> +#define TX_CLK_100_INVERTED BIT(4)
> +#define TX_CLK_1000_INVERTED BIT(5)
> +
> +struct ytphy_plat_priv {
> + u32 rx_delay_ps;
> + u32 tx_delay_ps;
> + u32 clk_out_frequency;
> + u32 flag;
> +};
> +
> +/**
> + * struct ytphy_cfg_reg_map - map a config value to a register value
> + * @cfg: value in device configuration
> + * @reg: value in the register
> + */
> +struct ytphy_cfg_reg_map {
> + u32 cfg;
> + u32 reg;
> +};
> +
> +static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = {
> + /* for tx delay / rx delay with YT8531_CCR_RXC_DLY_EN is not set. */
> + { 0, YT8531_RC1R_RGMII_0_000_NS },
> + { 150, YT8531_RC1R_RGMII_0_150_NS },
> + { 300, YT8531_RC1R_RGMII_0_300_NS },
> + { 450, YT8531_RC1R_RGMII_0_450_NS },
> + { 600, YT8531_RC1R_RGMII_0_600_NS },
> + { 750, YT8531_RC1R_RGMII_0_750_NS },
> + { 900, YT8531_RC1R_RGMII_0_900_NS },
> + { 1050, YT8531_RC1R_RGMII_1_050_NS },
> + { 1200, YT8531_RC1R_RGMII_1_200_NS },
> + { 1350, YT8531_RC1R_RGMII_1_350_NS },
> + { 1500, YT8531_RC1R_RGMII_1_500_NS },
> + { 1650, YT8531_RC1R_RGMII_1_650_NS },
> + { 1800, YT8531_RC1R_RGMII_1_800_NS },
> + { 1950, YT8531_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */
> + { 2100, YT8531_RC1R_RGMII_2_100_NS },
> + { 2250, YT8531_RC1R_RGMII_2_250_NS },
> +
> + /* only for rx delay with YT8531_CCR_RXC_DLY_EN is set. */
> + { 0 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_000_NS },
> + { 150 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_150_NS },
> + { 300 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_300_NS },
> + { 450 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_450_NS },
> + { 600 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_600_NS },
> + { 750 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_750_NS },
> + { 900 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_0_900_NS },
> + { 1050 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_050_NS },
> + { 1200 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_200_NS },
> + { 1350 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_350_NS },
> + { 1500 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_500_NS },
> + { 1650 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_650_NS },
> + { 1800 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_800_NS },
> + { 1950 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_1_950_NS },
> + { 2100 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_2_100_NS },
> + { 2250 + YT8531_CCR_RXC_DLY_1_900_NS, YT8531_RC1R_RGMII_2_250_NS }
> +};
> +
> +static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
> + u32 val,
> + u16 *rxc_dly_en)
> +{
> + int tb_size = ARRAY_SIZE(ytphy_rgmii_delays);
> + int tb_size_half = tb_size / 2;
> + int i;
> +
> + /* when rxc_dly_en is NULL, it is get the delay for tx, only half of
> + * tb_size is valid.
> + */
> + if (!rxc_dly_en)
> + tb_size = tb_size_half;
> +
> + for (i = 0; i < tb_size; i++) {
> + if (ytphy_rgmii_delays[i].cfg == val) {
> + if (rxc_dly_en && i < tb_size_half)
> + *rxc_dly_en = 0;
> + return ytphy_rgmii_delays[i].reg;
> + }
> + }
> +
> + pr_warn("Unsupported value %d, using default (%u)\n",
> + val, YT8531_RC1R_RGMII_1_950_NS);
> +
> + /* when rxc_dly_en is not NULL, it is get the delay for rx.
> + * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps,
> + * so YT8531_CCR_RXC_DLY_EN should not be set.
> + */
> + if (rxc_dly_en)
> + *rxc_dly_en = 0;
> +
> + return YT8531_RC1R_RGMII_1_950_NS;
> +}
> +
> +static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
> + u16 set)
> +{
> + int ret;
> +
> + ret = phy_write(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_SELECT, regnum);
> + if (ret < 0)
> + return ret;
> +
> + return phy_modify(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_DATA, mask, set);
> +}
> +
> +static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
> +{
> + struct ytphy_plat_priv *priv = phydev->priv;
> + u16 rxc_dly_en = YT8531_CCR_RXC_DLY_EN;
> + u32 rx_reg, tx_reg;
> + u16 mask, val = 0;
> + int ret;
> +
> + rx_reg = ytphy_get_delay_reg_value(phydev, priv->rx_delay_ps,
> + &rxc_dly_en);
> + tx_reg = ytphy_get_delay_reg_value(phydev, priv->tx_delay_ps,
> + NULL);
> +
> + switch (phydev->interface) {
> + case PHY_INTERFACE_MODE_RGMII:
> + rxc_dly_en = 0;
> + break;
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg);
> + break;
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + rxc_dly_en = 0;
> + val |= FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
> + break;
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg) |
> + FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
> + break;
> + default: /* do not support other modes */
> + return -EOPNOTSUPP;
> + }
> +
> + ret = ytphy_modify_ext(phydev, YT8531_CHIP_CONFIG_REG,
> + YT8531_CCR_RXC_DLY_EN, rxc_dly_en);
> + if (ret < 0)
> + return ret;
> +
> + /* Generally, it is not necessary to adjust YT8531_RC1R_FE_TX_DELAY */
> + mask = YT8531_RC1R_RX_DELAY_MASK | YT8531_RC1R_GE_TX_DELAY_MASK;
> + return ytphy_modify_ext(phydev, YT8531_RGMII_CONFIG1_REG, mask, val);
> +}
> +
> +static int yt8531_parse_status(struct phy_device *phydev)
> +{
> + int val;
> + int speed, speed_mode;
> +
> + val = phy_read(phydev, MDIO_DEVAD_NONE, YTPHY_SPECIFIC_STATUS_REG);
> + if (val < 0)
> + return val;
> +
> + speed_mode = (val & YTPHY_SPEED_MODE_MASK) >> YTPHY_SPEED_MODE_SHIFT;
> + switch (speed_mode) {
> + case 2:
> + speed = SPEED_1000;
> + break;
> + case 1:
> + speed = SPEED_100;
> + break;
> + default:
> + speed = SPEED_10;
> + break;
> + }
> +
> + phydev->speed = speed;
> + phydev->duplex = (val & YTPHY_DUPLEX_MASK) >> YTPHY_DUPLEX_SHIFT;
> +
> + return 0;
> +}
> +
> +static int yt8531_startup(struct phy_device *phydev)
> +{
> + struct ytphy_plat_priv *priv = phydev->priv;
> + u16 val = 0;
> + int ret;
> +
> + ret = genphy_update_link(phydev);
> + if (ret)
> + return ret;
> +
> + ret = yt8531_parse_status(phydev);
> + if (ret)
> + return ret;
> +
> + if (phydev->speed < 0)
> + return -EINVAL;
> +
> + if (!(priv->flag & TX_CLK_ADJ_ENABLED))
> + return 0;
> +
> + switch (phydev->speed) {
> + case SPEED_1000:
> + if (priv->flag & TX_CLK_1000_INVERTED)
> + val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
> + break;
> + case SPEED_100:
> + if (priv->flag & TX_CLK_100_INVERTED)
> + val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
> + break;
> + case SPEED_10:
> + if (priv->flag & TX_CLK_10_INVERTED)
> + val = YT8531_RC1R_TX_CLK_SEL_INVERTED;
> + break;
> + default:
> + printf("UNKNOWN SPEED\n");
> + return -EINVAL;
> + }
> +
> + ret = ytphy_modify_ext(phydev, YT8531_RGMII_CONFIG1_REG,
> + YT8531_RC1R_TX_CLK_SEL_INVERTED, val);
> + if (ret < 0)
> + pr_warn("Modify TX_CLK_SEL err:%d\n", ret);
> +
> + return 0;
> +}
> +
> +static void ytphy_dt_parse(struct phy_device *phydev)
> +{
> + struct ytphy_plat_priv *priv = phydev->priv;
> + int ret;
> +
> + ret = ofnode_read_u32(phydev->node, "motorcomm,clk-out-frequency-hz",
> + &priv->clk_out_frequency);
> + if (ret < 0)
> + priv->clk_out_frequency = YTPHY_DTS_OUTPUT_CLK_DIS;
> +
> + ret = ofnode_read_u32(phydev->node, "rx-internal-delay-ps",
> + &priv->rx_delay_ps);
> + if (ret < 0)
> + priv->rx_delay_ps = YT8531_RC1R_RGMII_1_950_NS;
> +
> + ret = ofnode_read_u32(phydev->node, "tx-internal-delay-ps",
> + &priv->tx_delay_ps);
> + if (ret < 0)
> + priv->tx_delay_ps = YT8531_RC1R_RGMII_1_950_NS;
> +
> + if (ofnode_read_bool(phydev->node, "motorcomm,auto-sleep-disabled"))
> + priv->flag |= AUTO_SLEEP_DISABLED;
> +
> + if (ofnode_read_bool(phydev->node, "motorcomm,keep-pll-enabled"))
> + priv->flag |= KEEP_PLL_ENABLED;
> +
> + if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-adj-enabled"))
> + priv->flag |= TX_CLK_ADJ_ENABLED;
> +
> + if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-10-inverted"))
> + priv->flag |= TX_CLK_10_INVERTED;
> +
> + if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-100-inverted"))
> + priv->flag |= TX_CLK_100_INVERTED;
> +
> + if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-1000-inverted"))
> + priv->flag |= TX_CLK_1000_INVERTED;
> +}
> +
> +static int yt8531_config(struct phy_device *phydev)
> +{
> + struct ytphy_plat_priv *priv = phydev->priv;
> + u16 mask, val;
> + int ret;
> +
> + ret = genphy_config_aneg(phydev);
> + if (ret < 0)
> + return ret;
> +
> + ytphy_dt_parse(phydev);
> + switch (priv->clk_out_frequency) {
> + case YTPHY_DTS_OUTPUT_CLK_DIS:
> + mask = YT8531_SCR_SYNCE_ENABLE;
> + val = 0;
> + break;
> + case YTPHY_DTS_OUTPUT_CLK_25M:
> + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
> + YT8531_SCR_CLK_FRE_SEL_125M;
> + val = YT8531_SCR_SYNCE_ENABLE |
> + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
> + YT8531_SCR_CLK_SRC_REF_25M);
> + break;
> + case YTPHY_DTS_OUTPUT_CLK_125M:
> + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
> + YT8531_SCR_CLK_FRE_SEL_125M;
> + val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M |
> + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
> + YT8531_SCR_CLK_SRC_PLL_125M);
> + break;
> + default:
> + pr_warn("Freq err:%u\n", priv->clk_out_frequency);
> + return -EINVAL;
> + }
> +
> + ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask,
> + val);
> + if (ret < 0)
> + return ret;
> +
> + ret = ytphy_rgmii_clk_delay_config(phydev);
> + if (ret < 0)
> + return ret;
> +
> + if (priv->flag & AUTO_SLEEP_DISABLED) {
> + /* disable auto sleep */
> + ret = ytphy_modify_ext(phydev,
> + YT8531_EXTREG_SLEEP_CONTROL1_REG,
> + YT8531_ESC1R_SLEEP_SW, 0);
> + if (ret < 0)
> + return ret;
> + }
> +
> + if (priv->flag & KEEP_PLL_ENABLED) {
> + /* enable RXC clock when no wire plug */
> + ret = ytphy_modify_ext(phydev,
> + YT8531_CLOCK_GATING_REG,
> + YT8531_CGR_RX_CLK_EN, 0);
> + if (ret < 0)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int yt8531_probe(struct phy_device *phydev)
> +{
> + struct ytphy_plat_priv *priv;
> +
> + priv = calloc(1, sizeof(struct ytphy_plat_priv));
> + if (!priv)
> + return -ENOMEM;
> +
> + phydev->priv = priv;
> +
> + return 0;
> +}
> +
> +static struct phy_driver motorcomm8531_driver = {
> + .name = "YT8531 Gigabit Ethernet",
> + .uid = PHY_ID_YT8531,
> + .mask = PHY_ID_MASK,
> + .features = PHY_GBIT_FEATURES,
> + .probe = &yt8531_probe,
> + .config = &yt8531_config,
> + .startup = &yt8531_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +
> +int phy_motorcomm_init(void)
> +{
> + phy_register(&motorcomm8531_driver);
> +
> + return 0;
> +}
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index 80230b907c..78bde61798 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -570,6 +570,9 @@ int phy_init(void)
> #endif
> #ifdef CONFIG_PHY_XILINX_GMII2RGMII
> phy_xilinx_gmii2rgmii_init();
> +#endif
> +#ifdef CONFIG_PHY_MOTORCOMM
> + phy_motorcomm_init();
> #endif
> genphy_init();
>
> @@ -755,7 +758,6 @@ static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
> while (phy_mask) {
> int addr = ffs(phy_mask) - 1;
> int r = get_phy_id(bus, addr, devad, &phy_id);
> -
> /*
> * If the PHY ID is flat 0 we ignore it. There are C45 PHYs
> * that return all 0s for C22 reads (like Aquantia AQR112) and
> diff --git a/include/phy.h b/include/phy.h
> index 87aa86c2e7..f7bb2fe0af 100644
> --- a/include/phy.h
> +++ b/include/phy.h
> @@ -344,6 +344,7 @@ int phy_mscc_init(void);
> int phy_fixed_init(void);
> int phy_ncsi_init(void);
> int phy_xilinx_gmii2rgmii_init(void);
> +int phy_motorcomm_init(void);
>
> int board_phy_config(struct phy_device *phydev);
> int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
> --
> 2.17.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-04-02 7:37 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-29 10:27 [PATCH v2 0/5] Add ethernet driver for StarFive JH7110 SoC Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy Yanhong Wang
2023-04-02 7:36 ` Ramon Fried
2023-03-29 10:27 ` [PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer Yanhong Wang
2023-03-29 20:02 ` Simon Glass
2023-03-30 2:03 ` yanhong wang
2023-03-29 10:27 ` [PATCH v2 3/5] riscv: dts: jh7110: Add ethernet device tree nodes Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 4/5] riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board Yanhong Wang
2023-03-29 10:27 ` [PATCH v2 5/5] configs: starfive: Enable ethernet configuration for StarFive VisionFive 2 Yanhong Wang
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