* [PATCH] board: bsh: Update imx8mn ddr3l timing according to BSH hw team
@ 2022-08-22 10:14 Michael Trimarchi
2022-08-31 12:06 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 4+ messages in thread
From: Michael Trimarchi @ 2022-08-22 10:14 UTC (permalink / raw)
To: Ariel D'Alessandro, open list
Cc: Stefano Babic, Fabio Estavam, linux-amarula, open list
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 23 ++++++++++++---------
board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 23 ++++++++++++---------
2 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
index 0da641834d..33452d2ad5 100644
--- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
+++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
@@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x20 },
{ 0x3d400000, 0xa1040001 },
- { 0x3d400064, 0x610040 },
+ { 0x3d400064, 0x300040 },
{ 0x3d4000d0, 0xc00200c5 },
{ 0x3d4000d4, 0x1000b },
{ 0x3d4000dc, 0x1d700004 },
- { 0x3d4000e0, 0x180000 },
+ { 0x3d4000e0, 0x580000 },
{ 0x3d4000e4, 0x90000 },
- { 0x3d4000f0, 0x0 },
+ { 0x3d4000f0, 0x2 },
{ 0x3d4000f4, 0xee5 },
- { 0x3d400100, 0xc101b0e },
+ { 0x3d400100, 0xc100d0e },
{ 0x3d400104, 0x30314 },
{ 0x3d400108, 0x4060509 },
{ 0x3d40010c, 0x2006 },
@@ -67,10 +67,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400498, 0x7ff },
{ 0x3d40049c, 0xe00 },
{ 0x3d4004a0, 0x7ff },
- { 0x3d402064, 0x28001b },
+ { 0x3d402064, 0x14001b },
{ 0x3d4020dc, 0x12200004 },
- { 0x3d4020e0, 0x0 },
- { 0x3d402100, 0x7090b07 },
+ { 0x3d4020e0, 0x400000 },
+ { 0x3d402100, 0x7090507 },
{ 0x3d402104, 0x20209 },
{ 0x3d402108, 0x3030407 },
{ 0x3d40210c, 0x2006 },
@@ -680,12 +680,13 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
+ { 0x54009, 0x200 },
{ 0x5400b, 0x31f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1d70 },
{ 0x54030, 0x4 },
- { 0x54031, 0x18 },
+ { 0x54031, 0x58 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
@@ -700,11 +701,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
+ { 0x54009, 0x200 },
{ 0x5400b, 0x21f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1220 },
{ 0x54030, 0x4 },
+ { 0x54031, 0x40 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
@@ -886,11 +889,11 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x90026, 0x2b },
- { 0x2000b, 0x32 },
+ { 0x2000b, 0x1c2 },
{ 0x2000c, 0x64 },
{ 0x2000d, 0x3e8 },
{ 0x2000e, 0x2c },
- { 0x12000b, 0x14 },
+ { 0x12000b, 0xbb },
{ 0x12000c, 0x26 },
{ 0x12000d, 0x1a1 },
{ 0x12000e, 0x10 },
diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
index f845395ad9..6f3e49ff9c 100644
--- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
+++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
@@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x20 },
{ 0x3d400000, 0xa1040001 },
- { 0x3d400064, 0x610068 },
+ { 0x3d400064, 0x300068 },
{ 0x3d4000d0, 0xc00200c5 },
{ 0x3d4000d4, 0x1000b },
{ 0x3d4000dc, 0x1d700004 },
- { 0x3d4000e0, 0x180000 },
+ { 0x3d4000e0, 0x580000 },
{ 0x3d4000e4, 0x90000 },
- { 0x3d4000f0, 0x0 },
+ { 0x3d4000f0, 0x2 },
{ 0x3d4000f4, 0xee5 },
- { 0x3d400100, 0xc101b0e },
+ { 0x3d400100, 0xc100d0e },
{ 0x3d400104, 0x30314 },
{ 0x3d400108, 0x4060509 },
{ 0x3d40010c, 0x2006 },
@@ -67,10 +67,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400498, 0x7ff },
{ 0x3d40049c, 0xe00 },
{ 0x3d4004a0, 0x7ff },
- { 0x3d402064, 0x28003c },
+ { 0x3d402064, 0x14002c },
{ 0x3d4020dc, 0x12200004 },
- { 0x3d4020e0, 0x0 },
- { 0x3d402100, 0x7090b07 },
+ { 0x3d4020e0, 0x400000 },
+ { 0x3d402100, 0x7090507 },
{ 0x3d402104, 0x20209 },
{ 0x3d402108, 0x3030407 },
{ 0x3d40210c, 0x2006 },
@@ -680,12 +680,13 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
+ { 0x54009, 0x200 },
{ 0x5400b, 0x31f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1d70 },
{ 0x54030, 0x4 },
- { 0x54031, 0x18 },
+ { 0x54031, 0x58 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
@@ -700,11 +701,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
+ { 0x54009, 0x200 },
{ 0x5400b, 0x21f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1220 },
{ 0x54030, 0x4 },
+ { 0x54031, 0x40 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
@@ -886,11 +889,11 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x90026, 0x2b },
- { 0x2000b, 0x32 },
+ { 0x2000b, 0x1c2 },
{ 0x2000c, 0x64 },
{ 0x2000d, 0x3e8 },
{ 0x2000e, 0x2c },
- { 0x12000b, 0x14 },
+ { 0x12000b, 0xbb },
{ 0x12000c, 0x26 },
{ 0x12000d, 0x1a1 },
{ 0x12000e, 0x10 },
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] board: bsh: Update imx8mn ddr3l timing according to BSH hw team
2022-08-22 10:14 [PATCH] board: bsh: Update imx8mn ddr3l timing according to BSH hw team Michael Trimarchi
@ 2022-08-31 12:06 ` Michael Nazzareno Trimarchi
2022-08-31 12:11 ` Fabio Estevam
0 siblings, 1 reply; 4+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-08-31 12:06 UTC (permalink / raw)
To: Ariel D'Alessandro, open list
Cc: Stefano Babic, Fabio Estavam, linux-amarula
Hi Fabio
On Mon, Aug 22, 2022 at 12:14 PM Michael Trimarchi
<michael@amarulasolutions.com> wrote:
>
> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
> ---
Time to review or ask for changes?
Michael
> board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 23 ++++++++++++---------
> board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 23 ++++++++++++---------
> 2 files changed, 26 insertions(+), 20 deletions(-)
>
> diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
> index 0da641834d..33452d2ad5 100644
> --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
> +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c
> @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
> { 0x3d400304, 0x1 },
> { 0x3d400030, 0x20 },
> { 0x3d400000, 0xa1040001 },
> - { 0x3d400064, 0x610040 },
> + { 0x3d400064, 0x300040 },
> { 0x3d4000d0, 0xc00200c5 },
> { 0x3d4000d4, 0x1000b },
> { 0x3d4000dc, 0x1d700004 },
> - { 0x3d4000e0, 0x180000 },
> + { 0x3d4000e0, 0x580000 },
> { 0x3d4000e4, 0x90000 },
> - { 0x3d4000f0, 0x0 },
> + { 0x3d4000f0, 0x2 },
> { 0x3d4000f4, 0xee5 },
> - { 0x3d400100, 0xc101b0e },
> + { 0x3d400100, 0xc100d0e },
> { 0x3d400104, 0x30314 },
> { 0x3d400108, 0x4060509 },
> { 0x3d40010c, 0x2006 },
> @@ -67,10 +67,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
> { 0x3d400498, 0x7ff },
> { 0x3d40049c, 0xe00 },
> { 0x3d4004a0, 0x7ff },
> - { 0x3d402064, 0x28001b },
> + { 0x3d402064, 0x14001b },
> { 0x3d4020dc, 0x12200004 },
> - { 0x3d4020e0, 0x0 },
> - { 0x3d402100, 0x7090b07 },
> + { 0x3d4020e0, 0x400000 },
> + { 0x3d402100, 0x7090507 },
> { 0x3d402104, 0x20209 },
> { 0x3d402108, 0x3030407 },
> { 0x3d40210c, 0x2006 },
> @@ -680,12 +680,13 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
> { 0x54006, 0x140 },
> { 0x54007, 0x1000 },
> { 0x54008, 0x101 },
> + { 0x54009, 0x200 },
> { 0x5400b, 0x31f },
> { 0x5400c, 0xc8 },
> { 0x54012, 0x1 },
> { 0x5402f, 0x1d70 },
> { 0x54030, 0x4 },
> - { 0x54031, 0x18 },
> + { 0x54031, 0x58 },
> { 0x5403a, 0x1323 },
> { 0xd0000, 0x1 },
> };
> @@ -700,11 +701,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
> { 0x54006, 0x140 },
> { 0x54007, 0x1000 },
> { 0x54008, 0x101 },
> + { 0x54009, 0x200 },
> { 0x5400b, 0x21f },
> { 0x5400c, 0xc8 },
> { 0x54012, 0x1 },
> { 0x5402f, 0x1220 },
> { 0x54030, 0x4 },
> + { 0x54031, 0x40 },
> { 0x5403a, 0x1323 },
> { 0xd0000, 0x1 },
> };
> @@ -886,11 +889,11 @@ struct dram_cfg_param ddr_phy_pie[] = {
> { 0xd00e7, 0x400 },
> { 0x90017, 0x0 },
> { 0x90026, 0x2b },
> - { 0x2000b, 0x32 },
> + { 0x2000b, 0x1c2 },
> { 0x2000c, 0x64 },
> { 0x2000d, 0x3e8 },
> { 0x2000e, 0x2c },
> - { 0x12000b, 0x14 },
> + { 0x12000b, 0xbb },
> { 0x12000c, 0x26 },
> { 0x12000d, 0x1a1 },
> { 0x12000e, 0x10 },
> diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
> index f845395ad9..6f3e49ff9c 100644
> --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
> +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c
> @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
> { 0x3d400304, 0x1 },
> { 0x3d400030, 0x20 },
> { 0x3d400000, 0xa1040001 },
> - { 0x3d400064, 0x610068 },
> + { 0x3d400064, 0x300068 },
> { 0x3d4000d0, 0xc00200c5 },
> { 0x3d4000d4, 0x1000b },
> { 0x3d4000dc, 0x1d700004 },
> - { 0x3d4000e0, 0x180000 },
> + { 0x3d4000e0, 0x580000 },
> { 0x3d4000e4, 0x90000 },
> - { 0x3d4000f0, 0x0 },
> + { 0x3d4000f0, 0x2 },
> { 0x3d4000f4, 0xee5 },
> - { 0x3d400100, 0xc101b0e },
> + { 0x3d400100, 0xc100d0e },
> { 0x3d400104, 0x30314 },
> { 0x3d400108, 0x4060509 },
> { 0x3d40010c, 0x2006 },
> @@ -67,10 +67,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
> { 0x3d400498, 0x7ff },
> { 0x3d40049c, 0xe00 },
> { 0x3d4004a0, 0x7ff },
> - { 0x3d402064, 0x28003c },
> + { 0x3d402064, 0x14002c },
> { 0x3d4020dc, 0x12200004 },
> - { 0x3d4020e0, 0x0 },
> - { 0x3d402100, 0x7090b07 },
> + { 0x3d4020e0, 0x400000 },
> + { 0x3d402100, 0x7090507 },
> { 0x3d402104, 0x20209 },
> { 0x3d402108, 0x3030407 },
> { 0x3d40210c, 0x2006 },
> @@ -680,12 +680,13 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
> { 0x54006, 0x140 },
> { 0x54007, 0x1000 },
> { 0x54008, 0x101 },
> + { 0x54009, 0x200 },
> { 0x5400b, 0x31f },
> { 0x5400c, 0xc8 },
> { 0x54012, 0x1 },
> { 0x5402f, 0x1d70 },
> { 0x54030, 0x4 },
> - { 0x54031, 0x18 },
> + { 0x54031, 0x58 },
> { 0x5403a, 0x1323 },
> { 0xd0000, 0x1 },
> };
> @@ -700,11 +701,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
> { 0x54006, 0x140 },
> { 0x54007, 0x1000 },
> { 0x54008, 0x101 },
> + { 0x54009, 0x200 },
> { 0x5400b, 0x21f },
> { 0x5400c, 0xc8 },
> { 0x54012, 0x1 },
> { 0x5402f, 0x1220 },
> { 0x54030, 0x4 },
> + { 0x54031, 0x40 },
> { 0x5403a, 0x1323 },
> { 0xd0000, 0x1 },
> };
> @@ -886,11 +889,11 @@ struct dram_cfg_param ddr_phy_pie[] = {
> { 0xd00e7, 0x400 },
> { 0x90017, 0x0 },
> { 0x90026, 0x2b },
> - { 0x2000b, 0x32 },
> + { 0x2000b, 0x1c2 },
> { 0x2000c, 0x64 },
> { 0x2000d, 0x3e8 },
> { 0x2000e, 0x2c },
> - { 0x12000b, 0x14 },
> + { 0x12000b, 0xbb },
> { 0x12000c, 0x26 },
> { 0x12000d, 0x1a1 },
> { 0x12000e, 0x10 },
> --
> 2.34.1
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] board: bsh: Update imx8mn ddr3l timing according to BSH hw team
2022-08-31 12:06 ` Michael Nazzareno Trimarchi
@ 2022-08-31 12:11 ` Fabio Estevam
2022-08-31 12:13 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 4+ messages in thread
From: Fabio Estevam @ 2022-08-31 12:11 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Ariel D'Alessandro, open list, Stefano Babic, linux-amarula
Hi Michael,
On 31/08/2022 09:06, Michael Nazzareno Trimarchi wrote:
> Hi Fabio
>
> On Mon, Aug 22, 2022 at 12:14 PM Michael Trimarchi
> <michael@amarulasolutions.com> wrote:
>>
>> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
>> ---
>
> Time to review or ask for changes?
The patch looks good and I trust that the changes improve stability
of the board.
The only comment is that it is always good to include something
in the commit log to explain why the change is done.
With a commit log added:
Reviewed-by: Fabio Estevam <festevam@denx.de>
Regards,
Fabio Estevam
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-60 Fax: (+49)-8142-66989-80 Email:
festevam@denx.de
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] board: bsh: Update imx8mn ddr3l timing according to BSH hw team
2022-08-31 12:11 ` Fabio Estevam
@ 2022-08-31 12:13 ` Michael Nazzareno Trimarchi
0 siblings, 0 replies; 4+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-08-31 12:13 UTC (permalink / raw)
To: Fabio Estevam
Cc: Ariel D'Alessandro, open list, Stefano Babic, linux-amarula
Hi Fabio
On Wed, Aug 31, 2022 at 2:11 PM Fabio Estevam <festevam@denx.de> wrote:
>
> Hi Michael,
>
> On 31/08/2022 09:06, Michael Nazzareno Trimarchi wrote:
> > Hi Fabio
> >
> > On Mon, Aug 22, 2022 at 12:14 PM Michael Trimarchi
> > <michael@amarulasolutions.com> wrote:
> >>
> >> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
> >> ---
> >
> > Time to review or ask for changes?
>
> The patch looks good and I trust that the changes improve stability
> of the board.
>
> The only comment is that it is always good to include something
> in the commit log to explain why the change is done.
>
> With a commit log added:
>
> Reviewed-by: Fabio Estevam <festevam@denx.de>
>
I had the same impression after the Marek patch. I will improve the
commit message
Michael
> Regards,
>
> Fabio Estevam
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-60 Fax: (+49)-8142-66989-80 Email:
> festevam@denx.de
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-08-22 10:14 [PATCH] board: bsh: Update imx8mn ddr3l timing according to BSH hw team Michael Trimarchi
2022-08-31 12:06 ` Michael Nazzareno Trimarchi
2022-08-31 12:11 ` Fabio Estevam
2022-08-31 12:13 ` Michael Nazzareno Trimarchi
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