* [PATCH v2 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs
@ 2022-02-08 0:22 Stanley Chu
2022-02-08 0:31 ` Jesse Taube
2022-02-11 15:05 ` Simon Glass
0 siblings, 2 replies; 3+ messages in thread
From: Stanley Chu @ 2022-02-08 0:22 UTC (permalink / raw)
To: yschu, kwliu, ctcchien, avifishman70, tmaimon77, mr.bossman075,
sjg, bmeng.cn, seanga2
Cc: u-boot
This driver enables a periodic timer on NPCM SoCs and
implements the get_count timer ops.
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
Changes in v2:
calculate the prescale value, not hardcode.
---
drivers/timer/Kconfig | 6 ++
drivers/timer/Makefile | 1 +
drivers/timer/npcm-timer.c | 110 +++++++++++++++++++++++++++++++++++++
3 files changed, 117 insertions(+)
create mode 100644 drivers/timer/npcm-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..f22c46f44e 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -143,6 +143,12 @@ config NOMADIK_MTU_TIMER
The MTU provides 4 decrementing free-running timers.
At the moment, only the first timer is used by the driver.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable a timer on Nuvoton NPCM SoCs.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..39bda1ea79 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
new file mode 100644
index 0000000000..65727e41a4
--- /dev/null
+++ b/drivers/timer/npcm-timer.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define NPCM_TIMER_CLOCK_RATE 1000000UL /* 1MHz timer */
+#define NPCM_TIMER_INPUT_RATE 25000000UL /* Rate of input clock */
+#define NPCM_TIMER_TDR_MASK GENMASK(23, 0)
+#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
+
+/* Register offsets */
+#define TCR0 0x0 /* Timer Control and Status Register */
+#define TICR0 0x8 /* Timer Initial Count Register */
+#define TDR0 0x10 /* Timer Data Register */
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE - 1)
+
+/*
+ * 24-bits down-counting hw timer.
+ * last_count: last hw counter value.
+ * counter: the value to be returned for get_count ops.
+ */
+struct npcm_timer_priv {
+ void __iomem *base;
+ u32 last_count;
+ u64 counter;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ /* The timer is couting down */
+ val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
+ if (val <= priv->last_count)
+ priv->counter += priv->last_count - val;
+ else
+ priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 - val);
+ priv->last_count = val;
+
+ return priv->counter;
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+ priv->counter = 0;
+ priv->last_count = 0;
+ uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
+
+ if (IS_ENABLED(CONFIG_ARCH_NPCM750)) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /*
+ * Configure timer and start
+ * periodic mode
+ * input clock freq = 25Mhz
+ * timer clock rate = input clock / prescale
+ */
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
+ priv->base + TCR0);
+
+ return 0;
+}
+
+static const struct timer_ops npcm_timer_ops = {
+ .get_count = npcm_timer_get_count,
+};
+
+static const struct udevice_id npcm_timer_ids[] = {
+ { .compatible = "nuvoton,npcm845-timer" },
+ { .compatible = "nuvoton,npcm750-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(npcm_timer) = {
+ .name = "npcm_timer",
+ .id = UCLASS_TIMER,
+ .of_match = npcm_timer_ids,
+ .priv_auto = sizeof(struct npcm_timer_priv),
+ .probe = npcm_timer_probe,
+ .ops = &npcm_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs
2022-02-08 0:22 [PATCH v2 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs Stanley Chu
@ 2022-02-08 0:31 ` Jesse Taube
2022-02-11 15:05 ` Simon Glass
1 sibling, 0 replies; 3+ messages in thread
From: Jesse Taube @ 2022-02-08 0:31 UTC (permalink / raw)
To: Stanley Chu, yschu, kwliu, ctcchien, avifishman70, tmaimon77,
sjg, bmeng.cn, seanga2
Cc: u-boot
On 2/7/22 19:22, Stanley Chu wrote:
> This driver enables a periodic timer on NPCM SoCs and
> implements the get_count timer ops.
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---
> Changes in v2:
> calculate the prescale value, not hardcode.I would have waited to see what maintainers say. They usually take
longer about 2 days. You also may want to find other people more
relevant to this patch. Do you have an online presence like linkedin,
github etc?
Thanks,
Jesse Taube
> ---
> drivers/timer/Kconfig | 6 ++
> drivers/timer/Makefile | 1 +
> drivers/timer/npcm-timer.c | 110 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 117 insertions(+)
> create mode 100644 drivers/timer/npcm-timer.c
>
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> index 8913142654..f22c46f44e 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -143,6 +143,12 @@ config NOMADIK_MTU_TIMER
> The MTU provides 4 decrementing free-running timers.
> At the moment, only the first timer is used by the driver.
>
> +config NPCM_TIMER
> + bool "Nuvoton NPCM timer support"
> + depends on TIMER
> + help
> + Select this to enable a timer on Nuvoton NPCM SoCs.
> +
> config OMAP_TIMER
> bool "Omap timer support"
> depends on TIMER
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
> index e2bd530eb0..39bda1ea79 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
> obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
> obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
> obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o
> +obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
> obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
> obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
> obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
> diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
> new file mode 100644
> index 0000000000..65727e41a4
> --- /dev/null
> +++ b/drivers/timer/npcm-timer.c
> @@ -0,0 +1,110 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2022 Nuvoton Technology Corp.
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <timer.h>
> +#include <asm/io.h>
> +
> +#define NPCM_TIMER_CLOCK_RATE 1000000UL /* 1MHz timer */
> +#define NPCM_TIMER_INPUT_RATE 25000000UL /* Rate of input clock */
> +#define NPCM_TIMER_TDR_MASK GENMASK(23, 0)
> +#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
> +
> +/* Register offsets */
> +#define TCR0 0x0 /* Timer Control and Status Register */
> +#define TICR0 0x8 /* Timer Initial Count Register */
> +#define TDR0 0x10 /* Timer Data Register */
> +
> +/* TCR fields */
> +#define TCR_MODE_PERIODIC BIT(27)
> +#define TCR_EN BIT(30)
> +#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE - 1)
> +
> +/*
> + * 24-bits down-counting hw timer.
> + * last_count: last hw counter value.
> + * counter: the value to be returned for get_count ops.
> + */
> +struct npcm_timer_priv {
> + void __iomem *base;
> + u32 last_count;
> + u64 counter;
> +};
> +
> +static u64 npcm_timer_get_count(struct udevice *dev)
> +{
> + struct npcm_timer_priv *priv = dev_get_priv(dev);
> + u32 val;
> +
> + /* The timer is couting down */
> + val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
> + if (val <= priv->last_count)
> + priv->counter += priv->last_count - val;
> + else
> + priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 - val);
> + priv->last_count = val;
> +
> + return priv->counter;
> +}
> +
> +static int npcm_timer_probe(struct udevice *dev)
> +{
> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> + struct npcm_timer_priv *priv = dev_get_priv(dev);
> + struct clk clk;
> + int ret;
> +
> + priv->base = dev_read_addr_ptr(dev);
> + if (!priv->base)
> + return -ENOENT;
> + priv->counter = 0;
> + priv->last_count = 0;
> + uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
> +
> + if (IS_ENABLED(CONFIG_ARCH_NPCM750)) {
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /*
> + * Configure timer and start
> + * periodic mode
> + * input clock freq = 25Mhz
> + * timer clock rate = input clock / prescale
> + */
> + writel(0, priv->base + TCR0);
> + writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
> + writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
> + priv->base + TCR0);
> +
> + return 0;
> +}
> +
> +static const struct timer_ops npcm_timer_ops = {
> + .get_count = npcm_timer_get_count,
> +};
> +
> +static const struct udevice_id npcm_timer_ids[] = {
> + { .compatible = "nuvoton,npcm845-timer" },
> + { .compatible = "nuvoton,npcm750-timer" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(npcm_timer) = {
> + .name = "npcm_timer",
> + .id = UCLASS_TIMER,
> + .of_match = npcm_timer_ids,
> + .priv_auto = sizeof(struct npcm_timer_priv),
> + .probe = npcm_timer_probe,
> + .ops = &npcm_timer_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs
2022-02-08 0:22 [PATCH v2 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs Stanley Chu
2022-02-08 0:31 ` Jesse Taube
@ 2022-02-11 15:05 ` Simon Glass
1 sibling, 0 replies; 3+ messages in thread
From: Simon Glass @ 2022-02-11 15:05 UTC (permalink / raw)
To: Stanley Chu
Cc: yschu, Joseph Liu, ctcchien, avifishman70, tmaimon77,
Jesse Taube, Bin Meng, Sean Anderson, U-Boot Mailing List
Hi Stanley,
On Mon, 7 Feb 2022 at 17:22, Stanley Chu <stanley.chuys@gmail.com> wrote:
>
> This driver enables a periodic timer on NPCM SoCs and
> implements the get_count timer ops.
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---
> Changes in v2:
> calculate the prescale value, not hardcode.
> ---
> drivers/timer/Kconfig | 6 ++
> drivers/timer/Makefile | 1 +
> drivers/timer/npcm-timer.c | 110 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 117 insertions(+)
> create mode 100644 drivers/timer/npcm-timer.c
>
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> index 8913142654..f22c46f44e 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -143,6 +143,12 @@ config NOMADIK_MTU_TIMER
> The MTU provides 4 decrementing free-running timers.
> At the moment, only the first timer is used by the driver.
>
> +config NPCM_TIMER
> + bool "Nuvoton NPCM timer support"
> + depends on TIMER
> + help
> + Select this to enable a timer on Nuvoton NPCM SoCs.
Please add proper help, e.g. how many channels and whether it supports
early timer and boot timer.
> +
> config OMAP_TIMER
> bool "Omap timer support"
> depends on TIMER
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
> index e2bd530eb0..39bda1ea79 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
> obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
> obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
> obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o
> +obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
> obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
> obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
> obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
> diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
> new file mode 100644
> index 0000000000..65727e41a4
> --- /dev/null
> +++ b/drivers/timer/npcm-timer.c
> @@ -0,0 +1,110 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2022 Nuvoton Technology Corp.
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <timer.h>
> +#include <asm/io.h>
> +
> +#define NPCM_TIMER_CLOCK_RATE 1000000UL /* 1MHz timer */
> +#define NPCM_TIMER_INPUT_RATE 25000000UL /* Rate of input clock */
> +#define NPCM_TIMER_TDR_MASK GENMASK(23, 0)
> +#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
> +
> +/* Register offsets */
> +#define TCR0 0x0 /* Timer Control and Status Register */
> +#define TICR0 0x8 /* Timer Initial Count Register */
> +#define TDR0 0x10 /* Timer Data Register */
> +
> +/* TCR fields */
> +#define TCR_MODE_PERIODIC BIT(27)
> +#define TCR_EN BIT(30)
> +#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE - 1)
> +
> +/*
insert the /** tag to make this work:
/** struct npcm_timer_priv
*
> + * 24-bits down-counting hw timer.
> + * last_count: last hw counter value.
> + * counter: the value to be returned for get_count ops.
> + */
> +struct npcm_timer_priv {
> + void __iomem *base;
> + u32 last_count;
> + u64 counter;
> +};
> +
> +static u64 npcm_timer_get_count(struct udevice *dev)
> +{
> + struct npcm_timer_priv *priv = dev_get_priv(dev);
> + u32 val;
> +
> + /* The timer is couting down */
counting
> + val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
> + if (val <= priv->last_count)
> + priv->counter += priv->last_count - val;
> + else
> + priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 - val);
> + priv->last_count = val;
> +
> + return priv->counter;
> +}
> +
> +static int npcm_timer_probe(struct udevice *dev)
> +{
> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> + struct npcm_timer_priv *priv = dev_get_priv(dev);
> + struct clk clk;
> + int ret;
> +
> + priv->base = dev_read_addr_ptr(dev);
> + if (!priv->base)
> + return -ENOENT;
-EINVAL I think?
> + priv->counter = 0;
> + priv->last_count = 0;
priv fields are already zeroed by driver model.
> + uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
> +
> + if (IS_ENABLED(CONFIG_ARCH_NPCM750)) {
Should use a compatible string to handle different devices.
Or maybe you can use CONFIG_IS_ENABLED(CLK) ?
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /*
> + * Configure timer and start
> + * periodic mode
> + * input clock freq = 25Mhz
> + * timer clock rate = input clock / prescale
> + */
> + writel(0, priv->base + TCR0);
> + writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
> + writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
> + priv->base + TCR0);
> +
> + return 0;
> +}
> +
> +static const struct timer_ops npcm_timer_ops = {
> + .get_count = npcm_timer_get_count,
> +};
> +
> +static const struct udevice_id npcm_timer_ids[] = {
> + { .compatible = "nuvoton,npcm845-timer" },
> + { .compatible = "nuvoton,npcm750-timer" },
Here you add a .data parameter for each (using an enum you device)
which you can read with dev_get_driver_data() and you can use that
above with your clock problem.
> + {}
> +};
> +
> +U_BOOT_DRIVER(npcm_timer) = {
> + .name = "npcm_timer",
> + .id = UCLASS_TIMER,
> + .of_match = npcm_timer_ids,
> + .priv_auto = sizeof(struct npcm_timer_priv),
> + .probe = npcm_timer_probe,
> + .ops = &npcm_timer_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> --
> 2.17.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-02-08 0:22 [PATCH v2 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs Stanley Chu
2022-02-08 0:31 ` Jesse Taube
2022-02-11 15:05 ` Simon Glass
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