* Re: [PATCH] clk: versal: Enable only GATE type clocks
[not found] <20210927081110.10528-1-ashok.reddy.soma@xilinx.com>
@ 2021-09-27 8:22 ` Michal Simek
0 siblings, 0 replies; 3+ messages in thread
From: Michal Simek @ 2021-09-27 8:22 UTC (permalink / raw)
To: Ashok Reddy Soma, u-boot
Cc: lukma, michal.simek, git, somaashokreddy, T Karthik Reddy
On 9/27/21 10:11 AM, Ashok Reddy Soma wrote:
> From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
>
> Clocks should be enabled or disabled only if they are of GATE type
> clocks. If they are not of GATE type clocks, don't touch them.
>
> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
> ---
>
> drivers/clk/clk_versal.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
> index 62523d2909..a9dd57b098 100644
> --- a/drivers/clk/clk_versal.c
> +++ b/drivers/clk/clk_versal.c
> @@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
>
> clk_id = priv->clk[clk->id].clk_id;
>
> - return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
> + if (versal_clock_gate(clk_id))
> + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
> +
> + return 0;
> }
>
> static struct clk_ops versal_clk_ops = {
>
CR?
M
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: versal: Enable only GATE type clocks
2021-09-28 6:00 Ashok Reddy Soma
@ 2021-09-29 13:28 ` Michal Simek
0 siblings, 0 replies; 3+ messages in thread
From: Michal Simek @ 2021-09-29 13:28 UTC (permalink / raw)
To: Ashok Reddy Soma, u-boot
Cc: lukma, michal.simek, git, somaashokreddy, T Karthik Reddy
On 9/28/21 8:00 AM, Ashok Reddy Soma wrote:
> From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
>
> Clocks should be enabled or disabled only if they are of GATE type
> clocks. If they are not of GATE type clocks, don't touch them.
>
> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
> ---
>
> drivers/clk/clk_versal.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
> index 62523d2909..a9dd57b098 100644
> --- a/drivers/clk/clk_versal.c
> +++ b/drivers/clk/clk_versal.c
> @@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
>
> clk_id = priv->clk[clk->id].clk_id;
>
> - return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
> + if (versal_clock_gate(clk_id))
> + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
> +
> + return 0;
> }
>
> static struct clk_ops versal_clk_ops = {
>
Applied.
M
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] clk: versal: Enable only GATE type clocks
@ 2021-09-28 6:00 Ashok Reddy Soma
2021-09-29 13:28 ` Michal Simek
0 siblings, 1 reply; 3+ messages in thread
From: Ashok Reddy Soma @ 2021-09-28 6:00 UTC (permalink / raw)
To: u-boot
Cc: lukma, michal.simek, git, somaashokreddy, T Karthik Reddy,
Ashok Reddy Soma
From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Clocks should be enabled or disabled only if they are of GATE type
clocks. If they are not of GATE type clocks, don't touch them.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
---
drivers/clk/clk_versal.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 62523d2909..a9dd57b098 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
clk_id = priv->clk[clk->id].clk_id;
- return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+ if (versal_clock_gate(clk_id))
+ return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+
+ return 0;
}
static struct clk_ops versal_clk_ops = {
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
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[not found] <20210927081110.10528-1-ashok.reddy.soma@xilinx.com>
2021-09-27 8:22 ` [PATCH] clk: versal: Enable only GATE type clocks Michal Simek
2021-09-28 6:00 Ashok Reddy Soma
2021-09-29 13:28 ` Michal Simek
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