From: Julien Grall <julien.grall@arm.com>
To: xen-devel@lists.xen.org
Cc: Julien Grall <julien.grall@arm.com>,
sstabellini@kernel.org, shankerd@codeaurora.org,
steve.capper@arm.com
Subject: [PATCH v2 1/9] xen/arm: gic: Consolidate the IRQ affinity set in a single place
Date: Thu, 14 Jul 2016 17:21:57 +0100 [thread overview]
Message-ID: <1468513325-29492-2-git-send-email-julien.grall@arm.com> (raw)
In-Reply-To: <1468513325-29492-1-git-send-email-julien.grall@arm.com>
The code to set the IRQ affinity is duplicated: once in
gicv{2,3}_set_properties and the other is gicv{2,3}_irq_set_affinity.
Remove the code from gicv{2,3}_set_properties and call directly the
affinity set helper from the common code.
Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
Changes in v2:
- Add Stefano's reviewed-by
---
xen/arch/arm/gic-v2.c | 10 +---------
xen/arch/arm/gic-v3.c | 10 ----------
xen/arch/arm/gic.c | 3 ++-
xen/include/asm-arm/gic.h | 1 -
4 files changed, 3 insertions(+), 21 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 3893ece..6c7dbfe 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -236,16 +236,10 @@ static unsigned int gicv2_read_irq(void)
return (readl_gicc(GICC_IAR) & GICC_IA_IRQ);
}
-/*
- * needs to be called with a valid cpu_mask, ie each cpu in the mask has
- * already called gic_cpu_init
- */
static void gicv2_set_irq_properties(struct irq_desc *desc,
- const cpumask_t *cpu_mask,
- unsigned int priority)
+ unsigned int priority)
{
uint32_t cfg, actual, edgebit;
- unsigned int mask = gicv2_cpu_mask(cpu_mask);
unsigned int irq = desc->irq;
unsigned int type = desc->arch.type;
@@ -276,8 +270,6 @@ static void gicv2_set_irq_properties(struct irq_desc *desc,
IRQ_TYPE_LEVEL_HIGH;
}
- /* Set target CPU mask (RAZ/WI on uniprocessor) */
- writeb_gicd(mask, GICD_ITARGETSR + irq);
/* Set priority */
writeb_gicd(priority, GICD_IPRIORITYR + irq);
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index cbda066..d6ab0e9 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -472,13 +472,10 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
}
static void gicv3_set_irq_properties(struct irq_desc *desc,
- const cpumask_t *cpu_mask,
unsigned int priority)
{
uint32_t cfg, actual, edgebit;
- uint64_t affinity;
void __iomem *base;
- unsigned int cpu = gicv3_get_cpu_from_mask(cpu_mask);
unsigned int irq = desc->irq;
unsigned int type = desc->arch.type;
@@ -516,13 +513,6 @@ static void gicv3_set_irq_properties(struct irq_desc *desc,
IRQ_TYPE_LEVEL_HIGH;
}
- affinity = gicv3_mpidr_to_affinity(cpu);
- /* Make sure we don't broadcast the interrupt */
- affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
-
- if ( irq >= NR_GIC_LOCAL_IRQS )
- writeq_relaxed(affinity, (GICD + GICD_IROUTER + irq * 8));
-
/* Set priority */
if ( irq < NR_GIC_LOCAL_IRQS )
writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irq);
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 12bb0ab..5726a05 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -106,7 +106,8 @@ static void gic_set_irq_properties(struct irq_desc *desc,
const cpumask_t *cpu_mask,
unsigned int priority)
{
- gic_hw_ops->set_irq_properties(desc, cpu_mask, priority);
+ gic_hw_ops->set_irq_properties(desc, priority);
+ desc->handler->set_affinity(desc, cpu_mask);
}
/* Program the GIC to route an interrupt to the host (i.e. Xen)
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index b073c53..2fc6126 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -331,7 +331,6 @@ struct gic_hw_operations {
unsigned int (*read_irq)(void);
/* Set IRQ property */
void (*set_irq_properties)(struct irq_desc *desc,
- const cpumask_t *cpu_mask,
unsigned int priority);
/* Send SGI */
void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
--
1.9.1
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next prev parent reply other threads:[~2016-07-14 16:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-14 16:21 [PATCH v2 0/9] xen/arm: Support SPIs routing Julien Grall
2016-07-14 16:21 ` Julien Grall [this message]
2016-07-14 16:21 ` [PATCH v2 2/9] xen/arm: gic: Do not configure affinity during routing Julien Grall
2016-07-19 23:08 ` Stefano Stabellini
2016-07-14 16:21 ` [PATCH v2 3/9] xen/arm: gic: split set_irq_properties Julien Grall
2016-07-14 16:22 ` [PATCH v2 4/9] xen/arm: gic: set_type: Pass the type in parameter rather than in desc->arch.type Julien Grall
2016-07-19 23:11 ` Stefano Stabellini
2016-07-14 16:22 ` [PATCH v2 5/9] xen/arm: gic: Document how gic_set_irq_type should be called Julien Grall
2016-07-14 16:22 ` [PATCH v2 6/9] Revert "xen/arm: warn the user that we cannot route SPIs to Dom0 on ACPI" Julien Grall
2016-07-14 16:24 ` Julien Grall
2016-07-14 16:22 ` [PATCH v2 7/9] xen/arm: Allow DOM0 to set the IRQ type Julien Grall
2016-07-19 23:43 ` Stefano Stabellini
2016-07-20 8:38 ` Julien Grall
2016-07-20 17:20 ` Stefano Stabellini
2016-07-14 16:22 ` [PATCH v2 8/9] xen/arm: acpi: route all unused IRQs to DOM0 Julien Grall
2016-07-19 23:49 ` Stefano Stabellini
2016-07-14 16:22 ` [PATCH v2 9/9] xen/arm: Fix coding style and update comment in acpi_route_spis Julien Grall
2016-07-19 23:46 ` Stefano Stabellini
2016-07-14 18:17 ` [PATCH v2 0/9] xen/arm: Support SPIs routing Shanker Donthineni
2016-07-27 13:30 ` Julien Grall
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