[for-4.7 v2 0/5] xen/arm: acpi: Bunch of fixes to use ACPI with SMP and PL011

[for-4.7 v2 0/5] xen/arm: acpi: Bunch of fixes to use ACPI with SMP and PL011

[Julien Grall]

Hello,

This patch series fixes secondary CPUs bring up and the use of the PL011 UART
driver when Xen boots using ACPI.

For all the changes see in each patch.

Regards,

Cc: wei.liu2@citrix.com

Julien Grall (5):
  drivers/pl011: ACPI: The interrupt should always be high level
    triggered
  xen/arm: acpi: The boot CPU does not always match the first entry in
    the MADT
  xen/arm: acpi: Fix SMP support when booting with ACPI
  xen/arm: acpi: Remove uncessary check in acpi_map_gic_cpu_interface
  xen/arm: acpi: Print more error messages in acpi_map_gic_cpu_interface

 xen/arch/arm/acpi/boot.c | 40 +++++++++++++++++++++++++++-------------
 xen/drivers/char/pl011.c |  2 +-
 2 files changed, 28 insertions(+), 14 deletions(-)

-- 
1.9.1


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[for-4.7 v2 1/5] drivers/pl011: ACPI: The interrupt should always be high level triggered

[Julien Grall]

The SPCR does not specify if the interrupt is edge or level triggered.
So the configuration needs to be hardcoded in the code.

Based on the PL011 TRM (see 2.2.8 in ARM DDI 0183G), the interrupt generated
will be active high. Whilst the wording may be interpreted differently,
the SBSA (section 4.3.2 in ARM-DEN-0029 v2.3) states the PL011 is
implemented with a level triggered interrupt.

So the driver should configure the interrupt as high level triggered.

Signed-off-by: Julien Grall <julien.grall@arm.com>

---
    Changes in v2:
        - Update the commit message
        - Effictively configure the interrupt high level triggered
---
 xen/drivers/char/pl011.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index fa22edf..1212d5c 100644
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -327,7 +327,7 @@ static int __init pl011_acpi_uart_init(const void *data)
     }
 
     /* trigger/polarity information is not available in spcr */
-    irq_set_type(spcr->interrupt, IRQ_TYPE_EDGE_BOTH);
+    irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH);
 
     res = pl011_uart_init(spcr->interrupt, spcr->serial_port.address,
                           PAGE_SIZE);
-- 
1.9.1


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[for-4.7 v2 2/5] xen/arm: acpi: The boot CPU does not always match the first entry in the MADT

[Julien Grall]

Since the ACPI 6.0 errata document [1], the first entry in the MADT
does not have to correspond to the boot CPU.

Introduce a new variable to know if a MADT entry matching the boot CPU
is found. Furthermore, it's not necessary to check if the MPIDR is
duplicated for the boot CPU. So the rest of the function can be skipped.

[1] 1380 Unnecessary restrictions to FW vendors in ordering of GIC structures
in MADT

Signed-off-by: Julien Grall <julien.grall@arm.com>

---
    Changes in v2:
        - Modify the loop to start to 1 and not 0
---
 xen/arch/arm/acpi/boot.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/xen/arch/arm/acpi/boot.c b/xen/arch/arm/acpi/boot.c
index 859aa86..1bba1cf 100644
--- a/xen/arch/arm/acpi/boot.c
+++ b/xen/arch/arm/acpi/boot.c
@@ -37,7 +37,8 @@
 #include <asm/setup.h>
 
 /* Processors with enabled flag and sane MPIDR */
-static unsigned int enabled_cpus;
+static unsigned int enabled_cpus = 1;
+static bool __initdata bootcpu_valid;
 
 /* total number of cpus in this system */
 static unsigned int __initdata total_cpus;
@@ -71,10 +72,15 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
     }
 
     /* Check if GICC structure of boot CPU is available in the MADT */
-    if ( (enabled_cpus == 0) && (cpu_logical_map(0) != mpidr) )
+    if ( cpu_logical_map(0) == mpidr )
     {
-        printk("Firmware bug, invalid CPU MPIDR for cpu0: 0x%"PRIx64" in MADT\n",
-               mpidr);
+        if ( bootcpu_valid )
+        {
+            printk("Firmware bug, duplicate boot CPU MPIDR: 0x%"PRIx64" in MADT\n",
+                   mpidr);
+            return;
+        }
+        bootcpu_valid = true;
         return;
     }
 
@@ -83,7 +89,7 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
      * all initialized entries and check for
      * duplicates. If any is found just ignore the CPU.
      */
-    for ( i = 0; i < enabled_cpus; i++ )
+    for ( i = 1; i < enabled_cpus; i++ )
     {
         if ( cpu_logical_map(i) == mpidr )
         {
-- 
1.9.1


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[for-4.7 v2 3/5] xen/arm: acpi: Fix SMP support when booting with ACPI

[Julien Grall]

The variable enabled_cpus is used to know the number of CPU enabled in
the MADT.

Currently this variable is used to check the validity of the boot CPU.
It will be considered invalid when "enabled_cpus > 1".

However, this condition also means that multiple CPUs are present on the
system. So secondary will never be brought up.

The correct way to check the validity of the boot CPU is to use the
variable bootcpu_valid.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

---
    Changes in v2:
        - Add Stefano's and Shannon's reviewed-by
---
 xen/arch/arm/acpi/boot.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/acpi/boot.c b/xen/arch/arm/acpi/boot.c
index 1bba1cf..a952efd 100644
--- a/xen/arch/arm/acpi/boot.c
+++ b/xen/arch/arm/acpi/boot.c
@@ -149,7 +149,7 @@ void __init acpi_smp_init_cpus(void)
         return;
     }
 
-    if ( enabled_cpus > 1 )
+    if ( !bootcpu_valid )
     {
         printk("MADT missing boot CPU MPIDR, not enabling secondaries\n");
         return;
-- 
1.9.1


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[for-4.7 v2 4/5] xen/arm: acpi: Remove uncessary check in acpi_map_gic_cpu_interface

[Julien Grall]

This part of the code will never be executed when the entry
corresponds to the boot CPU.

Also print an error message rather when arch_cpu_init has failed.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

---
    Changes in v2:
        - Add Stefano's and Shannon's reviewed-by
---
 xen/arch/arm/acpi/boot.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/xen/arch/arm/acpi/boot.c b/xen/arch/arm/acpi/boot.c
index a952efd..f3d8e7c 100644
--- a/xen/arch/arm/acpi/boot.c
+++ b/xen/arch/arm/acpi/boot.c
@@ -51,6 +51,7 @@ static void __init
 acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
 {
     int i;
+    int rc;
     u64 mpidr = processor->arm_mpidr & MPIDR_HWID_MASK;
     bool_t enabled = !!(processor->flags & ACPI_MADT_ENABLED);
 
@@ -102,16 +103,16 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
     if ( !acpi_psci_present() )
         return;
 
-    /* CPU 0 was already initialized */
-    if ( enabled_cpus )
+    if ( (rc = arch_cpu_init(enabled_cpus, NULL)) < 0 )
     {
-        if ( arch_cpu_init(enabled_cpus, NULL) < 0 )
-            return;
-
-        /* map the logical cpu id to cpu MPIDR */
-        cpu_logical_map(enabled_cpus) = mpidr;
+        printk("cpu%d: init failed (0x%"PRIx64" MPIDR): %d\n",
+               enabled_cpus, mpidr, rc);
+        return;
     }
 
+    /* map the logical cpu id to cpu MPIDR */
+    cpu_logical_map(enabled_cpus) = mpidr;
+
     enabled_cpus++;
 }
 
-- 
1.9.1


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[for-4.7 v2 5/5] xen/arm: acpi: Print more error messages in acpi_map_gic_cpu_interface

[Julien Grall]

It's helpful to spot any error without having to modify the hypervisor
code.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

---
    Changes in v2:
        - Add Stefano's and Shannon's reviewed-by
---
 xen/arch/arm/acpi/boot.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/xen/arch/arm/acpi/boot.c b/xen/arch/arm/acpi/boot.c
index f3d8e7c..28b3450 100644
--- a/xen/arch/arm/acpi/boot.c
+++ b/xen/arch/arm/acpi/boot.c
@@ -63,7 +63,10 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
 
     total_cpus++;
     if ( !enabled )
+    {
+        printk("Skipping disabled CPU entry with 0x%"PRIx64" MPIDR\n", mpidr);
         return;
+    }
 
     if ( enabled_cpus >=  NR_CPUS )
     {
@@ -101,7 +104,11 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
     }
 
     if ( !acpi_psci_present() )
+    {
+        printk("PSCI not present, skipping CPU MPIDR 0x%"PRIx64"\n",
+               mpidr);
         return;
+    }
 
     if ( (rc = arch_cpu_init(enabled_cpus, NULL)) < 0 )
     {
-- 
1.9.1


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Re: [for-4.7 v2 0/5] xen/arm: acpi: Bunch of fixes to use ACPI with SMP and PL011

[Wei Liu]

On Mon, Apr 11, 2016 at 02:33:32PM +0100, Julien Grall wrote:
> Hello,
> 
> This patch series fixes secondary CPUs bring up and the use of the PL011 UART
> driver when Xen boots using ACPI.
> 
> For all the changes see in each patch.
> 
> Regards,
> 
> Cc: wei.liu2@citrix.com
> 
> Julien Grall (5):
>   drivers/pl011: ACPI: The interrupt should always be high level
>     triggered
>   xen/arm: acpi: The boot CPU does not always match the first entry in
>     the MADT
>   xen/arm: acpi: Fix SMP support when booting with ACPI
>   xen/arm: acpi: Remove uncessary check in acpi_map_gic_cpu_interface
>   xen/arm: acpi: Print more error messages in acpi_map_gic_cpu_interface
> 
>  xen/arch/arm/acpi/boot.c | 40 +++++++++++++++++++++++++++-------------
>  xen/drivers/char/pl011.c |  2 +-
>  2 files changed, 28 insertions(+), 14 deletions(-)
> 

Release-acked-by: Wei Liu <wei.liu2@citrix.com>


> -- 
> 1.9.1
> 

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Re: [for-4.7 v2 1/5] drivers/pl011: ACPI: The interrupt should always be high level triggered

[Konrad Rzeszutek Wilk]

On Mon, Apr 11, 2016 at 02:33:33PM +0100, Julien Grall wrote:
> The SPCR does not specify if the interrupt is edge or level triggered.
> So the configuration needs to be hardcoded in the code.
> 
> Based on the PL011 TRM (see 2.2.8 in ARM DDI 0183G), the interrupt generated
> will be active high. Whilst the wording may be interpreted differently,
> the SBSA (section 4.3.2 in ARM-DEN-0029 v2.3) states the PL011 is
> implemented with a level triggered interrupt.
> 
> So the driver should configure the interrupt as high level triggered.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>

Shannon, Stefano,

Please reply whether you are OK with this patch. Thanks!
> 
> ---
>     Changes in v2:
>         - Update the commit message
>         - Effictively configure the interrupt high level triggered
> ---
>  xen/drivers/char/pl011.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
> index fa22edf..1212d5c 100644
> --- a/xen/drivers/char/pl011.c
> +++ b/xen/drivers/char/pl011.c
> @@ -327,7 +327,7 @@ static int __init pl011_acpi_uart_init(const void *data)
>      }
>  
>      /* trigger/polarity information is not available in spcr */
> -    irq_set_type(spcr->interrupt, IRQ_TYPE_EDGE_BOTH);
> +    irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH);
>  
>      res = pl011_uart_init(spcr->interrupt, spcr->serial_port.address,
>                            PAGE_SIZE);
> -- 
> 1.9.1
> 
> 
> _______________________________________________
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> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel

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Re: [for-4.7 v2 2/5] xen/arm: acpi: The boot CPU does not always match the first entry in the MADT

[Konrad Rzeszutek Wilk]

On Mon, Apr 11, 2016 at 02:33:34PM +0100, Julien Grall wrote:
> Since the ACPI 6.0 errata document [1], the first entry in the MADT
> does not have to correspond to the boot CPU.
> 
> Introduce a new variable to know if a MADT entry matching the boot CPU
> is found. Furthermore, it's not necessary to check if the MPIDR is
> duplicated for the boot CPU. So the rest of the function can be skipped.
> 
> [1] 1380 Unnecessary restrictions to FW vendors in ordering of GIC structures
> in MADT
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>

Applied.

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Re: [for-4.7 v2 3/5] xen/arm: acpi: Fix SMP support when booting with ACPI

[Konrad Rzeszutek Wilk]

On Mon, Apr 11, 2016 at 02:33:35PM +0100, Julien Grall wrote:
> The variable enabled_cpus is used to know the number of CPU enabled in
> the MADT.
> 
> Currently this variable is used to check the validity of the boot CPU.
> It will be considered invalid when "enabled_cpus > 1".
> 
> However, this condition also means that multiple CPUs are present on the
> system. So secondary will never be brought up.
> 
> The correct way to check the validity of the boot CPU is to use the
> variable bootcpu_valid.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

Applied.

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Re: [for-4.7 v2 4/5] xen/arm: acpi: Remove uncessary check in acpi_map_gic_cpu_interface

[Konrad Rzeszutek Wilk]

On Mon, Apr 11, 2016 at 02:33:36PM +0100, Julien Grall wrote:
> This part of the code will never be executed when the entry
> corresponds to the boot CPU.
> 
> Also print an error message rather when arch_cpu_init has failed.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

Applied.

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Re: [for-4.7 v2 5/5] xen/arm: acpi: Print more error messages in acpi_map_gic_cpu_interface

[Konrad Rzeszutek Wilk]

On Mon, Apr 11, 2016 at 02:33:37PM +0100, Julien Grall wrote:
> It's helpful to spot any error without having to modify the hypervisor
> code.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

Applied.

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Re: [for-4.7 v2 2/5] xen/arm: acpi: The boot CPU does not always match the first entry in the MADT

[Stefano Stabellini]

On Mon, 11 Apr 2016, Julien Grall wrote:
> Since the ACPI 6.0 errata document [1], the first entry in the MADT
> does not have to correspond to the boot CPU.
> 
> Introduce a new variable to know if a MADT entry matching the boot CPU
> is found. Furthermore, it's not necessary to check if the MPIDR is
> duplicated for the boot CPU. So the rest of the function can be skipped.
> 
> [1] 1380 Unnecessary restrictions to FW vendors in ordering of GIC structures
> in MADT
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>

Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>


> ---
>     Changes in v2:
>         - Modify the loop to start to 1 and not 0
> ---
>  xen/arch/arm/acpi/boot.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/xen/arch/arm/acpi/boot.c b/xen/arch/arm/acpi/boot.c
> index 859aa86..1bba1cf 100644
> --- a/xen/arch/arm/acpi/boot.c
> +++ b/xen/arch/arm/acpi/boot.c
> @@ -37,7 +37,8 @@
>  #include <asm/setup.h>
>  
>  /* Processors with enabled flag and sane MPIDR */
> -static unsigned int enabled_cpus;
> +static unsigned int enabled_cpus = 1;
> +static bool __initdata bootcpu_valid;
>  
>  /* total number of cpus in this system */
>  static unsigned int __initdata total_cpus;
> @@ -71,10 +72,15 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
>      }
>  
>      /* Check if GICC structure of boot CPU is available in the MADT */
> -    if ( (enabled_cpus == 0) && (cpu_logical_map(0) != mpidr) )
> +    if ( cpu_logical_map(0) == mpidr )
>      {
> -        printk("Firmware bug, invalid CPU MPIDR for cpu0: 0x%"PRIx64" in MADT\n",
> -               mpidr);
> +        if ( bootcpu_valid )
> +        {
> +            printk("Firmware bug, duplicate boot CPU MPIDR: 0x%"PRIx64" in MADT\n",
> +                   mpidr);
> +            return;
> +        }
> +        bootcpu_valid = true;
>          return;
>      }
>  
> @@ -83,7 +89,7 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
>       * all initialized entries and check for
>       * duplicates. If any is found just ignore the CPU.
>       */
> -    for ( i = 0; i < enabled_cpus; i++ )
> +    for ( i = 1; i < enabled_cpus; i++ )
>      {
>          if ( cpu_logical_map(i) == mpidr )
>          {
> -- 
> 1.9.1
> 

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Re: [for-4.7 v2 1/5] drivers/pl011: ACPI: The interrupt should always be high level triggered

[Stefano Stabellini]

On Mon, 11 Apr 2016, Konrad Rzeszutek Wilk wrote:
> On Mon, Apr 11, 2016 at 02:33:33PM +0100, Julien Grall wrote:
> > The SPCR does not specify if the interrupt is edge or level triggered.
> > So the configuration needs to be hardcoded in the code.
> > 
> > Based on the PL011 TRM (see 2.2.8 in ARM DDI 0183G), the interrupt generated
> > will be active high. Whilst the wording may be interpreted differently,
> > the SBSA (section 4.3.2 in ARM-DEN-0029 v2.3) states the PL011 is
> > implemented with a level triggered interrupt.
> > 
> > So the driver should configure the interrupt as high level triggered.
> > 
> > Signed-off-by: Julien Grall <julien.grall@arm.com>
> 
> Shannon, Stefano,
> 
> Please reply whether you are OK with this patch. Thanks!

Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>


> > ---
> >     Changes in v2:
> >         - Update the commit message
> >         - Effictively configure the interrupt high level triggered
> > ---
> >  xen/drivers/char/pl011.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
> > index fa22edf..1212d5c 100644
> > --- a/xen/drivers/char/pl011.c
> > +++ b/xen/drivers/char/pl011.c
> > @@ -327,7 +327,7 @@ static int __init pl011_acpi_uart_init(const void *data)
> >      }
> >  
> >      /* trigger/polarity information is not available in spcr */
> > -    irq_set_type(spcr->interrupt, IRQ_TYPE_EDGE_BOTH);
> > +    irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH);
> >  
> >      res = pl011_uart_init(spcr->interrupt, spcr->serial_port.address,
> >                            PAGE_SIZE);
> > -- 
> > 1.9.1
> > 
> > 
> > _______________________________________________
> > Xen-devel mailing list
> > Xen-devel@lists.xen.org
> > http://lists.xen.org/xen-devel
> 

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Re: [for-4.7 v2 1/5] drivers/pl011: ACPI: The interrupt should always be high level triggered

[Shannon Zhao]

On 2016/4/11 22:07, Konrad Rzeszutek Wilk wrote:
> On Mon, Apr 11, 2016 at 02:33:33PM +0100, Julien Grall wrote:
>> The SPCR does not specify if the interrupt is edge or level triggered.
>> So the configuration needs to be hardcoded in the code.
>>
>> Based on the PL011 TRM (see 2.2.8 in ARM DDI 0183G), the interrupt generated
>> will be active high. Whilst the wording may be interpreted differently,
>> the SBSA (section 4.3.2 in ARM-DEN-0029 v2.3) states the PL011 is
>> implemented with a level triggered interrupt.
>>
>> So the driver should configure the interrupt as high level triggered.
>>
>> Signed-off-by: Julien Grall <julien.grall@arm.com>
> 
> Shannon, Stefano,
> 
> Please reply whether you are OK with this patch. Thanks!

Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

>>
>> ---
>>     Changes in v2:
>>         - Update the commit message
>>         - Effictively configure the interrupt high level triggered
>> ---
>>  xen/drivers/char/pl011.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
>> index fa22edf..1212d5c 100644
>> --- a/xen/drivers/char/pl011.c
>> +++ b/xen/drivers/char/pl011.c
>> @@ -327,7 +327,7 @@ static int __init pl011_acpi_uart_init(const void *data)
>>      }
>>  
>>      /* trigger/polarity information is not available in spcr */
>> -    irq_set_type(spcr->interrupt, IRQ_TYPE_EDGE_BOTH);
>> +    irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH);
>>  
>>      res = pl011_uart_init(spcr->interrupt, spcr->serial_port.address,
>>                            PAGE_SIZE);
>> -- 
>> 1.9.1
>>
>>
>> _______________________________________________
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>> Xen-devel@lists.xen.org
>> http://lists.xen.org/xen-devel
> 
> _______________________________________________
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> 

-- 
Shannon


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Re: [for-4.7 v2 1/5] drivers/pl011: ACPI: The interrupt should always be high level triggered

[Konrad Rzeszutek Wilk]

On Tue, Apr 12, 2016 at 09:00:42AM +0800, Shannon Zhao wrote:
> 
> 
> On 2016/4/11 22:07, Konrad Rzeszutek Wilk wrote:
> > On Mon, Apr 11, 2016 at 02:33:33PM +0100, Julien Grall wrote:
> >> The SPCR does not specify if the interrupt is edge or level triggered.
> >> So the configuration needs to be hardcoded in the code.
> >>
> >> Based on the PL011 TRM (see 2.2.8 in ARM DDI 0183G), the interrupt generated
> >> will be active high. Whilst the wording may be interpreted differently,
> >> the SBSA (section 4.3.2 in ARM-DEN-0029 v2.3) states the PL011 is
> >> implemented with a level triggered interrupt.
> >>
> >> So the driver should configure the interrupt as high level triggered.
> >>
> >> Signed-off-by: Julien Grall <julien.grall@arm.com>
> > 
> > Shannon, Stefano,
> > 
> > Please reply whether you are OK with this patch. Thanks!
> 
> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>

Thanks. applied.

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