From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Manuel Bouyer <bouyer@antioche.eu.org>, <xen-devel@lists.xenproject.org>
Subject: Re: NetBSD dom0 PVH: hardware interrupts stalls
Date: Tue, 24 Nov 2020 13:21:02 +0100 [thread overview]
Message-ID: <20201124122102.3igsriesou3vl6mu@Air-de-Roger> (raw)
In-Reply-To: <b3912e97-9684-fe97-1053-ad7168a19721@suse.com>
On Tue, Nov 24, 2020 at 11:05:12AM +0100, Jan Beulich wrote:
> On 23.11.2020 18:39, Manuel Bouyer wrote:
> > On Mon, Nov 23, 2020 at 06:06:10PM +0100, Roger Pau Monné wrote:
> >> OK, I'm afraid this is likely too verbose and messes with the timings.
> >>
> >> I've been looking (again) into the code, and I found something weird
> >> that I think could be related to the issue you are seeing, but haven't
> >> managed to try to boot the NetBSD kernel provided in order to assert
> >> whether it solves the issue or not (or even whether I'm able to
> >> repro it). Would you mind giving the patch below a try?
> >
> > With this, I get the same hang but XEN outputs don't wake up the interrupt
> > any more. The NetBSD counter shows only one interrupt for ioapic2 pin 2,
> > while I would have about 8 at the time of the hang.
> >
> > So, now it looks like interrupts are blocked forever.
>
> Which may be a good thing for debugging purposes, because now we have
> a way to investigate what is actually blocking the interrupt's
> delivery without having to worry about more output screwing the
> overall picture.
>
> > At
> > http://www-soc.lip6.fr/~bouyer/xen-log5.txt
> > you'll find the output of the 'i' key.
>
> (XEN) IRQ: 34 vec:59 IO-APIC-level status=010 aff:{0}/{0-7} in-flight=1 d0: 34(-MM)
>
> (XEN) IRQ 34 Vec 89:
> (XEN) Apic 0x02, Pin 2: vec=59 delivery=LoPri dest=L status=1 polarity=1 irr=1 trig=L mask=0 dest_id:00000001
>
> (XEN) ioapic 2 pin 2 gsi 34 vector 0x67
> (XEN) delivery mode 0 dest mode 0 delivery status 0
> (XEN) polarity 1 IRR 0 trig mode 1 mask 0 dest id 0
>
> IOW from guest pov the interrupt is entirely idle (mask and irr clear),
> while Xen sees it as both in-flight and irr also already having become
> set again. I continue to suspect the EOI timer not doing its job. Yet
> as said before, for it to have to do anything in the first place the
> "guest" (really Dom0 here) would need to fail to EOI the IRQ within
> the timeout period. Which in turn, given your description of how you
> handle interrupts, cannot be excluded (i.e. the handling may simply
> take "slightly" too long).
I've tried to force some of those scenarios myself by modifying the
code, and didn't seem to be able to trigger the same scenario. I guess
the NetBSD case is slightly difficult to recreate.
> What we're missing is LAPIC information, since the masked status logged
> is unclear: (-MM) isn't fully matching up with "mask=0". But of course
> the former is just a software representation, while the latter is what
> the RTE holds. IOW for the interrupt to not get delivered, there needs
> to be this or a higher ISR bit set (considering we don't use the TPR),
> or (I think we can pretty much exclude this) we'd need to be running
> with IRQs off for extended periods of time.
Let's dump the physical lapic(s) IRR and ISR together with the
IO-APIC state. Can you please apply the following patch and use the
'i' key again? (please keep the previous patch applied)
Thanks, Roger.
---8<---
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 60627fd6e6..c33d682b69 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -1547,3 +1547,24 @@ void check_for_unexpected_msi(unsigned int vector)
{
BUG_ON(apic_isr_read(vector));
}
+
+static DEFINE_SPINLOCK(dump_lock);
+void dump_lapic(void *unused)
+{
+ unsigned int i;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dump_lock, flags);
+ printk("CPU %u APIC ID %u\n", smp_processor_id(), apic_read(APIC_ID));
+
+ printk("IRR ");
+ for ( i = APIC_ISR_NR - 1; i-- > 0; )
+ printk("%08x", apic_read(APIC_ISR + i*0x10));
+
+ printk("\nISR ");
+ for ( i = APIC_ISR_NR - 1; i-- > 0; )
+ printk("%08x", apic_read(APIC_IRR + i*0x10));
+ printk("\n");
+
+ spin_unlock_irqrestore(&dump_lock, flags);
+}
diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index e66fa99ec7..92edb3000a 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -2470,6 +2470,7 @@ static const char * delivery_mode_2_str(
}
}
+void dump_lapic(void *unused);
void dump_ioapic_irq_info(void)
{
struct irq_pin_list *entry;
@@ -2516,6 +2517,9 @@ void dump_ioapic_irq_info(void)
entry = &irq_2_pin[entry->next];
}
}
+
+ dump_lapic(NULL);
+ smp_call_function(dump_lapic, NULL, true);
}
static unsigned int __initdata max_gsi_irqs;
next prev parent reply other threads:[~2020-11-24 12:21 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-17 15:09 NetBSD dom0 PVH: hardware interrupts stalls Manuel Bouyer
2020-11-17 15:58 ` Roger Pau Monné
2020-11-17 16:40 ` Manuel Bouyer
2020-11-18 8:57 ` Roger Pau Monné
2020-11-18 9:24 ` Manuel Bouyer
2020-11-18 10:00 ` Roger Pau Monné
2020-11-18 12:14 ` Manuel Bouyer
2020-11-18 14:39 ` Roger Pau Monné
2020-11-18 14:59 ` Jan Beulich
2020-11-19 14:19 ` Roger Pau Monné
2020-11-19 15:57 ` Manuel Bouyer
2020-11-19 16:57 ` Manuel Bouyer
2020-11-19 17:57 ` Manuel Bouyer
2020-11-20 8:09 ` Jan Beulich
2020-11-20 8:28 ` Roger Pau Monné
2020-11-20 8:52 ` Manuel Bouyer
2020-11-20 8:59 ` Jan Beulich
2020-11-20 9:27 ` Manuel Bouyer
2020-11-20 10:00 ` Jan Beulich
2020-11-20 10:38 ` Manuel Bouyer
2020-11-23 9:57 ` Roger Pau Monné
2020-11-23 11:32 ` Manuel Bouyer
2020-11-23 12:51 ` Roger Pau Monné
2020-11-23 14:31 ` Manuel Bouyer
2020-11-23 17:06 ` Roger Pau Monné
2020-11-23 17:39 ` Manuel Bouyer
2020-11-24 10:05 ` Jan Beulich
2020-11-24 12:21 ` Roger Pau Monné [this message]
2020-11-24 13:59 ` Manuel Bouyer
2020-11-24 14:09 ` Jan Beulich
2020-11-24 14:27 ` Manuel Bouyer
2020-11-24 14:33 ` Jan Beulich
2020-11-24 14:36 ` Jan Beulich
2020-11-24 14:52 ` Jan Beulich
2020-11-24 15:00 ` Roger Pau Monné
2020-11-24 15:08 ` Manuel Bouyer
2020-11-24 15:49 ` Roger Pau Monné
2020-11-24 16:09 ` Manuel Bouyer
2020-11-26 13:34 ` Roger Pau Monné
2020-11-26 14:16 ` Manuel Bouyer
2020-11-26 14:26 ` Roger Pau Monné
2020-11-26 15:09 ` Roger Pau Monné
2020-11-26 17:20 ` Manuel Bouyer
2020-11-27 10:59 ` Roger Pau Monné
2020-11-27 11:18 ` Jan Beulich
2020-11-27 11:19 ` Manuel Bouyer
2020-11-27 11:21 ` Jan Beulich
2020-11-27 13:10 ` Manuel Bouyer
2020-11-27 13:14 ` Jan Beulich
2020-11-27 13:18 ` Manuel Bouyer
2020-11-27 11:29 ` Jan Beulich
2020-11-27 13:13 ` Manuel Bouyer
2020-11-27 13:18 ` Jan Beulich
2020-11-27 13:31 ` Manuel Bouyer
2020-11-27 13:40 ` Jan Beulich
2020-11-27 13:49 ` Jürgen Groß
2020-11-27 13:59 ` Manuel Bouyer
2020-11-27 20:22 ` Roger Pau Monné
2020-11-27 21:44 ` Manuel Bouyer
2020-11-28 14:53 ` Roger Pau Monné
2020-11-28 17:14 ` Manuel Bouyer
2020-11-29 9:23 ` Manuel Bouyer
2020-11-30 10:00 ` Jan Beulich
2020-11-30 10:28 ` Manuel Bouyer
2020-11-30 11:35 ` Manuel Bouyer
2020-11-30 11:44 ` Jan Beulich
2020-11-30 11:50 ` Manuel Bouyer
2020-11-30 12:09 ` Jan Beulich
2020-11-24 14:42 ` Jan Beulich
2020-11-24 14:59 ` Roger Pau Monné
2020-11-24 15:18 ` Manuel Bouyer
2020-11-24 15:23 ` Jürgen Groß
2020-11-20 8:54 ` Jan Beulich
2020-11-20 9:13 ` Manuel Bouyer
2020-11-23 9:49 ` Roger Pau Monné
2020-11-18 15:03 ` Manuel Bouyer
2020-11-18 9:16 ` Jan Beulich
2020-11-18 9:28 ` Manuel Bouyer
2020-11-18 9:43 ` Jan Beulich
2020-11-18 10:14 ` Manuel Bouyer
2020-11-18 11:17 ` Jan Beulich
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