From: "Michał Leszczyński" <michal.leszczynski@cert.pl>
To: Xen-devel <xen-devel@lists.xenproject.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
"Wei Liu" <wl@xen.org>, "Jan Beulich" <jbeulich@suse.com>,
"Roger Pau Monné" <roger.pau@citrix.com>
Subject: [PATCH v1 1/7] x86/vmx: add Intel PT MSR definitions
Date: Tue, 16 Jun 2020 17:19:49 +0200 (CEST) [thread overview]
Message-ID: <2141998496.8765382.1592320789155.JavaMail.zimbra@cert.pl> (raw)
In-Reply-To: <1548605014.8764792.1592320576239.JavaMail.zimbra@cert.pl>
Define constants related to Intel Processor Trace features.
Signed-off-by: Michal Leszczynski <michal.leszczynski@cert.pl>
---
xen/include/asm-x86/msr-index.h | 37 +++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index b328a47ed8..ecf0dd8bab 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -621,4 +621,41 @@
#define MSR_PKGC9_IRTL 0x00000634
#define MSR_PKGC10_IRTL 0x00000635
+/* Intel PT MSRs */
+#define MSR_IA32_RTIT_CTL 0x00000570
+#define RTIT_CTL_TRACEEN (1ULL << 0)
+#define RTIT_CTL_CYCEN (1ULL << 1)
+#define RTIT_CTL_OS (1ULL << 2)
+#define RTIT_CTL_USR (1ULL << 3)
+#define RTIT_CTL_PWR_EVT_EN (1ULL << 4)
+#define RTIT_CTL_FUP_ON_PTW (1ULL << 5)
+#define RTIT_CTL_FABRIC_EN (1ULL << 6)
+#define RTIT_CTL_CR3_FILTER (1ULL << 7)
+#define RTIT_CTL_TOPA (1ULL << 8)
+#define RTIT_CTL_MTC_EN (1ULL << 9)
+#define RTIT_CTL_TSC_EN (1ULL << 10)
+#define RTIT_CTL_DIS_RETC (1ULL << 11)
+#define RTIT_CTL_PTW_EN (1ULL << 12)
+#define RTIT_CTL_BRANCH_EN (1ULL << 13)
+#define RTIT_CTL_MTC_FREQ_OFFSET 14
+#define RTIT_CTL_MTC_FREQ (0x0fULL << RTIT_CTL_MTC_FREQ_OFFSET)
+#define RTIT_CTL_CYC_THRESH_OFFSET 19
+#define RTIT_CTL_CYC_THRESH (0x0fULL << RTIT_CTL_CYC_THRESH_OFFSET)
+#define RTIT_CTL_PSB_FREQ_OFFSET 24
+#define RTIT_CTL_PSB_FREQ (0x0fULL << RTIT_CTL_PSB_FREQ_OFFSET)
+#define RTIT_CTL_ADDR_OFFSET(n) (32 + 4 * (n))
+#define RTIT_CTL_ADDR(n) (0x0fULL << RTIT_CTL_ADDR_OFFSET(n))
+#define MSR_IA32_RTIT_STATUS 0x00000571
+#define RTIT_STATUS_FILTER_EN (1ULL << 0)
+#define RTIT_STATUS_CONTEXT_EN (1ULL << 1)
+#define RTIT_STATUS_TRIGGER_EN (1ULL << 2)
+#define RTIT_STATUS_ERROR (1ULL << 4)
+#define RTIT_STATUS_STOPPED (1ULL << 5)
+#define RTIT_STATUS_BYTECNT (0x1ffffULL << 32)
+#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
+#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
+#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
+#define MSR_IA32_RTIT_ADDR_A(n) (0x00000580 + (n) * 2)
+#define MSR_IA32_RTIT_ADDR_B(n) (0x00000581 + (n) * 2)
+
#endif /* __ASM_MSR_INDEX_H */
--
2.20.1
next prev parent reply other threads:[~2020-06-16 15:20 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 15:16 [PATCH v1 0/7] Implement support for external IPT monitoring Michał Leszczyński
2020-06-16 15:19 ` Michał Leszczyński [this message]
2020-06-18 13:31 ` [PATCH v1 1/7] x86/vmx: add Intel PT MSR definitions Jan Beulich
2020-06-16 15:20 ` [PATCH v1 2/7] x86/vmx: add IPT cpu feature Michał Leszczyński
2020-06-16 16:30 ` Roger Pau Monné
2020-06-17 11:34 ` Jan Beulich
2020-06-16 15:21 ` [PATCH v1 3/7] x86/vmx: add ipt_state as part of vCPU state Michał Leszczyński
2020-06-16 16:33 ` Roger Pau Monné
2020-06-16 15:22 ` [PATCH v1 4/7] x86/vmx: add do_vmtrace_op Michał Leszczyński
2020-06-16 17:23 ` Roger Pau Monné
2020-06-17 19:13 ` Michał Leszczyński
2020-06-18 3:20 ` Tamas K Lengyel
2020-06-18 11:01 ` Michał Leszczyński
2020-06-18 11:55 ` Roger Pau Monné
2020-06-18 12:51 ` Jan Beulich
2020-06-18 13:09 ` Michał Leszczyński
2020-06-18 13:24 ` Jan Beulich
2020-06-18 13:40 ` Roger Pau Monné
2020-06-18 8:46 ` Roger Pau Monné
2020-06-18 15:25 ` Michał Leszczyński
2020-06-18 15:39 ` Jan Beulich
2020-06-18 15:47 ` Tamas K Lengyel
2020-06-18 15:49 ` Tamas K Lengyel
2020-06-16 15:22 ` [PATCH v1 5/7] tools/libxc: add xc_ptbuf_* functions Michał Leszczyński
2020-06-16 15:23 ` [PATCH v1 6/7] tools/proctrace: add proctrace tool Michał Leszczyński
2020-06-16 15:24 ` [PATCH v1 7/7] x86/vmx: switch IPT MSRs on vmentry/vmexit Michał Leszczyński
2020-06-16 17:38 ` Roger Pau Monné
2020-06-16 17:47 ` Michał Leszczyński
2020-06-17 9:09 ` Roger Pau Monné
2020-06-17 11:54 ` Michał Leszczyński
2020-06-17 12:51 ` Roger Pau Monné
2020-06-17 15:14 ` Andrew Cooper
2020-06-17 18:56 ` Michał Leszczyński
2020-06-18 8:52 ` Roger Pau Monné
2020-06-18 11:07 ` Michał Leszczyński
2020-06-18 11:49 ` Roger Pau Monné
2020-06-17 23:30 ` Kang, Luwei
2020-06-18 10:02 ` Andrew Cooper
2020-06-18 17:38 ` Andrew Cooper
2020-06-16 18:17 ` [PATCH v1 0/7] Implement support for external IPT monitoring Andrew Cooper
2020-06-16 18:47 ` Michał Leszczyński
2020-06-16 20:16 ` Andrew Cooper
2020-06-17 3:02 ` Tamas K Lengyel
2020-06-17 16:19 ` Andrew Cooper
2020-06-17 16:27 ` Tamas K Lengyel
2020-06-17 17:23 ` Andrew Cooper
2020-06-17 19:31 ` Tamas K Lengyel
2020-06-17 19:30 ` Michał Leszczyński
2020-06-17 20:20 ` Michał Leszczyński
2020-06-18 8:25 ` Roger Pau Monné
2020-06-18 14:59 ` Michał Leszczyński
2020-06-17 1:35 ` Tian, Kevin
2020-06-17 6:45 ` Kang, Luwei
2020-06-17 9:21 ` Roger Pau Monné
2020-06-17 12:37 ` Kang, Luwei
2020-06-17 12:53 ` Roger Pau Monné
2020-06-17 23:29 ` Kang, Luwei
2020-06-18 0:56 ` Michał Leszczyński
2020-06-18 7:00 ` Roger Pau Monné
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